src/arm/bcm63148.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2022 Broadcom Ltd.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8
   9 / {
  10         compatible = "brcm,bcm63148", "brcm,bcmbca";
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         interrupt-parent = <&gic>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 B15_0: cpu@0 {
  21                         device_type = "cpu";
  22                         compatible = "brcm,brahma-b15";
  23                         reg = <0x0>;
  24                         next-level-cache = <&L2_0>;
  25                         enable-method = "psci";
  26                 };
  27
  28                 B15_1: cpu@1 {
  29                         device_type = "cpu";
  30                         compatible = "brcm,brahma-b15";
  31                         reg = <0x1>;
  32                         next-level-cache = <&L2_0>;
  33                         enable-method = "psci";
  34                 };
  35
  36                 L2_0: l2-cache0 {
  37                         compatible = "cache";
  38                         cache-level = <2>;
  39                 };
  40         };
  41
  42         timer {
  43                 compatible = "arm,armv7-timer";
  44                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  45                         <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  46                         <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  47                         <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  48         };
  49
  50         pmu: pmu {
  51                 compatible = "arm,cortex-a15-pmu";
  52                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
  53                         <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  54                 interrupt-affinity = <&B15_0>, <&B15_1>;
  55         };
  56
  57         clocks: clocks {
  58                 periph_clk: periph-clk {
  59                         compatible = "fixed-clock";
  60                         #clock-cells = <0>;
  61                         clock-frequency = <50000000>;
  62                 };
  63
  64                 hsspi_pll: hsspi-pll {
  65                         compatible = "fixed-clock";
  66                         #clock-cells = <0>;
  67                         clock-frequency = <400000000>;
  68                 };
  69         };
  70
  71         psci {
  72                 compatible = "arm,psci-0.2";
  73                 method = "smc";
  74         };
  75
  76         axi@80030000 {
  77                 compatible = "simple-bus";
  78                 #address-cells = <1>;
  79                 #size-cells = <1>;
  80                 ranges = <0 0x80030000 0x8000>;
  81
  82                 gic: interrupt-controller@1000 {
  83                         compatible = "arm,cortex-a15-gic";
  84                         #interrupt-cells = <3>;
  85                         interrupt-controller;
  86                         reg = <0x1000 0x1000>,
  87                                 <0x2000 0x2000>,
  88                                 <0x4000 0x2000>,
  89                                 <0x6000 0x2000>;
  90                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
  91                                         IRQ_TYPE_LEVEL_HIGH)>;
  92                 };
  93         };
  94
  95         bus@ff800000 {
  96                 compatible = "simple-bus";
  97                 #address-cells = <1>;
  98                 #size-cells = <1>;
  99                 ranges = <0 0xfffe8000 0x8000>;
 100
 101                 uart0: serial@600 {
 102                         compatible = "brcm,bcm6345-uart";
 103                         reg = <0x600 0x20>;
 104                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 105                         clocks = <&periph_clk>;
 106                         clock-names = "refclk";
 107                         status = "disabled";
 108                 };
 109
 110                 hsspi: spi@1000 {
 111                         #address-cells = <1>;
 112                         #size-cells = <0>;
 113                         compatible = "brcm,bcm63148-hsspi", "brcm,bcmbca-hsspi-v1.0";
 114                         reg = <0x1000 0x600>;
 115                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 116                         clocks = <&hsspi_pll &hsspi_pll>;
 117                         clock-names = "hsspi", "pll";
 118                         num-cs = <8>;
 119                         status = "disabled";
 120                 };
 121         };
 122 };