src/arm/dra74x.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
   4  *
   5  * Based on "omap4.dtsi"
   6  */
   7
   8 #include "dra7.dtsi"
   9
  10 / {
  11         compatible = "ti,dra742", "ti,dra74", "ti,dra7";
  12
  13         cpus {
  14                 cpu@1 {
  15                         device_type = "cpu";
  16                         compatible = "arm,cortex-a15";
  17                         reg = <1>;
  18                         operating-points-v2 = <&cpu0_opp_table>;
  19
  20                         clocks = <&dpll_mpu_ck>;
  21                         clock-names = "cpu";
  22
  23                         clock-latency = <300000>; /* From omap-cpufreq driver */
  24
  25                         /* cooling options */
  26                         #cooling-cells = <2>; /* min followed by max */
  27
  28                         vbb-supply = <&abb_mpu>;
  29                 };
  30         };
  31
  32         aliases {
  33                 rproc0 = &ipu1;
  34                 rproc1 = &ipu2;
  35                 rproc2 = &dsp1;
  36                 rproc3 = &dsp2;
  37         };
  38
  39         pmu {
  40                 compatible = "arm,cortex-a15-pmu";
  41                 interrupt-parent = <&wakeupgen>;
  42                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  43                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
  44         };
  45
  46         ocp {
  47                 dsp2_system: dsp_system@41500000 {
  48                         compatible = "syscon";
  49                         reg = <0x41500000 0x100>;
  50                 };
  51
  52                 omap_dwc3_4: omap_dwc3_4@48940000 {
  53                         compatible = "ti,dwc3";
  54                         ti,hwmods = "usb_otg_ss4";
  55                         reg = <0x48940000 0x10000>;
  56                         interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
  57                         #address-cells = <1>;
  58                         #size-cells = <1>;
  59                         utmi-mode = <2>;
  60                         ranges;
  61                         status = "disabled";
  62                         usb4: usb@48950000 {
  63                                 compatible = "snps,dwc3";
  64                                 reg = <0x48950000 0x17000>;
  65                                 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
  66                                              <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
  67                                              <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
  68                                 interrupt-names = "peripheral",
  69                                                   "host",
  70                                                   "otg";
  71                                 maximum-speed = "high-speed";
  72                                 dr_mode = "otg";
  73                         };
  74                 };
  75
  76                 target-module@41501000 {
  77                         compatible = "ti,sysc-omap2", "ti,sysc";
  78                         reg = <0x41501000 0x4>,
  79                               <0x41501010 0x4>,
  80                               <0x41501014 0x4>;
  81                         reg-names = "rev", "sysc", "syss";
  82                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  83                                         <SYSC_IDLE_NO>,
  84                                         <SYSC_IDLE_SMART>;
  85                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  86                                          SYSC_OMAP2_SOFTRESET |
  87                                          SYSC_OMAP2_AUTOIDLE)>;
  88                         clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
  89                         clock-names = "fck";
  90                         resets = <&prm_dsp2 1>;
  91                         reset-names = "rstctrl";
  92                         ranges = <0x0 0x41501000 0x1000>;
  93                         #size-cells = <1>;
  94                         #address-cells = <1>;
  95
  96                         mmu0_dsp2: mmu@0 {
  97                                 compatible = "ti,dra7-dsp-iommu";
  98                                 reg = <0x0 0x100>;
  99                                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 100                                 #iommu-cells = <0>;
 101                                 ti,syscon-mmuconfig = <&dsp2_system 0x0>;
 102                         };
 103                 };
 104
 105                 target-module@41502000 {
 106                         compatible = "ti,sysc-omap2", "ti,sysc";
 107                         reg = <0x41502000 0x4>,
 108                               <0x41502010 0x4>,
 109                               <0x41502014 0x4>;
 110                         reg-names = "rev", "sysc", "syss";
 111                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 112                                         <SYSC_IDLE_NO>,
 113                                         <SYSC_IDLE_SMART>;
 114                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 115                                          SYSC_OMAP2_SOFTRESET |
 116                                          SYSC_OMAP2_AUTOIDLE)>;
 117
 118                         clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
 119                         clock-names = "fck";
 120                         resets = <&prm_dsp2 1>;
 121                         reset-names = "rstctrl";
 122                         ranges = <0x0 0x41502000 0x1000>;
 123                         #size-cells = <1>;
 124                         #address-cells = <1>;
 125
 126                         mmu1_dsp2: mmu@0 {
 127                                 compatible = "ti,dra7-dsp-iommu";
 128                                 reg = <0x0 0x100>;
 129                                 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 130                                 #iommu-cells = <0>;
 131                                 ti,syscon-mmuconfig = <&dsp2_system 0x1>;
 132                         };
 133                 };
 134
 135                 dsp2: dsp@41000000 {
 136                         compatible = "ti,dra7-dsp";
 137                         reg = <0x41000000 0x48000>,
 138                               <0x41600000 0x8000>,
 139                               <0x41700000 0x8000>;
 140                         reg-names = "l2ram", "l1pram", "l1dram";
 141                         ti,bootreg = <&scm_conf 0x560 10>;
 142                         iommus = <&mmu0_dsp2>, <&mmu1_dsp2>;
 143                         status = "disabled";
 144                         resets = <&prm_dsp2 0>;
 145                         clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
 146                         firmware-name = "dra7-dsp2-fw.xe66";
 147                 };
 148         };
 149 };
 150
 151 &cpu0_opp_table {
 152         opp-shared;
 153 };
 154
 155 &dss {
 156         reg = <0 0x80>,
 157               <0x4054 0x4>,
 158               <0x4300 0x20>,
 159               <0x9054 0x4>,
 160               <0x9300 0x20>;
 161         reg-names = "dss", "pll1_clkctrl", "pll1",
 162                     "pll2_clkctrl", "pll2";
 163
 164         clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
 165                  <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>,
 166                  <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 13>;
 167         clock-names = "fck", "video1_clk", "video2_clk";
 168 };
 169
 170 &mailbox5 {
 171         mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
 172                 ti,mbox-tx = <6 2 2>;
 173                 ti,mbox-rx = <4 2 2>;
 174                 status = "disabled";
 175         };
 176         mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
 177                 ti,mbox-tx = <5 2 2>;
 178                 ti,mbox-rx = <1 2 2>;
 179                 status = "disabled";
 180         };
 181 };
 182
 183 &mailbox6 {
 184         mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
 185                 ti,mbox-tx = <6 2 2>;
 186                 ti,mbox-rx = <4 2 2>;
 187                 status = "disabled";
 188         };
 189         mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
 190                 ti,mbox-tx = <5 2 2>;
 191                 ti,mbox-rx = <1 2 2>;
 192                 status = "disabled";
 193         };
 194 };
 195
 196 &pcie1_rc {
 197         compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
 198 };
 199
 200 &pcie1_ep {
 201         compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep";
 202 };
 203
 204 &pcie2_rc {
 205         compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
 206 };