src/arm/exynos3250.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Samsung's Exynos3250 SoC device tree source
   4  *
   5  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  *
   8  * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
   9  * based board files can include this file and provide values for board specfic
  10  * bindings.
  11  *
  12  * Note: This file does not include device nodes for all the controllers in
  13  * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
  14  * nodes can be added to this file.
  15  */
  16
  17 #include "exynos4-cpu-thermal.dtsi"
  18 #include <dt-bindings/clock/exynos3250.h>
  19 #include <dt-bindings/interrupt-controller/arm-gic.h>
  20 #include <dt-bindings/interrupt-controller/irq.h>
  21
  22 / {
  23         compatible = "samsung,exynos3250";
  24         interrupt-parent = <&gic>;
  25         #address-cells = <1>;
  26         #size-cells = <1>;
  27
  28         aliases {
  29                 pinctrl0 = &pinctrl_0;
  30                 pinctrl1 = &pinctrl_1;
  31                 mshc0 = &mshc_0;
  32                 mshc1 = &mshc_1;
  33                 mshc2 = &mshc_2;
  34                 spi0 = &spi_0;
  35                 spi1 = &spi_1;
  36                 i2c0 = &i2c_0;
  37                 i2c1 = &i2c_1;
  38                 i2c2 = &i2c_2;
  39                 i2c3 = &i2c_3;
  40                 i2c4 = &i2c_4;
  41                 i2c5 = &i2c_5;
  42                 i2c6 = &i2c_6;
  43                 i2c7 = &i2c_7;
  44                 serial0 = &serial_0;
  45                 serial1 = &serial_1;
  46                 serial2 = &serial_2;
  47         };
  48
  49         cpus {
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52
  53                 cpu0: cpu@0 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a7";
  56                         reg = <0>;
  57                         clock-frequency = <1000000000>;
  58                         clocks = <&cmu CLK_ARM_CLK>;
  59                         clock-names = "cpu";
  60                         #cooling-cells = <2>;
  61
  62                         operating-points = <
  63                                 1000000 1150000
  64                                 900000  1112500
  65                                 800000  1075000
  66                                 700000  1037500
  67                                 600000  1000000
  68                                 500000  962500
  69                                 400000  925000
  70                                 300000  887500
  71                                 200000  850000
  72                                 100000  850000
  73                         >;
  74                 };
  75
  76                 cpu1: cpu@1 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a7";
  79                         reg = <1>;
  80                         clock-frequency = <1000000000>;
  81                 };
  82         };
  83
  84         soc: soc {
  85                 compatible = "simple-bus";
  86                 #address-cells = <1>;
  87                 #size-cells = <1>;
  88                 ranges;
  89
  90                 fixed-rate-clocks {
  91                         #address-cells = <1>;
  92                         #size-cells = <0>;
  93
  94                         xusbxti: clock@0 {
  95                                 compatible = "fixed-clock";
  96                                 #address-cells = <1>;
  97                                 #size-cells = <0>;
  98                                 reg = <0>;
  99                                 clock-frequency = <0>;
 100                                 #clock-cells = <0>;
 101                                 clock-output-names = "xusbxti";
 102                         };
 103
 104                         xxti: clock@1 {
 105                                 compatible = "fixed-clock";
 106                                 reg = <1>;
 107                                 clock-frequency = <0>;
 108                                 #clock-cells = <0>;
 109                                 clock-output-names = "xxti";
 110                         };
 111
 112                         xtcxo: clock@2 {
 113                                 compatible = "fixed-clock";
 114                                 reg = <2>;
 115                                 clock-frequency = <0>;
 116                                 #clock-cells = <0>;
 117                                 clock-output-names = "xtcxo";
 118                         };
 119                 };
 120
 121                 sysram@2020000 {
 122                         compatible = "mmio-sram";
 123                         reg = <0x02020000 0x40000>;
 124                         #address-cells = <1>;
 125                         #size-cells = <1>;
 126                         ranges = <0 0x02020000 0x40000>;
 127
 128                         smp-sysram@0 {
 129                                 compatible = "samsung,exynos4210-sysram";
 130                                 reg = <0x0 0x1000>;
 131                         };
 132
 133                         smp-sysram@3f000 {
 134                                 compatible = "samsung,exynos4210-sysram-ns";
 135                                 reg = <0x3f000 0x1000>;
 136                         };
 137                 };
 138
 139                 chipid@10000000 {
 140                         compatible = "samsung,exynos4210-chipid";
 141                         reg = <0x10000000 0x100>;
 142                 };
 143
 144                 sys_reg: syscon@10010000 {
 145                         compatible = "samsung,exynos3-sysreg", "syscon";
 146                         reg = <0x10010000 0x400>;
 147                 };
 148
 149                 pmu_system_controller: system-controller@10020000 {
 150                         compatible = "samsung,exynos3250-pmu", "syscon";
 151                         reg = <0x10020000 0x4000>;
 152                         interrupt-controller;
 153                         #interrupt-cells = <3>;
 154                         interrupt-parent = <&gic>;
 155                 };
 156
 157                 mipi_phy: video-phy {
 158                         compatible = "samsung,s5pv210-mipi-video-phy";
 159                         #phy-cells = <1>;
 160                         syscon = <&pmu_system_controller>;
 161                 };
 162
 163                 pd_cam: power-domain@10023c00 {
 164                         compatible = "samsung,exynos4210-pd";
 165                         reg = <0x10023C00 0x20>;
 166                         #power-domain-cells = <0>;
 167                         label = "CAM";
 168                 };
 169
 170                 pd_mfc: power-domain@10023c40 {
 171                         compatible = "samsung,exynos4210-pd";
 172                         reg = <0x10023C40 0x20>;
 173                         #power-domain-cells = <0>;
 174                         label = "MFC";
 175                 };
 176
 177                 pd_g3d: power-domain@10023c60 {
 178                         compatible = "samsung,exynos4210-pd";
 179                         reg = <0x10023C60 0x20>;
 180                         #power-domain-cells = <0>;
 181                         label = "G3D";
 182                 };
 183
 184                 pd_lcd0: power-domain@10023c80 {
 185                         compatible = "samsung,exynos4210-pd";
 186                         reg = <0x10023C80 0x20>;
 187                         #power-domain-cells = <0>;
 188                         label = "LCD0";
 189                 };
 190
 191                 pd_isp: power-domain@10023ca0 {
 192                         compatible = "samsung,exynos4210-pd";
 193                         reg = <0x10023CA0 0x20>;
 194                         #power-domain-cells = <0>;
 195                         label = "ISP";
 196                 };
 197
 198                 cmu: clock-controller@10030000 {
 199                         compatible = "samsung,exynos3250-cmu";
 200                         reg = <0x10030000 0x20000>;
 201                         #clock-cells = <1>;
 202                         assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
 203                                           <&cmu CLK_MOUT_ACLK_266_SUB>;
 204                         assigned-clock-parents = <&cmu CLK_FIN_PLL>,
 205                                                  <&cmu CLK_FIN_PLL>;
 206                 };
 207
 208                 cmu_dmc: clock-controller@105c0000 {
 209                         compatible = "samsung,exynos3250-cmu-dmc";
 210                         reg = <0x105C0000 0x2000>;
 211                         #clock-cells = <1>;
 212                 };
 213
 214                 rtc: rtc@10070000 {
 215                         compatible = "samsung,s3c6410-rtc";
 216                         reg = <0x10070000 0x100>;
 217                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 218                                      <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 219                         interrupt-parent = <&pmu_system_controller>;
 220                         status = "disabled";
 221                 };
 222
 223                 tmu: tmu@100c0000 {
 224                         compatible = "samsung,exynos3250-tmu";
 225                         reg = <0x100C0000 0x100>;
 226                         interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 227                         clocks = <&cmu CLK_TMU_APBIF>;
 228                         clock-names = "tmu_apbif";
 229                         #include "exynos4412-tmu-sensor-conf.dtsi"
 230                         status = "disabled";
 231                 };
 232
 233                 gic: interrupt-controller@10481000 {
 234                         compatible = "arm,cortex-a15-gic";
 235                         #interrupt-cells = <3>;
 236                         interrupt-controller;
 237                         reg = <0x10481000 0x1000>,
 238                               <0x10482000 0x2000>,
 239                               <0x10484000 0x2000>,
 240                               <0x10486000 0x2000>;
 241                         interrupts = <GIC_PPI 9
 242                                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 243                 };
 244
 245                 mct@10050000 {
 246                         compatible = "samsung,exynos4210-mct";
 247                         reg = <0x10050000 0x800>;
 248                         interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
 249                                      <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
 250                                      <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
 251                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
 252                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
 253                                      <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
 254                                      <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
 255                                      <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
 256                         clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
 257                         clock-names = "fin_pll", "mct";
 258                 };
 259
 260                 pinctrl_1: pinctrl@11000000 {
 261                         compatible = "samsung,exynos3250-pinctrl";
 262                         reg = <0x11000000 0x1000>;
 263                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 264
 265                         wakeup-interrupt-controller {
 266                                 compatible = "samsung,exynos4210-wakeup-eint";
 267                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 268                         };
 269                 };
 270
 271                 pinctrl_0: pinctrl@11400000 {
 272                         compatible = "samsung,exynos3250-pinctrl";
 273                         reg = <0x11400000 0x1000>;
 274                         interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 275                 };
 276
 277                 jpeg: codec@11830000 {
 278                         compatible = "samsung,exynos3250-jpeg";
 279                         reg = <0x11830000 0x1000>;
 280                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 281                         clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
 282                         clock-names = "jpeg", "sclk";
 283                         power-domains = <&pd_cam>;
 284                         assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
 285                         assigned-clock-rates = <0>, <150000000>;
 286                         assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
 287                         iommus = <&sysmmu_jpeg>;
 288                         status = "disabled";
 289                 };
 290
 291                 sysmmu_jpeg: sysmmu@11a60000 {
 292                         compatible = "samsung,exynos-sysmmu";
 293                         reg = <0x11a60000 0x1000>;
 294                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
 295                                      <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 296                         clock-names = "sysmmu", "master";
 297                         clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
 298                         power-domains = <&pd_cam>;
 299                         #iommu-cells = <0>;
 300                 };
 301
 302                 fimd: fimd@11c00000 {
 303                         compatible = "samsung,exynos3250-fimd";
 304                         reg = <0x11c00000 0x30000>;
 305                         interrupt-names = "fifo", "vsync", "lcd_sys";
 306                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 307                                      <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 308                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 309                         clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
 310                         clock-names = "sclk_fimd", "fimd";
 311                         power-domains = <&pd_lcd0>;
 312                         iommus = <&sysmmu_fimd0>;
 313                         samsung,sysreg = <&sys_reg>;
 314                         status = "disabled";
 315                 };
 316
 317                 dsi_0: dsi@11c80000 {
 318                         compatible = "samsung,exynos3250-mipi-dsi";
 319                         reg = <0x11C80000 0x10000>;
 320                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 321                         samsung,phy-type = <0>;
 322                         power-domains = <&pd_lcd0>;
 323                         phys = <&mipi_phy 1>;
 324                         phy-names = "dsim";
 325                         clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
 326                         clock-names = "bus_clk", "pll_clk";
 327                         #address-cells = <1>;
 328                         #size-cells = <0>;
 329                         status = "disabled";
 330                 };
 331
 332                 sysmmu_fimd0: sysmmu@11e20000 {
 333                         compatible = "samsung,exynos-sysmmu";
 334                         reg = <0x11e20000 0x1000>;
 335                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
 336                                      <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 337                         clock-names = "sysmmu", "master";
 338                         clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
 339                         power-domains = <&pd_lcd0>;
 340                         #iommu-cells = <0>;
 341                 };
 342
 343                 hsotg: hsotg@12480000 {
 344                         compatible = "snps,dwc2";
 345                         reg = <0x12480000 0x20000>;
 346                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 347                         clocks = <&cmu CLK_USBOTG>;
 348                         clock-names = "otg";
 349                         phys = <&exynos_usbphy 0>;
 350                         phy-names = "usb2-phy";
 351                         status = "disabled";
 352                 };
 353
 354                 mshc_0: mshc@12510000 {
 355                         compatible = "samsung,exynos5420-dw-mshc";
 356                         reg = <0x12510000 0x1000>;
 357                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 358                         clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
 359                         clock-names = "biu", "ciu";
 360                         fifo-depth = <0x80>;
 361                         #address-cells = <1>;
 362                         #size-cells = <0>;
 363                         status = "disabled";
 364                 };
 365
 366                 mshc_1: mshc@12520000 {
 367                         compatible = "samsung,exynos5420-dw-mshc";
 368                         reg = <0x12520000 0x1000>;
 369                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 370                         clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
 371                         clock-names = "biu", "ciu";
 372                         fifo-depth = <0x80>;
 373                         #address-cells = <1>;
 374                         #size-cells = <0>;
 375                         status = "disabled";
 376                 };
 377
 378                 mshc_2: mshc@12530000 {
 379                         compatible = "samsung,exynos5250-dw-mshc";
 380                         reg = <0x12530000 0x1000>;
 381                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 382                         clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
 383                         clock-names = "biu", "ciu";
 384                         fifo-depth = <0x80>;
 385                         #address-cells = <1>;
 386                         #size-cells = <0>;
 387                         status = "disabled";
 388                 };
 389
 390                 exynos_usbphy: exynos-usbphy@125b0000 {
 391                         compatible = "samsung,exynos3250-usb2-phy";
 392                         reg = <0x125B0000 0x100>;
 393                         samsung,pmureg-phandle = <&pmu_system_controller>;
 394                         clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
 395                         clock-names = "phy", "ref";
 396                         #phy-cells = <1>;
 397                         status = "disabled";
 398                 };
 399
 400                 amba {
 401                         compatible = "simple-bus";
 402                         #address-cells = <1>;
 403                         #size-cells = <1>;
 404                         ranges;
 405
 406                         pdma0: pdma@12680000 {
 407                                 compatible = "arm,pl330", "arm,primecell";
 408                                 reg = <0x12680000 0x1000>;
 409                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 410                                 clocks = <&cmu CLK_PDMA0>;
 411                                 clock-names = "apb_pclk";
 412                                 #dma-cells = <1>;
 413                                 #dma-channels = <8>;
 414                                 #dma-requests = <32>;
 415                         };
 416
 417                         pdma1: pdma@12690000 {
 418                                 compatible = "arm,pl330", "arm,primecell";
 419                                 reg = <0x12690000 0x1000>;
 420                                 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 421                                 clocks = <&cmu CLK_PDMA1>;
 422                                 clock-names = "apb_pclk";
 423                                 #dma-cells = <1>;
 424                                 #dma-channels = <8>;
 425                                 #dma-requests = <32>;
 426                         };
 427                 };
 428
 429                 adc: adc@126c0000 {
 430                         compatible = "samsung,exynos3250-adc",
 431                                      "samsung,exynos-adc-v2";
 432                         reg = <0x126C0000 0x100>;
 433                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 434                         clock-names = "adc", "sclk";
 435                         clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
 436                         #io-channel-cells = <1>;
 437                         io-channel-ranges;
 438                         samsung,syscon-phandle = <&pmu_system_controller>;
 439                         status = "disabled";
 440                 };
 441
 442                 mfc: codec@13400000 {
 443                         compatible = "samsung,mfc-v7";
 444                         reg = <0x13400000 0x10000>;
 445                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 446                         clock-names = "mfc", "sclk_mfc";
 447                         clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
 448                         power-domains = <&pd_mfc>;
 449                         iommus = <&sysmmu_mfc>;
 450                 };
 451
 452                 sysmmu_mfc: sysmmu@13620000 {
 453                         compatible = "samsung,exynos-sysmmu";
 454                         reg = <0x13620000 0x1000>;
 455                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 456                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 457                         clock-names = "sysmmu", "master";
 458                         clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
 459                         power-domains = <&pd_mfc>;
 460                         #iommu-cells = <0>;
 461                 };
 462
 463                 serial_0: serial@13800000 {
 464                         compatible = "samsung,exynos4210-uart";
 465                         reg = <0x13800000 0x100>;
 466                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 467                         clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
 468                         clock-names = "uart", "clk_uart_baud0";
 469                         pinctrl-names = "default";
 470                         pinctrl-0 = <&uart0_data &uart0_fctl>;
 471                         status = "disabled";
 472                 };
 473
 474                 serial_1: serial@13810000 {
 475                         compatible = "samsung,exynos4210-uart";
 476                         reg = <0x13810000 0x100>;
 477                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 478                         clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
 479                         clock-names = "uart", "clk_uart_baud0";
 480                         pinctrl-names = "default";
 481                         pinctrl-0 = <&uart1_data>;
 482                         status = "disabled";
 483                 };
 484
 485                 serial_2: serial@13820000 {
 486                         compatible = "samsung,exynos4210-uart";
 487                         reg = <0x13820000 0x100>;
 488                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 489                         clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
 490                         clock-names = "uart", "clk_uart_baud0";
 491                         pinctrl-names = "default";
 492                         pinctrl-0 = <&uart2_data>;
 493                         status = "disabled";
 494                 };
 495
 496                 i2c_0: i2c@13860000 {
 497                         #address-cells = <1>;
 498                         #size-cells = <0>;
 499                         compatible = "samsung,s3c2440-i2c";
 500                         reg = <0x13860000 0x100>;
 501                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 502                         clocks = <&cmu CLK_I2C0>;
 503                         clock-names = "i2c";
 504                         pinctrl-names = "default";
 505                         pinctrl-0 = <&i2c0_bus>;
 506                         status = "disabled";
 507                 };
 508
 509                 i2c_1: i2c@13870000 {
 510                         #address-cells = <1>;
 511                         #size-cells = <0>;
 512                         compatible = "samsung,s3c2440-i2c";
 513                         reg = <0x13870000 0x100>;
 514                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 515                         clocks = <&cmu CLK_I2C1>;
 516                         clock-names = "i2c";
 517                         pinctrl-names = "default";
 518                         pinctrl-0 = <&i2c1_bus>;
 519                         status = "disabled";
 520                 };
 521
 522                 i2c_2: i2c@13880000 {
 523                         #address-cells = <1>;
 524                         #size-cells = <0>;
 525                         compatible = "samsung,s3c2440-i2c";
 526                         reg = <0x13880000 0x100>;
 527                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 528                         clocks = <&cmu CLK_I2C2>;
 529                         clock-names = "i2c";
 530                         pinctrl-names = "default";
 531                         pinctrl-0 = <&i2c2_bus>;
 532                         status = "disabled";
 533                 };
 534
 535                 i2c_3: i2c@13890000 {
 536                         #address-cells = <1>;
 537                         #size-cells = <0>;
 538                         compatible = "samsung,s3c2440-i2c";
 539                         reg = <0x13890000 0x100>;
 540                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 541                         clocks = <&cmu CLK_I2C3>;
 542                         clock-names = "i2c";
 543                         pinctrl-names = "default";
 544                         pinctrl-0 = <&i2c3_bus>;
 545                         status = "disabled";
 546                 };
 547
 548                 i2c_4: i2c@138a0000 {
 549                         #address-cells = <1>;
 550                         #size-cells = <0>;
 551                         compatible = "samsung,s3c2440-i2c";
 552                         reg = <0x138A0000 0x100>;
 553                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 554                         clocks = <&cmu CLK_I2C4>;
 555                         clock-names = "i2c";
 556                         pinctrl-names = "default";
 557                         pinctrl-0 = <&i2c4_bus>;
 558                         status = "disabled";
 559                 };
 560
 561                 i2c_5: i2c@138b0000 {
 562                         #address-cells = <1>;
 563                         #size-cells = <0>;
 564                         compatible = "samsung,s3c2440-i2c";
 565                         reg = <0x138B0000 0x100>;
 566                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 567                         clocks = <&cmu CLK_I2C5>;
 568                         clock-names = "i2c";
 569                         pinctrl-names = "default";
 570                         pinctrl-0 = <&i2c5_bus>;
 571                         status = "disabled";
 572                 };
 573
 574                 i2c_6: i2c@138c0000 {
 575                         #address-cells = <1>;
 576                         #size-cells = <0>;
 577                         compatible = "samsung,s3c2440-i2c";
 578                         reg = <0x138C0000 0x100>;
 579                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 580                         clocks = <&cmu CLK_I2C6>;
 581                         clock-names = "i2c";
 582                         pinctrl-names = "default";
 583                         pinctrl-0 = <&i2c6_bus>;
 584                         status = "disabled";
 585                 };
 586
 587                 i2c_7: i2c@138d0000 {
 588                         #address-cells = <1>;
 589                         #size-cells = <0>;
 590                         compatible = "samsung,s3c2440-i2c";
 591                         reg = <0x138D0000 0x100>;
 592                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 593                         clocks = <&cmu CLK_I2C7>;
 594                         clock-names = "i2c";
 595                         pinctrl-names = "default";
 596                         pinctrl-0 = <&i2c7_bus>;
 597                         status = "disabled";
 598                 };
 599
 600                 spi_0: spi@13920000 {
 601                         compatible = "samsung,exynos4210-spi";
 602                         reg = <0x13920000 0x100>;
 603                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 604                         dmas = <&pdma0 7>, <&pdma0 6>;
 605                         dma-names = "tx", "rx";
 606                         #address-cells = <1>;
 607                         #size-cells = <0>;
 608                         clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
 609                         clock-names = "spi", "spi_busclk0";
 610                         samsung,spi-src-clk = <0>;
 611                         pinctrl-names = "default";
 612                         pinctrl-0 = <&spi0_bus>;
 613                         status = "disabled";
 614                 };
 615
 616                 spi_1: spi@13930000 {
 617                         compatible = "samsung,exynos4210-spi";
 618                         reg = <0x13930000 0x100>;
 619                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 620                         dmas = <&pdma1 7>, <&pdma1 6>;
 621                         dma-names = "tx", "rx";
 622                         #address-cells = <1>;
 623                         #size-cells = <0>;
 624                         clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
 625                         clock-names = "spi", "spi_busclk0";
 626                         samsung,spi-src-clk = <0>;
 627                         pinctrl-names = "default";
 628                         pinctrl-0 = <&spi1_bus>;
 629                         status = "disabled";
 630                 };
 631
 632                 i2s2: i2s@13970000 {
 633                         compatible = "samsung,s3c6410-i2s";
 634                         reg = <0x13970000 0x100>;
 635                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 636                         clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
 637                         clock-names = "iis", "i2s_opclk0";
 638                         dmas = <&pdma0 14>, <&pdma0 13>;
 639                         dma-names = "tx", "rx";
 640                         pinctrl-0 = <&i2s2_bus>;
 641                         pinctrl-names = "default";
 642                         status = "disabled";
 643                 };
 644
 645                 pwm: pwm@139d0000 {
 646                         compatible = "samsung,exynos4210-pwm";
 647                         reg = <0x139D0000 0x1000>;
 648                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 649                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 650                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 651                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 652                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 653                         #pwm-cells = <3>;
 654                         status = "disabled";
 655                 };
 656
 657                 pmu {
 658                         compatible = "arm,cortex-a7-pmu";
 659                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 660                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 661                 };
 662
 663                 ppmu_dmc0: ppmu_dmc0@106a0000 {
 664                         compatible = "samsung,exynos-ppmu";
 665                         reg = <0x106a0000 0x2000>;
 666                         status = "disabled";
 667                 };
 668
 669                 ppmu_dmc1: ppmu_dmc1@106b0000 {
 670                         compatible = "samsung,exynos-ppmu";
 671                         reg = <0x106b0000 0x2000>;
 672                         status = "disabled";
 673                 };
 674
 675                 ppmu_cpu: ppmu_cpu@106c0000 {
 676                         compatible = "samsung,exynos-ppmu";
 677                         reg = <0x106c0000 0x2000>;
 678                         status = "disabled";
 679                 };
 680
 681                 ppmu_rightbus: ppmu_rightbus@112a0000 {
 682                         compatible = "samsung,exynos-ppmu";
 683                         reg = <0x112a0000 0x2000>;
 684                         clocks = <&cmu CLK_PPMURIGHT>;
 685                         clock-names = "ppmu";
 686                         status = "disabled";
 687                 };
 688
 689                 ppmu_leftbus: ppmu_leftbus0@116a0000 {
 690                         compatible = "samsung,exynos-ppmu";
 691                         reg = <0x116a0000 0x2000>;
 692                         clocks = <&cmu CLK_PPMULEFT>;
 693                         clock-names = "ppmu";
 694                         status = "disabled";
 695                 };
 696
 697                 ppmu_camif: ppmu_camif@11ac0000 {
 698                         compatible = "samsung,exynos-ppmu";
 699                         reg = <0x11ac0000 0x2000>;
 700                         clocks = <&cmu CLK_PPMUCAMIF>;
 701                         clock-names = "ppmu";
 702                         status = "disabled";
 703                 };
 704
 705                 ppmu_lcd0: ppmu_lcd0@11e40000 {
 706                         compatible = "samsung,exynos-ppmu";
 707                         reg = <0x11e40000 0x2000>;
 708                         clocks = <&cmu CLK_PPMULCD0>;
 709                         clock-names = "ppmu";
 710                         status = "disabled";
 711                 };
 712
 713                 ppmu_fsys: ppmu_fsys@12630000 {
 714                         compatible = "samsung,exynos-ppmu";
 715                         reg = <0x12630000 0x2000>;
 716                         clocks = <&cmu CLK_PPMUFILE>;
 717                         clock-names = "ppmu";
 718                         status = "disabled";
 719                 };
 720
 721                 ppmu_g3d: ppmu_g3d@13220000 {
 722                         compatible = "samsung,exynos-ppmu";
 723                         reg = <0x13220000 0x2000>;
 724                         clocks = <&cmu CLK_PPMUG3D>;
 725                         clock-names = "ppmu";
 726                         status = "disabled";
 727                 };
 728
 729                 ppmu_mfc: ppmu_mfc@13660000 {
 730                         compatible = "samsung,exynos-ppmu";
 731                         reg = <0x13660000 0x2000>;
 732                         clocks = <&cmu CLK_PPMUMFC_L>;
 733                         clock-names = "ppmu";
 734                         status = "disabled";
 735                 };
 736
 737                 bus_dmc: bus_dmc {
 738                         compatible = "samsung,exynos-bus";
 739                         clocks = <&cmu_dmc CLK_DIV_DMC>;
 740                         clock-names = "bus";
 741                         operating-points-v2 = <&bus_dmc_opp_table>;
 742                         status = "disabled";
 743                 };
 744
 745                 bus_dmc_opp_table: opp_table1 {
 746                         compatible = "operating-points-v2";
 747                         opp-shared;
 748
 749                         opp-50000000 {
 750                                 opp-hz = /bits/ 64 <50000000>;
 751                                 opp-microvolt = <800000>;
 752                         };
 753                         opp-100000000 {
 754                                 opp-hz = /bits/ 64 <100000000>;
 755                                 opp-microvolt = <800000>;
 756                         };
 757                         opp-134000000 {
 758                                 opp-hz = /bits/ 64 <134000000>;
 759                                 opp-microvolt = <800000>;
 760                         };
 761                         opp-200000000 {
 762                                 opp-hz = /bits/ 64 <200000000>;
 763                                 opp-microvolt = <825000>;
 764                         };
 765                         opp-400000000 {
 766                                 opp-hz = /bits/ 64 <400000000>;
 767                                 opp-microvolt = <875000>;
 768                         };
 769                 };
 770
 771                 bus_leftbus: bus_leftbus {
 772                         compatible = "samsung,exynos-bus";
 773                         clocks = <&cmu CLK_DIV_GDL>;
 774                         clock-names = "bus";
 775                         operating-points-v2 = <&bus_leftbus_opp_table>;
 776                         status = "disabled";
 777                 };
 778
 779                 bus_rightbus: bus_rightbus {
 780                         compatible = "samsung,exynos-bus";
 781                         clocks = <&cmu CLK_DIV_GDR>;
 782                         clock-names = "bus";
 783                         operating-points-v2 = <&bus_leftbus_opp_table>;
 784                         status = "disabled";
 785                 };
 786
 787                 bus_lcd0: bus_lcd0 {
 788                         compatible = "samsung,exynos-bus";
 789                         clocks = <&cmu CLK_DIV_ACLK_160>;
 790                         clock-names = "bus";
 791                         operating-points-v2 = <&bus_leftbus_opp_table>;
 792                         status = "disabled";
 793                 };
 794
 795                 bus_fsys: bus_fsys {
 796                         compatible = "samsung,exynos-bus";
 797                         clocks = <&cmu CLK_DIV_ACLK_200>;
 798                         clock-names = "bus";
 799                         operating-points-v2 = <&bus_leftbus_opp_table>;
 800                         status = "disabled";
 801                 };
 802
 803                 bus_mcuisp: bus_mcuisp {
 804                         compatible = "samsung,exynos-bus";
 805                         clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
 806                         clock-names = "bus";
 807                         operating-points-v2 = <&bus_mcuisp_opp_table>;
 808                         status = "disabled";
 809                 };
 810
 811                 bus_isp: bus_isp {
 812                         compatible = "samsung,exynos-bus";
 813                         clocks = <&cmu CLK_DIV_ACLK_266>;
 814                         clock-names = "bus";
 815                         operating-points-v2 = <&bus_isp_opp_table>;
 816                         status = "disabled";
 817                 };
 818
 819                 bus_peril: bus_peril {
 820                         compatible = "samsung,exynos-bus";
 821                         clocks = <&cmu CLK_DIV_ACLK_100>;
 822                         clock-names = "bus";
 823                         operating-points-v2 = <&bus_peril_opp_table>;
 824                         status = "disabled";
 825                 };
 826
 827                 bus_mfc: bus_mfc {
 828                         compatible = "samsung,exynos-bus";
 829                         clocks = <&cmu CLK_SCLK_MFC>;
 830                         clock-names = "bus";
 831                         operating-points-v2 = <&bus_leftbus_opp_table>;
 832                         status = "disabled";
 833                 };
 834
 835                 bus_leftbus_opp_table: opp_table2 {
 836                         compatible = "operating-points-v2";
 837                         opp-shared;
 838
 839                         opp-50000000 {
 840                                 opp-hz = /bits/ 64 <50000000>;
 841                                 opp-microvolt = <900000>;
 842                         };
 843                         opp-80000000 {
 844                                 opp-hz = /bits/ 64 <80000000>;
 845                                 opp-microvolt = <900000>;
 846                         };
 847                         opp-100000000 {
 848                                 opp-hz = /bits/ 64 <100000000>;
 849                                 opp-microvolt = <1000000>;
 850                         };
 851                         opp-134000000 {
 852                                 opp-hz = /bits/ 64 <134000000>;
 853                                 opp-microvolt = <1000000>;
 854                         };
 855                         opp-200000000 {
 856                                 opp-hz = /bits/ 64 <200000000>;
 857                                 opp-microvolt = <1000000>;
 858                         };
 859                 };
 860
 861                 bus_mcuisp_opp_table: opp_table3 {
 862                         compatible = "operating-points-v2";
 863                         opp-shared;
 864
 865                         opp-50000000 {
 866                                 opp-hz = /bits/ 64 <50000000>;
 867                         };
 868                         opp-80000000 {
 869                                 opp-hz = /bits/ 64 <80000000>;
 870                         };
 871                         opp-100000000 {
 872                                 opp-hz = /bits/ 64 <100000000>;
 873                         };
 874                         opp-200000000 {
 875                                 opp-hz = /bits/ 64 <200000000>;
 876                         };
 877                         opp-400000000 {
 878                                 opp-hz = /bits/ 64 <400000000>;
 879                         };
 880                 };
 881
 882                 bus_isp_opp_table: opp_table4 {
 883                         compatible = "operating-points-v2";
 884                         opp-shared;
 885
 886                         opp-50000000 {
 887                                 opp-hz = /bits/ 64 <50000000>;
 888                         };
 889                         opp-80000000 {
 890                                 opp-hz = /bits/ 64 <80000000>;
 891                         };
 892                         opp-100000000 {
 893                                 opp-hz = /bits/ 64 <100000000>;
 894                         };
 895                         opp-200000000 {
 896                                 opp-hz = /bits/ 64 <200000000>;
 897                         };
 898                         opp-300000000 {
 899                                 opp-hz = /bits/ 64 <300000000>;
 900                         };
 901                 };
 902
 903                 bus_peril_opp_table: opp_table5 {
 904                         compatible = "operating-points-v2";
 905                         opp-shared;
 906
 907                         opp-50000000 {
 908                                 opp-hz = /bits/ 64 <50000000>;
 909                         };
 910                         opp-80000000 {
 911                                 opp-hz = /bits/ 64 <80000000>;
 912                         };
 913                         opp-100000000 {
 914                                 opp-hz = /bits/ 64 <100000000>;
 915                         };
 916                 };
 917         };
 918 };
 919
 920 #include "exynos3250-pinctrl.dtsi"
 921 #include "exynos-syscon-restart.dtsi"