src/arm/exynos3250.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Samsung's Exynos3250 SoC device tree source
   4  *
   5  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  *
   8  * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
   9  * based board files can include this file and provide values for board specfic
  10  * bindings.
  11  *
  12  * Note: This file does not include device nodes for all the controllers in
  13  * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
  14  * nodes can be added to this file.
  15  */
  16
  17 #include "exynos4-cpu-thermal.dtsi"
  18 #include <dt-bindings/clock/exynos3250.h>
  19 #include <dt-bindings/interrupt-controller/arm-gic.h>
  20 #include <dt-bindings/interrupt-controller/irq.h>
  21
  22 / {
  23         compatible = "samsung,exynos3250";
  24         interrupt-parent = <&gic>;
  25         #address-cells = <1>;
  26         #size-cells = <1>;
  27
  28         aliases {
  29                 pinctrl0 = &pinctrl_0;
  30                 pinctrl1 = &pinctrl_1;
  31                 spi0 = &spi_0;
  32                 spi1 = &spi_1;
  33                 i2c0 = &i2c_0;
  34                 i2c1 = &i2c_1;
  35                 i2c2 = &i2c_2;
  36                 i2c3 = &i2c_3;
  37                 i2c4 = &i2c_4;
  38                 i2c5 = &i2c_5;
  39                 i2c6 = &i2c_6;
  40                 i2c7 = &i2c_7;
  41                 serial0 = &serial_0;
  42                 serial1 = &serial_1;
  43                 serial2 = &serial_2;
  44         };
  45
  46         bus_dmc: bus-dmc {
  47                 compatible = "samsung,exynos-bus";
  48                 clocks = <&cmu_dmc CLK_DIV_DMC>;
  49                 clock-names = "bus";
  50                 operating-points-v2 = <&bus_dmc_opp_table>;
  51                 status = "disabled";
  52
  53                 bus_dmc_opp_table: opp-table {
  54                         compatible = "operating-points-v2";
  55
  56                         opp-50000000 {
  57                                 opp-hz = /bits/ 64 <50000000>;
  58                                 opp-microvolt = <800000>;
  59                         };
  60                         opp-100000000 {
  61                                 opp-hz = /bits/ 64 <100000000>;
  62                                 opp-microvolt = <800000>;
  63                         };
  64                         opp-134000000 {
  65                                 opp-hz = /bits/ 64 <134000000>;
  66                                 opp-microvolt = <800000>;
  67                         };
  68                         opp-200000000 {
  69                                 opp-hz = /bits/ 64 <200000000>;
  70                                 opp-microvolt = <825000>;
  71                         };
  72                         opp-400000000 {
  73                                 opp-hz = /bits/ 64 <400000000>;
  74                                 opp-microvolt = <875000>;
  75                         };
  76                 };
  77         };
  78
  79         bus_fsys: bus-fsys {
  80                 compatible = "samsung,exynos-bus";
  81                 clocks = <&cmu CLK_DIV_ACLK_200>;
  82                 clock-names = "bus";
  83                 operating-points-v2 = <&bus_leftbus_opp_table>;
  84                 status = "disabled";
  85         };
  86
  87         bus_isp: bus-isp {
  88                 compatible = "samsung,exynos-bus";
  89                 clocks = <&cmu CLK_DIV_ACLK_266>;
  90                 clock-names = "bus";
  91                 operating-points-v2 = <&bus_isp_opp_table>;
  92                 status = "disabled";
  93
  94                 bus_isp_opp_table: opp-table {
  95                         compatible = "operating-points-v2";
  96
  97                         opp-50000000 {
  98                                 opp-hz = /bits/ 64 <50000000>;
  99                         };
 100                         opp-80000000 {
 101                                 opp-hz = /bits/ 64 <80000000>;
 102                         };
 103                         opp-100000000 {
 104                                 opp-hz = /bits/ 64 <100000000>;
 105                         };
 106                         opp-200000000 {
 107                                 opp-hz = /bits/ 64 <200000000>;
 108                         };
 109                         opp-300000000 {
 110                                 opp-hz = /bits/ 64 <300000000>;
 111                         };
 112                 };
 113         };
 114
 115         bus_lcd0: bus-lcd0 {
 116                 compatible = "samsung,exynos-bus";
 117                 clocks = <&cmu CLK_DIV_ACLK_160>;
 118                 clock-names = "bus";
 119                 operating-points-v2 = <&bus_leftbus_opp_table>;
 120                 status = "disabled";
 121         };
 122
 123         bus_leftbus: bus-leftbus {
 124                 compatible = "samsung,exynos-bus";
 125                 clocks = <&cmu CLK_DIV_GDL>;
 126                 clock-names = "bus";
 127                 operating-points-v2 = <&bus_leftbus_opp_table>;
 128                 status = "disabled";
 129         };
 130
 131         bus_mcuisp: bus-mcuisp {
 132                 compatible = "samsung,exynos-bus";
 133                 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
 134                 clock-names = "bus";
 135                 operating-points-v2 = <&bus_mcuisp_opp_table>;
 136                 status = "disabled";
 137
 138                 bus_mcuisp_opp_table: opp-table {
 139                         compatible = "operating-points-v2";
 140
 141                         opp-50000000 {
 142                                 opp-hz = /bits/ 64 <50000000>;
 143                         };
 144                         opp-80000000 {
 145                                 opp-hz = /bits/ 64 <80000000>;
 146                         };
 147                         opp-100000000 {
 148                                 opp-hz = /bits/ 64 <100000000>;
 149                         };
 150                         opp-200000000 {
 151                                 opp-hz = /bits/ 64 <200000000>;
 152                         };
 153                         opp-400000000 {
 154                                 opp-hz = /bits/ 64 <400000000>;
 155                         };
 156                 };
 157         };
 158
 159         bus_mfc: bus-mfc {
 160                 compatible = "samsung,exynos-bus";
 161                 clocks = <&cmu CLK_SCLK_MFC>;
 162                 clock-names = "bus";
 163                 operating-points-v2 = <&bus_leftbus_opp_table>;
 164                 status = "disabled";
 165         };
 166
 167         bus_peril: bus-peril {
 168                 compatible = "samsung,exynos-bus";
 169                 clocks = <&cmu CLK_DIV_ACLK_100>;
 170                 clock-names = "bus";
 171                 operating-points-v2 = <&bus_peril_opp_table>;
 172                 status = "disabled";
 173
 174                 bus_peril_opp_table: opp-table {
 175                         compatible = "operating-points-v2";
 176
 177                         opp-50000000 {
 178                                 opp-hz = /bits/ 64 <50000000>;
 179                         };
 180                         opp-80000000 {
 181                                 opp-hz = /bits/ 64 <80000000>;
 182                         };
 183                         opp-100000000 {
 184                                 opp-hz = /bits/ 64 <100000000>;
 185                         };
 186                 };
 187         };
 188
 189         bus_rightbus: bus-rightbus {
 190                 compatible = "samsung,exynos-bus";
 191                 clocks = <&cmu CLK_DIV_GDR>;
 192                 clock-names = "bus";
 193                 operating-points-v2 = <&bus_leftbus_opp_table>;
 194                 status = "disabled";
 195         };
 196
 197         cpus {
 198                 #address-cells = <1>;
 199                 #size-cells = <0>;
 200
 201                 cpu-map {
 202                         cluster0 {
 203                                 core0 {
 204                                         cpu = <&cpu0>;
 205                                 };
 206                                 core1 {
 207                                         cpu = <&cpu1>;
 208                                 };
 209                         };
 210                 };
 211
 212                 cpu0: cpu@0 {
 213                         device_type = "cpu";
 214                         compatible = "arm,cortex-a7";
 215                         reg = <0>;
 216                         clock-frequency = <1000000000>;
 217                         clocks = <&cmu CLK_ARM_CLK>;
 218                         clock-names = "cpu";
 219                         #cooling-cells = <2>;
 220
 221                         operating-points = <
 222                                 1000000 1150000
 223                                 900000  1112500
 224                                 800000  1075000
 225                                 700000  1037500
 226                                 600000  1000000
 227                                 500000  962500
 228                                 400000  925000
 229                                 300000  887500
 230                                 200000  850000
 231                                 100000  850000
 232                         >;
 233                 };
 234
 235                 cpu1: cpu@1 {
 236                         device_type = "cpu";
 237                         compatible = "arm,cortex-a7";
 238                         reg = <1>;
 239                         clock-frequency = <1000000000>;
 240                         clocks = <&cmu CLK_ARM_CLK>;
 241                         clock-names = "cpu";
 242                         #cooling-cells = <2>;
 243
 244                         operating-points = <
 245                                 1000000 1150000
 246                                 900000  1112500
 247                                 800000  1075000
 248                                 700000  1037500
 249                                 600000  1000000
 250                                 500000  962500
 251                                 400000  925000
 252                                 300000  887500
 253                                 200000  850000
 254                                 100000  850000
 255                         >;
 256                 };
 257         };
 258
 259         xusbxti: clock-0 {
 260                 compatible = "fixed-clock";
 261                 clock-frequency = <0>;
 262                 #clock-cells = <0>;
 263                 clock-output-names = "xusbxti";
 264         };
 265
 266         xxti: clock-1 {
 267                 compatible = "fixed-clock";
 268                 clock-frequency = <0>;
 269                 #clock-cells = <0>;
 270                 clock-output-names = "xxti";
 271         };
 272
 273         xtcxo: clock-2 {
 274                 compatible = "fixed-clock";
 275                 clock-frequency = <0>;
 276                 #clock-cells = <0>;
 277                 clock-output-names = "xtcxo";
 278         };
 279
 280         bus_leftbus_opp_table: opp-table-0 {
 281                 compatible = "operating-points-v2";
 282
 283                 opp-50000000 {
 284                         opp-hz = /bits/ 64 <50000000>;
 285                         opp-microvolt = <900000>;
 286                 };
 287                 opp-80000000 {
 288                         opp-hz = /bits/ 64 <80000000>;
 289                         opp-microvolt = <900000>;
 290                 };
 291                 opp-100000000 {
 292                         opp-hz = /bits/ 64 <100000000>;
 293                         opp-microvolt = <1000000>;
 294                 };
 295                 opp-134000000 {
 296                         opp-hz = /bits/ 64 <134000000>;
 297                         opp-microvolt = <1000000>;
 298                 };
 299                 opp-200000000 {
 300                         opp-hz = /bits/ 64 <200000000>;
 301                         opp-microvolt = <1000000>;
 302                 };
 303         };
 304
 305         pmu {
 306                 compatible = "arm,cortex-a7-pmu";
 307                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 308                              <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 309         };
 310
 311         soc: soc {
 312                 compatible = "simple-bus";
 313                 #address-cells = <1>;
 314                 #size-cells = <1>;
 315                 ranges;
 316
 317                 sram@2020000 {
 318                         compatible = "mmio-sram";
 319                         reg = <0x02020000 0x40000>;
 320                         #address-cells = <1>;
 321                         #size-cells = <1>;
 322                         ranges = <0 0x02020000 0x40000>;
 323
 324                         smp-sram@0 {
 325                                 compatible = "samsung,exynos4210-sysram";
 326                                 reg = <0x0 0x1000>;
 327                         };
 328
 329                         smp-sram@3f000 {
 330                                 compatible = "samsung,exynos4210-sysram-ns";
 331                                 reg = <0x3f000 0x1000>;
 332                         };
 333                 };
 334
 335                 chipid@10000000 {
 336                         compatible = "samsung,exynos4210-chipid";
 337                         reg = <0x10000000 0x100>;
 338                 };
 339
 340                 sys_reg: syscon@10010000 {
 341                         compatible = "samsung,exynos3-sysreg", "syscon";
 342                         reg = <0x10010000 0x400>;
 343                 };
 344
 345                 pmu_system_controller: system-controller@10020000 {
 346                         compatible = "samsung,exynos3250-pmu", "simple-mfd", "syscon";
 347                         reg = <0x10020000 0x4000>;
 348                         interrupt-controller;
 349                         #interrupt-cells = <3>;
 350                         interrupt-parent = <&gic>;
 351                         clock-names = "clkout8";
 352                         clocks = <&cmu CLK_FIN_PLL>;
 353                         #clock-cells = <1>;
 354
 355                         mipi_phy: mipi-phy {
 356                                 compatible = "samsung,s5pv210-mipi-video-phy";
 357                                 #phy-cells = <1>;
 358                         };
 359                 };
 360
 361                 pd_cam: power-domain@10023c00 {
 362                         compatible = "samsung,exynos4210-pd";
 363                         reg = <0x10023c00 0x20>;
 364                         #power-domain-cells = <0>;
 365                         label = "CAM";
 366                 };
 367
 368                 pd_mfc: power-domain@10023c40 {
 369                         compatible = "samsung,exynos4210-pd";
 370                         reg = <0x10023c40 0x20>;
 371                         #power-domain-cells = <0>;
 372                         label = "MFC";
 373                 };
 374
 375                 pd_g3d: power-domain@10023c60 {
 376                         compatible = "samsung,exynos4210-pd";
 377                         reg = <0x10023c60 0x20>;
 378                         #power-domain-cells = <0>;
 379                         label = "G3D";
 380                 };
 381
 382                 pd_lcd0: power-domain@10023c80 {
 383                         compatible = "samsung,exynos4210-pd";
 384                         reg = <0x10023c80 0x20>;
 385                         #power-domain-cells = <0>;
 386                         label = "LCD0";
 387                 };
 388
 389                 pd_isp: power-domain@10023ca0 {
 390                         compatible = "samsung,exynos4210-pd";
 391                         reg = <0x10023ca0 0x20>;
 392                         #power-domain-cells = <0>;
 393                         label = "ISP";
 394                 };
 395
 396                 cmu: clock-controller@10030000 {
 397                         compatible = "samsung,exynos3250-cmu";
 398                         reg = <0x10030000 0x20000>;
 399                         #clock-cells = <1>;
 400                         assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
 401                                           <&cmu CLK_MOUT_ACLK_266_SUB>;
 402                         assigned-clock-parents = <&cmu CLK_FIN_PLL>,
 403                                                  <&cmu CLK_FIN_PLL>;
 404                 };
 405
 406                 cmu_dmc: clock-controller@105c0000 {
 407                         compatible = "samsung,exynos3250-cmu-dmc";
 408                         reg = <0x105c0000 0x2000>;
 409                         #clock-cells = <1>;
 410                 };
 411
 412                 rtc: rtc@10070000 {
 413                         compatible = "samsung,s3c6410-rtc";
 414                         reg = <0x10070000 0x100>;
 415                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 416                                      <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 417                         interrupt-parent = <&pmu_system_controller>;
 418                         status = "disabled";
 419                 };
 420
 421                 tmu: tmu@100c0000 {
 422                         compatible = "samsung,exynos3250-tmu";
 423                         reg = <0x100c0000 0x100>;
 424                         interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 425                         clocks = <&cmu CLK_TMU_APBIF>;
 426                         clock-names = "tmu_apbif";
 427                         #thermal-sensor-cells = <0>;
 428                         status = "disabled";
 429                 };
 430
 431                 gic: interrupt-controller@10481000 {
 432                         compatible = "arm,cortex-a15-gic";
 433                         #interrupt-cells = <3>;
 434                         interrupt-controller;
 435                         reg = <0x10481000 0x1000>,
 436                               <0x10482000 0x2000>,
 437                               <0x10484000 0x2000>,
 438                               <0x10486000 0x2000>;
 439                         interrupts = <GIC_PPI 9
 440                                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 441                 };
 442
 443                 timer@10050000 {
 444                         compatible = "samsung,exynos3250-mct",
 445                                      "samsung,exynos4210-mct";
 446                         reg = <0x10050000 0x800>;
 447                         interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
 448                                      <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
 449                                      <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
 450                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
 451                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
 452                                      <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
 453                                      <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
 454                                      <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
 455                         clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
 456                         clock-names = "fin_pll", "mct";
 457                 };
 458
 459                 pinctrl_1: pinctrl@11000000 {
 460                         compatible = "samsung,exynos3250-pinctrl";
 461                         reg = <0x11000000 0x1000>;
 462                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 463
 464                         wakeup-interrupt-controller {
 465                                 compatible = "samsung,exynos4210-wakeup-eint";
 466                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 467                         };
 468                 };
 469
 470                 pinctrl_0: pinctrl@11400000 {
 471                         compatible = "samsung,exynos3250-pinctrl";
 472                         reg = <0x11400000 0x1000>;
 473                         interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 474                 };
 475
 476                 jpeg: codec@11830000 {
 477                         compatible = "samsung,exynos3250-jpeg";
 478                         reg = <0x11830000 0x1000>;
 479                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 480                         clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
 481                         clock-names = "jpeg", "sclk";
 482                         power-domains = <&pd_cam>;
 483                         assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
 484                         assigned-clock-rates = <0>, <150000000>;
 485                         assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
 486                         iommus = <&sysmmu_jpeg>;
 487                         status = "disabled";
 488                 };
 489
 490                 sysmmu_jpeg: sysmmu@11a60000 {
 491                         compatible = "samsung,exynos-sysmmu";
 492                         reg = <0x11a60000 0x1000>;
 493                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 494                         clock-names = "sysmmu", "master";
 495                         clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
 496                         power-domains = <&pd_cam>;
 497                         #iommu-cells = <0>;
 498                 };
 499
 500                 fimd: fimd@11c00000 {
 501                         compatible = "samsung,exynos3250-fimd";
 502                         reg = <0x11c00000 0x30000>;
 503                         interrupt-names = "fifo", "vsync", "lcd_sys";
 504                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 505                                      <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 506                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 507                         clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
 508                         clock-names = "sclk_fimd", "fimd";
 509                         power-domains = <&pd_lcd0>;
 510                         iommus = <&sysmmu_fimd0>;
 511                         samsung,sysreg = <&sys_reg>;
 512                         status = "disabled";
 513                 };
 514
 515                 dsi_0: dsi@11c80000 {
 516                         compatible = "samsung,exynos3250-mipi-dsi";
 517                         reg = <0x11c80000 0x10000>;
 518                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 519                         samsung,phy-type = <0>;
 520                         power-domains = <&pd_lcd0>;
 521                         phys = <&mipi_phy 1>;
 522                         phy-names = "dsim";
 523                         clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
 524                         clock-names = "bus_clk", "pll_clk";
 525                         #address-cells = <1>;
 526                         #size-cells = <0>;
 527                         status = "disabled";
 528                 };
 529
 530                 sysmmu_fimd0: sysmmu@11e20000 {
 531                         compatible = "samsung,exynos-sysmmu";
 532                         reg = <0x11e20000 0x1000>;
 533                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 534                         clock-names = "sysmmu", "master";
 535                         clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
 536                         power-domains = <&pd_lcd0>;
 537                         #iommu-cells = <0>;
 538                 };
 539
 540                 hsotg: usb@12480000 {
 541                         compatible = "samsung,s3c6400-hsotg";
 542                         reg = <0x12480000 0x20000>;
 543                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 544                         clocks = <&cmu CLK_USBOTG>;
 545                         clock-names = "otg";
 546                         phys = <&exynos_usbphy 0>;
 547                         phy-names = "usb2-phy";
 548                         status = "disabled";
 549                 };
 550
 551                 mshc_0: mmc@12510000 {
 552                         compatible = "samsung,exynos5420-dw-mshc";
 553                         reg = <0x12510000 0x1000>;
 554                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 555                         clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
 556                         clock-names = "biu", "ciu";
 557                         fifo-depth = <0x80>;
 558                         #address-cells = <1>;
 559                         #size-cells = <0>;
 560                         status = "disabled";
 561                 };
 562
 563                 mshc_1: mmc@12520000 {
 564                         compatible = "samsung,exynos5420-dw-mshc";
 565                         reg = <0x12520000 0x1000>;
 566                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 567                         clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
 568                         clock-names = "biu", "ciu";
 569                         fifo-depth = <0x80>;
 570                         #address-cells = <1>;
 571                         #size-cells = <0>;
 572                         status = "disabled";
 573                 };
 574
 575                 mshc_2: mmc@12530000 {
 576                         compatible = "samsung,exynos5250-dw-mshc";
 577                         reg = <0x12530000 0x1000>;
 578                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 579                         clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
 580                         clock-names = "biu", "ciu";
 581                         fifo-depth = <0x80>;
 582                         #address-cells = <1>;
 583                         #size-cells = <0>;
 584                         status = "disabled";
 585                 };
 586
 587                 exynos_usbphy: usb-phy@125b0000 {
 588                         compatible = "samsung,exynos3250-usb2-phy";
 589                         reg = <0x125b0000 0x100>;
 590                         samsung,pmureg-phandle = <&pmu_system_controller>;
 591                         clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
 592                         clock-names = "phy", "ref";
 593                         #phy-cells = <1>;
 594                         status = "disabled";
 595                 };
 596
 597                 pdma0: dma-controller@12680000 {
 598                         compatible = "arm,pl330", "arm,primecell";
 599                         reg = <0x12680000 0x1000>;
 600                         interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 601                         clocks = <&cmu CLK_PDMA0>;
 602                         clock-names = "apb_pclk";
 603                         #dma-cells = <1>;
 604                 };
 605
 606                 pdma1: dma-controller@12690000 {
 607                         compatible = "arm,pl330", "arm,primecell";
 608                         reg = <0x12690000 0x1000>;
 609                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 610                         clocks = <&cmu CLK_PDMA1>;
 611                         clock-names = "apb_pclk";
 612                         #dma-cells = <1>;
 613                 };
 614
 615                 adc: adc@126c0000 {
 616                         compatible = "samsung,exynos3250-adc";
 617                         reg = <0x126c0000 0x100>;
 618                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 619                         clock-names = "adc", "sclk";
 620                         clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
 621                         #io-channel-cells = <1>;
 622                         samsung,syscon-phandle = <&pmu_system_controller>;
 623                         status = "disabled";
 624                 };
 625
 626                 gpu: gpu@13000000 {
 627                         compatible = "samsung,exynos4210-mali", "arm,mali-400";
 628                         reg = <0x13000000 0x10000>;
 629                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
 630                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
 631                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
 632                                      <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
 633                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 634                                      <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
 635                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 636                                      <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
 637                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
 638                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 639                                      <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 640                         interrupt-names = "gp",
 641                                           "gpmmu",
 642                                           "pp0",
 643                                           "ppmmu0",
 644                                           "pp1",
 645                                           "ppmmu1",
 646                                           "pp2",
 647                                           "ppmmu2",
 648                                           "pp3",
 649                                           "ppmmu3",
 650                                           "pmu";
 651                         clocks = <&cmu CLK_G3D>,
 652                                  <&cmu CLK_SCLK_G3D>;
 653                         clock-names = "bus", "core";
 654                         power-domains = <&pd_g3d>;
 655                         status = "disabled";
 656                         /* TODO: operating points for DVFS, assigned clock as 134 MHz */
 657                 };
 658
 659                 mfc: codec@13400000 {
 660                         compatible = "samsung,exynos3250-mfc", "samsung,mfc-v7";
 661                         reg = <0x13400000 0x10000>;
 662                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 663                         clock-names = "mfc", "sclk_mfc";
 664                         clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
 665                         power-domains = <&pd_mfc>;
 666                         iommus = <&sysmmu_mfc>;
 667                 };
 668
 669                 sysmmu_mfc: sysmmu@13620000 {
 670                         compatible = "samsung,exynos-sysmmu";
 671                         reg = <0x13620000 0x1000>;
 672                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 673                         clock-names = "sysmmu", "master";
 674                         clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
 675                         power-domains = <&pd_mfc>;
 676                         #iommu-cells = <0>;
 677                 };
 678
 679                 serial_0: serial@13800000 {
 680                         compatible = "samsung,exynos4210-uart";
 681                         reg = <0x13800000 0x100>;
 682                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 683                         clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
 684                         clock-names = "uart", "clk_uart_baud0";
 685                         pinctrl-names = "default";
 686                         pinctrl-0 = <&uart0_data &uart0_fctl>;
 687                         status = "disabled";
 688                 };
 689
 690                 serial_1: serial@13810000 {
 691                         compatible = "samsung,exynos4210-uart";
 692                         reg = <0x13810000 0x100>;
 693                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 694                         clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
 695                         clock-names = "uart", "clk_uart_baud0";
 696                         pinctrl-names = "default";
 697                         pinctrl-0 = <&uart1_data>;
 698                         status = "disabled";
 699                 };
 700
 701                 serial_2: serial@13820000 {
 702                         compatible = "samsung,exynos4210-uart";
 703                         reg = <0x13820000 0x100>;
 704                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 705                         clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
 706                         clock-names = "uart", "clk_uart_baud0";
 707                         pinctrl-names = "default";
 708                         pinctrl-0 = <&uart2_data>;
 709                         status = "disabled";
 710                 };
 711
 712                 i2c_0: i2c@13860000 {
 713                         #address-cells = <1>;
 714                         #size-cells = <0>;
 715                         compatible = "samsung,s3c2440-i2c";
 716                         reg = <0x13860000 0x100>;
 717                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 718                         clocks = <&cmu CLK_I2C0>;
 719                         clock-names = "i2c";
 720                         pinctrl-names = "default";
 721                         pinctrl-0 = <&i2c0_bus>;
 722                         status = "disabled";
 723                 };
 724
 725                 i2c_1: i2c@13870000 {
 726                         #address-cells = <1>;
 727                         #size-cells = <0>;
 728                         compatible = "samsung,s3c2440-i2c";
 729                         reg = <0x13870000 0x100>;
 730                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 731                         clocks = <&cmu CLK_I2C1>;
 732                         clock-names = "i2c";
 733                         pinctrl-names = "default";
 734                         pinctrl-0 = <&i2c1_bus>;
 735                         status = "disabled";
 736                 };
 737
 738                 i2c_2: i2c@13880000 {
 739                         #address-cells = <1>;
 740                         #size-cells = <0>;
 741                         compatible = "samsung,s3c2440-i2c";
 742                         reg = <0x13880000 0x100>;
 743                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 744                         clocks = <&cmu CLK_I2C2>;
 745                         clock-names = "i2c";
 746                         pinctrl-names = "default";
 747                         pinctrl-0 = <&i2c2_bus>;
 748                         status = "disabled";
 749                 };
 750
 751                 i2c_3: i2c@13890000 {
 752                         #address-cells = <1>;
 753                         #size-cells = <0>;
 754                         compatible = "samsung,s3c2440-i2c";
 755                         reg = <0x13890000 0x100>;
 756                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 757                         clocks = <&cmu CLK_I2C3>;
 758                         clock-names = "i2c";
 759                         pinctrl-names = "default";
 760                         pinctrl-0 = <&i2c3_bus>;
 761                         status = "disabled";
 762                 };
 763
 764                 i2c_4: i2c@138a0000 {
 765                         #address-cells = <1>;
 766                         #size-cells = <0>;
 767                         compatible = "samsung,s3c2440-i2c";
 768                         reg = <0x138a0000 0x100>;
 769                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 770                         clocks = <&cmu CLK_I2C4>;
 771                         clock-names = "i2c";
 772                         pinctrl-names = "default";
 773                         pinctrl-0 = <&i2c4_bus>;
 774                         status = "disabled";
 775                 };
 776
 777                 i2c_5: i2c@138b0000 {
 778                         #address-cells = <1>;
 779                         #size-cells = <0>;
 780                         compatible = "samsung,s3c2440-i2c";
 781                         reg = <0x138b0000 0x100>;
 782                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 783                         clocks = <&cmu CLK_I2C5>;
 784                         clock-names = "i2c";
 785                         pinctrl-names = "default";
 786                         pinctrl-0 = <&i2c5_bus>;
 787                         status = "disabled";
 788                 };
 789
 790                 i2c_6: i2c@138c0000 {
 791                         #address-cells = <1>;
 792                         #size-cells = <0>;
 793                         compatible = "samsung,s3c2440-i2c";
 794                         reg = <0x138c0000 0x100>;
 795                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 796                         clocks = <&cmu CLK_I2C6>;
 797                         clock-names = "i2c";
 798                         pinctrl-names = "default";
 799                         pinctrl-0 = <&i2c6_bus>;
 800                         status = "disabled";
 801                 };
 802
 803                 i2c_7: i2c@138d0000 {
 804                         #address-cells = <1>;
 805                         #size-cells = <0>;
 806                         compatible = "samsung,s3c2440-i2c";
 807                         reg = <0x138d0000 0x100>;
 808                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 809                         clocks = <&cmu CLK_I2C7>;
 810                         clock-names = "i2c";
 811                         pinctrl-names = "default";
 812                         pinctrl-0 = <&i2c7_bus>;
 813                         status = "disabled";
 814                 };
 815
 816                 spi_0: spi@13920000 {
 817                         compatible = "samsung,exynos4210-spi";
 818                         reg = <0x13920000 0x100>;
 819                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 820                         dmas = <&pdma0 7>, <&pdma0 6>;
 821                         dma-names = "tx", "rx";
 822                         #address-cells = <1>;
 823                         #size-cells = <0>;
 824                         clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
 825                         clock-names = "spi", "spi_busclk0";
 826                         samsung,spi-src-clk = <0>;
 827                         pinctrl-names = "default";
 828                         pinctrl-0 = <&spi0_bus>;
 829                         status = "disabled";
 830                 };
 831
 832                 spi_1: spi@13930000 {
 833                         compatible = "samsung,exynos4210-spi";
 834                         reg = <0x13930000 0x100>;
 835                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 836                         dmas = <&pdma1 7>, <&pdma1 6>;
 837                         dma-names = "tx", "rx";
 838                         #address-cells = <1>;
 839                         #size-cells = <0>;
 840                         clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
 841                         clock-names = "spi", "spi_busclk0";
 842                         samsung,spi-src-clk = <0>;
 843                         pinctrl-names = "default";
 844                         pinctrl-0 = <&spi1_bus>;
 845                         status = "disabled";
 846                 };
 847
 848                 i2s2: i2s@13970000 {
 849                         compatible = "samsung,s3c6410-i2s";
 850                         reg = <0x13970000 0x100>;
 851                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 852                         clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
 853                         clock-names = "iis", "i2s_opclk0";
 854                         dmas = <&pdma0 14>, <&pdma0 13>;
 855                         dma-names = "tx", "rx";
 856                         pinctrl-0 = <&i2s2_bus>;
 857                         pinctrl-names = "default";
 858                         status = "disabled";
 859                 };
 860
 861                 pwm: pwm@139d0000 {
 862                         compatible = "samsung,exynos4210-pwm";
 863                         reg = <0x139d0000 0x1000>;
 864                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 865                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 866                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 867                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 868                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 869                         #pwm-cells = <3>;
 870                         status = "disabled";
 871                 };
 872
 873                 ppmu_dmc0: ppmu@106a0000 {
 874                         compatible = "samsung,exynos-ppmu";
 875                         reg = <0x106a0000 0x2000>;
 876                         status = "disabled";
 877                 };
 878
 879                 ppmu_dmc1: ppmu@106b0000 {
 880                         compatible = "samsung,exynos-ppmu";
 881                         reg = <0x106b0000 0x2000>;
 882                         status = "disabled";
 883                 };
 884
 885                 ppmu_cpu: ppmu@106c0000 {
 886                         compatible = "samsung,exynos-ppmu";
 887                         reg = <0x106c0000 0x2000>;
 888                         status = "disabled";
 889                 };
 890
 891                 ppmu_rightbus: ppmu@112a0000 {
 892                         compatible = "samsung,exynos-ppmu";
 893                         reg = <0x112a0000 0x2000>;
 894                         clocks = <&cmu CLK_PPMURIGHT>;
 895                         clock-names = "ppmu";
 896                         status = "disabled";
 897                 };
 898
 899                 ppmu_leftbus: ppmu@116a0000 {
 900                         compatible = "samsung,exynos-ppmu";
 901                         reg = <0x116a0000 0x2000>;
 902                         clocks = <&cmu CLK_PPMULEFT>;
 903                         clock-names = "ppmu";
 904                         status = "disabled";
 905                 };
 906
 907                 ppmu_camif: ppmu@11ac0000 {
 908                         compatible = "samsung,exynos-ppmu";
 909                         reg = <0x11ac0000 0x2000>;
 910                         clocks = <&cmu CLK_PPMUCAMIF>;
 911                         clock-names = "ppmu";
 912                         status = "disabled";
 913                 };
 914
 915                 ppmu_lcd0: ppmu@11e40000 {
 916                         compatible = "samsung,exynos-ppmu";
 917                         reg = <0x11e40000 0x2000>;
 918                         clocks = <&cmu CLK_PPMULCD0>;
 919                         clock-names = "ppmu";
 920                         status = "disabled";
 921                 };
 922
 923                 ppmu_fsys: ppmu@12630000 {
 924                         compatible = "samsung,exynos-ppmu";
 925                         reg = <0x12630000 0x2000>;
 926                         clocks = <&cmu CLK_PPMUFILE>;
 927                         clock-names = "ppmu";
 928                         status = "disabled";
 929                 };
 930
 931                 ppmu_g3d: ppmu@13220000 {
 932                         compatible = "samsung,exynos-ppmu";
 933                         reg = <0x13220000 0x2000>;
 934                         clocks = <&cmu CLK_PPMUG3D>;
 935                         clock-names = "ppmu";
 936                         status = "disabled";
 937                 };
 938
 939                 ppmu_mfc: ppmu@13660000 {
 940                         compatible = "samsung,exynos-ppmu";
 941                         reg = <0x13660000 0x2000>;
 942                         clocks = <&cmu CLK_PPMUMFC_L>;
 943                         clock-names = "ppmu";
 944                         status = "disabled";
 945                 };
 946         };
 947 };
 948
 949 #include "exynos3250-pinctrl.dtsi"
 950 #include "exynos-syscon-restart.dtsi"