src/arm/exynos5420.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Samsung Exynos5420 SoC device tree source
   4  *
   5  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  *
   8  * Samsung Exynos5420 SoC device nodes are listed in this file.
   9  * Exynos5420 based board files can include this file and provide
  10  * values for board specfic bindings.
  11  */
  12
  13 #include "exynos54xx.dtsi"
  14 #include <dt-bindings/clock/exynos5420.h>
  15 #include <dt-bindings/clock/exynos-audss-clk.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17
  18 / {
  19         compatible = "samsung,exynos5420", "samsung,exynos5";
  20
  21         aliases {
  22                 pinctrl0 = &pinctrl_0;
  23                 pinctrl1 = &pinctrl_1;
  24                 pinctrl2 = &pinctrl_2;
  25                 pinctrl3 = &pinctrl_3;
  26                 pinctrl4 = &pinctrl_4;
  27                 i2c8 = &hsi2c_8;
  28                 i2c9 = &hsi2c_9;
  29                 i2c10 = &hsi2c_10;
  30                 gsc0 = &gsc_0;
  31                 gsc1 = &gsc_1;
  32                 spi0 = &spi_0;
  33                 spi1 = &spi_1;
  34                 spi2 = &spi_2;
  35         };
  36
  37         bus_disp1: bus-disp1 {
  38                 compatible = "samsung,exynos-bus";
  39                 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
  40                 clock-names = "bus";
  41                 status = "disabled";
  42         };
  43
  44         bus_disp1_fimd: bus-disp1-fimd {
  45                 compatible = "samsung,exynos-bus";
  46                 clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
  47                 clock-names = "bus";
  48                 status = "disabled";
  49         };
  50
  51         bus_fsys: bus-fsys {
  52                 compatible = "samsung,exynos-bus";
  53                 clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
  54                 clock-names = "bus";
  55                 status = "disabled";
  56         };
  57
  58         bus_fsys2: bus-fsys2 {
  59                 compatible = "samsung,exynos-bus";
  60                 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
  61                 clock-names = "bus";
  62                 status = "disabled";
  63         };
  64
  65         bus_fsys_apb: bus-fsys-apb {
  66                 compatible = "samsung,exynos-bus";
  67                 clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
  68                 clock-names = "bus";
  69                 status = "disabled";
  70         };
  71
  72         bus_g2d: bus-g2d {
  73                 compatible = "samsung,exynos-bus";
  74                 clocks = <&clock CLK_DOUT_ACLK333_G2D>;
  75                 clock-names = "bus";
  76                 status = "disabled";
  77         };
  78
  79         bus_g2d_acp: bus-g2d-acp {
  80                 compatible = "samsung,exynos-bus";
  81                 clocks = <&clock CLK_DOUT_ACLK266_G2D>;
  82                 clock-names = "bus";
  83                 status = "disabled";
  84         };
  85         bus_gen: bus-gen {
  86                 compatible = "samsung,exynos-bus";
  87                 clocks = <&clock CLK_DOUT_ACLK266>;
  88                 clock-names = "bus";
  89                 status = "disabled";
  90         };
  91
  92         bus_gscl_scaler: bus-gscl-scaler {
  93                 compatible = "samsung,exynos-bus";
  94                 clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
  95                 clock-names = "bus";
  96                 status = "disabled";
  97         };
  98
  99         bus_jpeg: bus-jpeg {
 100                 compatible = "samsung,exynos-bus";
 101                 clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
 102                 clock-names = "bus";
 103                 status = "disabled";
 104         };
 105
 106         bus_jpeg_apb: bus-jpeg-apb {
 107                 compatible = "samsung,exynos-bus";
 108                 clocks = <&clock CLK_DOUT_ACLK166>;
 109                 clock-names = "bus";
 110                 status = "disabled";
 111         };
 112
 113         bus_mfc: bus-mfc {
 114                 compatible = "samsung,exynos-bus";
 115                 clocks = <&clock CLK_DOUT_ACLK333>;
 116                 clock-names = "bus";
 117                 status = "disabled";
 118         };
 119
 120         bus_mscl: bus-mscl {
 121                 compatible = "samsung,exynos-bus";
 122                 clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
 123                 clock-names = "bus";
 124                 status = "disabled";
 125         };
 126
 127         bus_noc: bus-noc {
 128                 compatible = "samsung,exynos-bus";
 129                 clocks = <&clock CLK_DOUT_ACLK100_NOC>;
 130                 clock-names = "bus";
 131                 status = "disabled";
 132         };
 133
 134         bus_peri: bus-peri {
 135                 compatible = "samsung,exynos-bus";
 136                 clocks = <&clock CLK_DOUT_ACLK66>;
 137                 clock-names = "bus";
 138                 status = "disabled";
 139         };
 140
 141         bus_wcore: bus-wcore {
 142                 compatible = "samsung,exynos-bus";
 143                 clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
 144                 clock-names = "bus";
 145                 status = "disabled";
 146         };
 147
 148         /*
 149          * The 'cpus' node is not present here but instead it is provided
 150          * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
 151          */
 152
 153         cluster_a15_opp_table: opp-table-0 {
 154                 compatible = "operating-points-v2";
 155                 opp-shared;
 156
 157                 opp-1800000000 {
 158                         opp-hz = /bits/ 64 <1800000000>;
 159                         opp-microvolt = <1250000 1250000 1500000>;
 160                         clock-latency-ns = <140000>;
 161                 };
 162                 opp-1700000000 {
 163                         opp-hz = /bits/ 64 <1700000000>;
 164                         opp-microvolt = <1212500 1212500 1500000>;
 165                         clock-latency-ns = <140000>;
 166                 };
 167                 opp-1600000000 {
 168                         opp-hz = /bits/ 64 <1600000000>;
 169                         opp-microvolt = <1175000 1175000 1500000>;
 170                         clock-latency-ns = <140000>;
 171                 };
 172                 opp-1500000000 {
 173                         opp-hz = /bits/ 64 <1500000000>;
 174                         opp-microvolt = <1137500 1137500 1500000>;
 175                         clock-latency-ns = <140000>;
 176                 };
 177                 opp-1400000000 {
 178                         opp-hz = /bits/ 64 <1400000000>;
 179                         opp-microvolt = <1112500 1112500 1500000>;
 180                         clock-latency-ns = <140000>;
 181                 };
 182                 opp-1300000000 {
 183                         opp-hz = /bits/ 64 <1300000000>;
 184                         opp-microvolt = <1062500 1062500 1500000>;
 185                         clock-latency-ns = <140000>;
 186                 };
 187                 opp-1200000000 {
 188                         opp-hz = /bits/ 64 <1200000000>;
 189                         opp-microvolt = <1037500 1037500 1500000>;
 190                         clock-latency-ns = <140000>;
 191                 };
 192                 opp-1100000000 {
 193                         opp-hz = /bits/ 64 <1100000000>;
 194                         opp-microvolt = <1012500 1012500 1500000>;
 195                         clock-latency-ns = <140000>;
 196                 };
 197                 opp-1000000000 {
 198                         opp-hz = /bits/ 64 <1000000000>;
 199                         opp-microvolt = < 987500 987500 1500000>;
 200                         clock-latency-ns = <140000>;
 201                 };
 202                 opp-900000000 {
 203                         opp-hz = /bits/ 64 <900000000>;
 204                         opp-microvolt = < 962500 962500 1500000>;
 205                         clock-latency-ns = <140000>;
 206                 };
 207                 opp-800000000 {
 208                         opp-hz = /bits/ 64 <800000000>;
 209                         opp-microvolt = < 937500 937500 1500000>;
 210                         clock-latency-ns = <140000>;
 211                 };
 212                 opp-700000000 {
 213                         opp-hz = /bits/ 64 <700000000>;
 214                         opp-microvolt = < 912500 912500 1500000>;
 215                         clock-latency-ns = <140000>;
 216                 };
 217         };
 218
 219         cluster_a7_opp_table: opp-table-1 {
 220                 compatible = "operating-points-v2";
 221                 opp-shared;
 222
 223                 opp-1300000000 {
 224                         opp-hz = /bits/ 64 <1300000000>;
 225                         opp-microvolt = <1275000>;
 226                         clock-latency-ns = <140000>;
 227                 };
 228                 opp-1200000000 {
 229                         opp-hz = /bits/ 64 <1200000000>;
 230                         opp-microvolt = <1212500>;
 231                         clock-latency-ns = <140000>;
 232                 };
 233                 opp-1100000000 {
 234                         opp-hz = /bits/ 64 <1100000000>;
 235                         opp-microvolt = <1162500>;
 236                         clock-latency-ns = <140000>;
 237                 };
 238                 opp-1000000000 {
 239                         opp-hz = /bits/ 64 <1000000000>;
 240                         opp-microvolt = <1112500>;
 241                         clock-latency-ns = <140000>;
 242                 };
 243                 opp-900000000 {
 244                         opp-hz = /bits/ 64 <900000000>;
 245                         opp-microvolt = <1062500>;
 246                         clock-latency-ns = <140000>;
 247                 };
 248                 opp-800000000 {
 249                         opp-hz = /bits/ 64 <800000000>;
 250                         opp-microvolt = <1025000>;
 251                         clock-latency-ns = <140000>;
 252                 };
 253                 opp-700000000 {
 254                         opp-hz = /bits/ 64 <700000000>;
 255                         opp-microvolt = <975000>;
 256                         clock-latency-ns = <140000>;
 257                 };
 258                 opp-600000000 {
 259                         opp-hz = /bits/ 64 <600000000>;
 260                         opp-microvolt = <937500>;
 261                         clock-latency-ns = <140000>;
 262                 };
 263         };
 264
 265         soc: soc {
 266                 cci: cci@10d20000 {
 267                         compatible = "arm,cci-400";
 268                         #address-cells = <1>;
 269                         #size-cells = <1>;
 270                         reg = <0x10d20000 0x1000>;
 271                         ranges = <0x0 0x10d20000 0x6000>;
 272
 273                         cci_control0: slave-if@4000 {
 274                                 compatible = "arm,cci-400-ctrl-if";
 275                                 interface-type = "ace";
 276                                 reg = <0x4000 0x1000>;
 277                         };
 278                         cci_control1: slave-if@5000 {
 279                                 compatible = "arm,cci-400-ctrl-if";
 280                                 interface-type = "ace";
 281                                 reg = <0x5000 0x1000>;
 282                         };
 283                 };
 284
 285                 clock: clock-controller@10010000 {
 286                         compatible = "samsung,exynos5420-clock", "syscon";
 287                         reg = <0x10010000 0x30000>;
 288                         #clock-cells = <1>;
 289                 };
 290
 291                 clock_audss: audss-clock-controller@3810000 {
 292                         compatible = "samsung,exynos5420-audss-clock";
 293                         reg = <0x03810000 0x0c>;
 294                         #clock-cells = <1>;
 295                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
 296                                  <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
 297                         clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 298                         power-domains = <&mau_pd>;
 299                 };
 300
 301                 mfc: codec@11000000 {
 302                         compatible = "samsung,mfc-v7";
 303                         reg = <0x11000000 0x10000>;
 304                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 305                         clocks = <&clock CLK_MFC>;
 306                         clock-names = "mfc";
 307                         power-domains = <&mfc_pd>;
 308                         iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 309                         iommu-names = "left", "right";
 310                 };
 311
 312                 mmc_0: mmc@12200000 {
 313                         compatible = "samsung,exynos5420-dw-mshc-smu";
 314                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 315                         #address-cells = <1>;
 316                         #size-cells = <0>;
 317                         reg = <0x12200000 0x2000>;
 318                         clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 319                         clock-names = "biu", "ciu";
 320                         fifo-depth = <0x40>;
 321                         status = "disabled";
 322                 };
 323
 324                 mmc_1: mmc@12210000 {
 325                         compatible = "samsung,exynos5420-dw-mshc-smu";
 326                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 327                         #address-cells = <1>;
 328                         #size-cells = <0>;
 329                         reg = <0x12210000 0x2000>;
 330                         clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 331                         clock-names = "biu", "ciu";
 332                         fifo-depth = <0x40>;
 333                         status = "disabled";
 334                 };
 335
 336                 mmc_2: mmc@12220000 {
 337                         compatible = "samsung,exynos5420-dw-mshc";
 338                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 339                         #address-cells = <1>;
 340                         #size-cells = <0>;
 341                         reg = <0x12220000 0x1000>;
 342                         clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 343                         clock-names = "biu", "ciu";
 344                         fifo-depth = <0x40>;
 345                         status = "disabled";
 346                 };
 347
 348                 dmc: memory-controller@10c20000 {
 349                         compatible = "samsung,exynos5422-dmc";
 350                         reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
 351                         clocks = <&clock CLK_FOUT_SPLL>,
 352                                  <&clock CLK_MOUT_SCLK_SPLL>,
 353                                  <&clock CLK_FF_DOUT_SPLL2>,
 354                                  <&clock CLK_FOUT_BPLL>,
 355                                  <&clock CLK_MOUT_BPLL>,
 356                                  <&clock CLK_SCLK_BPLL>,
 357                                  <&clock CLK_MOUT_MX_MSPLL_CCORE>,
 358                                  <&clock CLK_MOUT_MCLK_CDREX>;
 359                         clock-names = "fout_spll",
 360                                       "mout_sclk_spll",
 361                                       "ff_dout_spll2",
 362                                       "fout_bpll",
 363                                       "mout_bpll",
 364                                       "sclk_bpll",
 365                                       "mout_mx_mspll_ccore",
 366                                       "mout_mclk_cdrex";
 367                         samsung,syscon-clk = <&clock>;
 368                         status = "disabled";
 369                 };
 370
 371                 nocp_mem0_0: nocp@10ca1000 {
 372                         compatible = "samsung,exynos5420-nocp";
 373                         reg = <0x10ca1000 0x200>;
 374                         status = "disabled";
 375                 };
 376
 377                 nocp_mem0_1: nocp@10ca1400 {
 378                         compatible = "samsung,exynos5420-nocp";
 379                         reg = <0x10ca1400 0x200>;
 380                         status = "disabled";
 381                 };
 382
 383                 nocp_mem1_0: nocp@10ca1800 {
 384                         compatible = "samsung,exynos5420-nocp";
 385                         reg = <0x10ca1800 0x200>;
 386                         status = "disabled";
 387                 };
 388
 389                 nocp_mem1_1: nocp@10ca1c00 {
 390                         compatible = "samsung,exynos5420-nocp";
 391                         reg = <0x10ca1c00 0x200>;
 392                         status = "disabled";
 393                 };
 394
 395                 nocp_g3d_0: nocp@11a51000 {
 396                         compatible = "samsung,exynos5420-nocp";
 397                         reg = <0x11a51000 0x200>;
 398                         status = "disabled";
 399                 };
 400
 401                 nocp_g3d_1: nocp@11a51400 {
 402                         compatible = "samsung,exynos5420-nocp";
 403                         reg = <0x11a51400 0x200>;
 404                         status = "disabled";
 405                 };
 406
 407                 ppmu_dmc0_0: ppmu@10d00000 {
 408                         compatible = "samsung,exynos-ppmu";
 409                         reg = <0x10d00000 0x2000>;
 410                         clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
 411                         clock-names = "ppmu";
 412                         events {
 413                                 ppmu_event3_dmc0_0: ppmu-event3-dmc0-0 {
 414                                         event-name = "ppmu-event3-dmc0-0";
 415                                 };
 416                         };
 417                 };
 418
 419                 ppmu_dmc0_1: ppmu@10d10000 {
 420                         compatible = "samsung,exynos-ppmu";
 421                         reg = <0x10d10000 0x2000>;
 422                         clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
 423                         clock-names = "ppmu";
 424                         events {
 425                                 ppmu_event3_dmc0_1: ppmu-event3-dmc0-1 {
 426                                         event-name = "ppmu-event3-dmc0-1";
 427                                 };
 428                         };
 429                 };
 430
 431                 ppmu_dmc1_0: ppmu@10d60000 {
 432                         compatible = "samsung,exynos-ppmu";
 433                         reg = <0x10d60000 0x2000>;
 434                         clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
 435                         clock-names = "ppmu";
 436                         events {
 437                                 ppmu_event3_dmc1_0: ppmu-event3-dmc1-0 {
 438                                         event-name = "ppmu-event3-dmc1-0";
 439                                 };
 440                         };
 441                 };
 442
 443                 ppmu_dmc1_1: ppmu@10d70000 {
 444                         compatible = "samsung,exynos-ppmu";
 445                         reg = <0x10d70000 0x2000>;
 446                         clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
 447                         clock-names = "ppmu";
 448                         events {
 449                                 ppmu_event3_dmc1_1: ppmu-event3-dmc1-1 {
 450                                         event-name = "ppmu-event3-dmc1-1";
 451                                 };
 452                         };
 453                 };
 454
 455                 gsc_pd: power-domain@10044000 {
 456                         compatible = "samsung,exynos4210-pd";
 457                         reg = <0x10044000 0x20>;
 458                         #power-domain-cells = <0>;
 459                         label = "GSC";
 460                 };
 461
 462                 isp_pd: power-domain@10044020 {
 463                         compatible = "samsung,exynos4210-pd";
 464                         reg = <0x10044020 0x20>;
 465                         #power-domain-cells = <0>;
 466                         label = "ISP";
 467                 };
 468
 469                 mfc_pd: power-domain@10044060 {
 470                         compatible = "samsung,exynos4210-pd";
 471                         reg = <0x10044060 0x20>;
 472                         #power-domain-cells = <0>;
 473                         label = "MFC";
 474                 };
 475
 476                 g3d_pd: power-domain@10044080 {
 477                         compatible = "samsung,exynos4210-pd";
 478                         reg = <0x10044080 0x20>;
 479                         #power-domain-cells = <0>;
 480                         label = "G3D";
 481                 };
 482
 483                 disp_pd: power-domain@100440c0 {
 484                         compatible = "samsung,exynos4210-pd";
 485                         reg = <0x100440c0 0x20>;
 486                         #power-domain-cells = <0>;
 487                         label = "DISP";
 488                 };
 489
 490                 mau_pd: power-domain@100440e0 {
 491                         compatible = "samsung,exynos4210-pd";
 492                         reg = <0x100440e0 0x20>;
 493                         #power-domain-cells = <0>;
 494                         label = "MAU";
 495                 };
 496
 497                 msc_pd: power-domain@10044120 {
 498                         compatible = "samsung,exynos4210-pd";
 499                         reg = <0x10044120 0x20>;
 500                         #power-domain-cells = <0>;
 501                         label = "MSC";
 502                 };
 503
 504                 pinctrl_0: pinctrl@13400000 {
 505                         compatible = "samsung,exynos5420-pinctrl";
 506                         reg = <0x13400000 0x1000>;
 507                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 508
 509                         wakeup-interrupt-controller {
 510                                 compatible = "samsung,exynos4210-wakeup-eint";
 511                                 interrupt-parent = <&gic>;
 512                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 513                         };
 514                 };
 515
 516                 pinctrl_1: pinctrl@13410000 {
 517                         compatible = "samsung,exynos5420-pinctrl";
 518                         reg = <0x13410000 0x1000>;
 519                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 520                 };
 521
 522                 pinctrl_2: pinctrl@14000000 {
 523                         compatible = "samsung,exynos5420-pinctrl";
 524                         reg = <0x14000000 0x1000>;
 525                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 526                 };
 527
 528                 pinctrl_3: pinctrl@14010000 {
 529                         compatible = "samsung,exynos5420-pinctrl";
 530                         reg = <0x14010000 0x1000>;
 531                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 532                 };
 533
 534                 pinctrl_4: pinctrl@3860000 {
 535                         compatible = "samsung,exynos5420-pinctrl";
 536                         reg = <0x03860000 0x1000>;
 537                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 538                         power-domains = <&mau_pd>;
 539                 };
 540
 541                 adma: dma-controller@3880000 {
 542                         compatible = "arm,pl330", "arm,primecell";
 543                         reg = <0x03880000 0x1000>;
 544                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 545                         clocks = <&clock_audss EXYNOS_ADMA>;
 546                         clock-names = "apb_pclk";
 547                         #dma-cells = <1>;
 548                         power-domains = <&mau_pd>;
 549                 };
 550
 551                 pdma0: dma-controller@121a0000 {
 552                         compatible = "arm,pl330", "arm,primecell";
 553                         reg = <0x121a0000 0x1000>;
 554                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 555                         clocks = <&clock CLK_PDMA0>;
 556                         clock-names = "apb_pclk";
 557                         #dma-cells = <1>;
 558                 };
 559
 560                 pdma1: dma-controller@121b0000 {
 561                         compatible = "arm,pl330", "arm,primecell";
 562                         reg = <0x121b0000 0x1000>;
 563                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 564                         clocks = <&clock CLK_PDMA1>;
 565                         clock-names = "apb_pclk";
 566                         #dma-cells = <1>;
 567                 };
 568
 569                 mdma0: dma-controller@10800000 {
 570                         compatible = "arm,pl330", "arm,primecell";
 571                         reg = <0x10800000 0x1000>;
 572                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 573                         clocks = <&clock CLK_MDMA0>;
 574                         clock-names = "apb_pclk";
 575                         #dma-cells = <1>;
 576                 };
 577
 578                 mdma1: dma-controller@11c10000 {
 579                         compatible = "arm,pl330", "arm,primecell";
 580                         reg = <0x11c10000 0x1000>;
 581                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 582                         clocks = <&clock CLK_MDMA1>;
 583                         clock-names = "apb_pclk";
 584                         #dma-cells = <1>;
 585                         /*
 586                          * MDMA1 can support both secure and non-secure
 587                          * AXI transactions. When this is enabled in
 588                          * the kernel for boards that run in secure
 589                          * mode, we are getting imprecise external
 590                          * aborts causing the kernel to oops.
 591                          */
 592                         status = "disabled";
 593                 };
 594
 595                 i2s0: i2s@3830000 {
 596                         compatible = "samsung,exynos5420-i2s";
 597                         reg = <0x03830000 0x100>;
 598                         dmas = <&adma 0>,
 599                                 <&adma 2>,
 600                                 <&adma 1>;
 601                         dma-names = "tx", "rx", "tx-sec";
 602                         clocks = <&clock_audss EXYNOS_I2S_BUS>,
 603                                 <&clock_audss EXYNOS_I2S_BUS>,
 604                                 <&clock_audss EXYNOS_SCLK_I2S>;
 605                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 606                         #clock-cells = <1>;
 607                         clock-output-names = "i2s_cdclk0";
 608                         #sound-dai-cells = <1>;
 609                         samsung,idma-addr = <0x03000000>;
 610                         pinctrl-names = "default";
 611                         pinctrl-0 = <&i2s0_bus>;
 612                         power-domains = <&mau_pd>;
 613                         status = "disabled";
 614                 };
 615
 616                 i2s1: i2s@12d60000 {
 617                         compatible = "samsung,exynos5420-i2s";
 618                         reg = <0x12d60000 0x100>;
 619                         dmas = <&pdma1 12>,
 620                                 <&pdma1 11>;
 621                         dma-names = "tx", "rx";
 622                         clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
 623                         clock-names = "iis", "i2s_opclk0";
 624                         #clock-cells = <1>;
 625                         clock-output-names = "i2s_cdclk1";
 626                         #sound-dai-cells = <1>;
 627                         pinctrl-names = "default";
 628                         pinctrl-0 = <&i2s1_bus>;
 629                         status = "disabled";
 630                 };
 631
 632                 i2s2: i2s@12d70000 {
 633                         compatible = "samsung,exynos5420-i2s";
 634                         reg = <0x12d70000 0x100>;
 635                         dmas = <&pdma0 12>,
 636                                 <&pdma0 11>;
 637                         dma-names = "tx", "rx";
 638                         clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
 639                         clock-names = "iis", "i2s_opclk0";
 640                         #clock-cells = <1>;
 641                         clock-output-names = "i2s_cdclk2";
 642                         #sound-dai-cells = <1>;
 643                         pinctrl-names = "default";
 644                         pinctrl-0 = <&i2s2_bus>;
 645                         status = "disabled";
 646                 };
 647
 648                 spi_0: spi@12d20000 {
 649                         compatible = "samsung,exynos4210-spi";
 650                         reg = <0x12d20000 0x100>;
 651                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 652                         dmas = <&pdma0 5
 653                                 &pdma0 4>;
 654                         dma-names = "tx", "rx";
 655                         #address-cells = <1>;
 656                         #size-cells = <0>;
 657                         pinctrl-names = "default";
 658                         pinctrl-0 = <&spi0_bus>;
 659                         clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 660                         clock-names = "spi", "spi_busclk0";
 661                         status = "disabled";
 662                 };
 663
 664                 spi_1: spi@12d30000 {
 665                         compatible = "samsung,exynos4210-spi";
 666                         reg = <0x12d30000 0x100>;
 667                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 668                         dmas = <&pdma1 5
 669                                 &pdma1 4>;
 670                         dma-names = "tx", "rx";
 671                         #address-cells = <1>;
 672                         #size-cells = <0>;
 673                         pinctrl-names = "default";
 674                         pinctrl-0 = <&spi1_bus>;
 675                         clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 676                         clock-names = "spi", "spi_busclk0";
 677                         status = "disabled";
 678                 };
 679
 680                 spi_2: spi@12d40000 {
 681                         compatible = "samsung,exynos4210-spi";
 682                         reg = <0x12d40000 0x100>;
 683                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 684                         dmas = <&pdma0 7
 685                                 &pdma0 6>;
 686                         dma-names = "tx", "rx";
 687                         #address-cells = <1>;
 688                         #size-cells = <0>;
 689                         pinctrl-names = "default";
 690                         pinctrl-0 = <&spi2_bus>;
 691                         clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 692                         clock-names = "spi", "spi_busclk0";
 693                         status = "disabled";
 694                 };
 695
 696                 dsi: dsi@14500000 {
 697                         compatible = "samsung,exynos5410-mipi-dsi";
 698                         reg = <0x14500000 0x10000>;
 699                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 700                         phys = <&mipi_phy 1>;
 701                         phy-names = "dsim";
 702                         clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
 703                         clock-names = "bus_clk", "pll_clk";
 704                         #address-cells = <1>;
 705                         #size-cells = <0>;
 706                         status = "disabled";
 707                 };
 708
 709                 hsi2c_8: i2c@12e00000 {
 710                         compatible = "samsung,exynos5250-hsi2c";
 711                         reg = <0x12e00000 0x1000>;
 712                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 713                         #address-cells = <1>;
 714                         #size-cells = <0>;
 715                         pinctrl-names = "default";
 716                         pinctrl-0 = <&i2c8_hs_bus>;
 717                         clocks = <&clock CLK_USI4>;
 718                         clock-names = "hsi2c";
 719                         status = "disabled";
 720                 };
 721
 722                 hsi2c_9: i2c@12e10000 {
 723                         compatible = "samsung,exynos5250-hsi2c";
 724                         reg = <0x12e10000 0x1000>;
 725                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 726                         #address-cells = <1>;
 727                         #size-cells = <0>;
 728                         pinctrl-names = "default";
 729                         pinctrl-0 = <&i2c9_hs_bus>;
 730                         clocks = <&clock CLK_USI5>;
 731                         clock-names = "hsi2c";
 732                         status = "disabled";
 733                 };
 734
 735                 hsi2c_10: i2c@12e20000 {
 736                         compatible = "samsung,exynos5250-hsi2c";
 737                         reg = <0x12e20000 0x1000>;
 738                         interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 739                         #address-cells = <1>;
 740                         #size-cells = <0>;
 741                         pinctrl-names = "default";
 742                         pinctrl-0 = <&i2c10_hs_bus>;
 743                         clocks = <&clock CLK_USI6>;
 744                         clock-names = "hsi2c";
 745                         status = "disabled";
 746                 };
 747
 748                 hdmi: hdmi@14530000 {
 749                         compatible = "samsung,exynos5420-hdmi";
 750                         reg = <0x14530000 0x70000>;
 751                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 752                         clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 753                                  <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 754                                  <&clock CLK_MOUT_HDMI>;
 755                         clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 756                                 "sclk_hdmiphy", "mout_hdmi";
 757                         phy = <&hdmiphy>;
 758                         samsung,syscon-phandle = <&pmu_system_controller>;
 759                         status = "disabled";
 760                         power-domains = <&disp_pd>;
 761                         #sound-dai-cells = <0>;
 762                 };
 763
 764                 hdmiphy: hdmi-phy@145d0000 {
 765                         reg = <0x145d0000 0x20>;
 766                 };
 767
 768                 hdmicec: cec@101b0000 {
 769                         compatible = "samsung,s5p-cec";
 770                         reg = <0x101b0000 0x200>;
 771                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 772                         clocks = <&clock CLK_HDMI_CEC>;
 773                         clock-names = "hdmicec";
 774                         samsung,syscon-phandle = <&pmu_system_controller>;
 775                         hdmi-phandle = <&hdmi>;
 776                         pinctrl-names = "default";
 777                         pinctrl-0 = <&hdmi_cec>;
 778                         status = "disabled";
 779                 };
 780
 781                 mixer: mixer@14450000 {
 782                         compatible = "samsung,exynos5420-mixer";
 783                         reg = <0x14450000 0x10000>;
 784                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 785                         clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 786                                  <&clock CLK_SCLK_HDMI>;
 787                         clock-names = "mixer", "hdmi", "sclk_hdmi";
 788                         power-domains = <&disp_pd>;
 789                         iommus = <&sysmmu_tv>;
 790                         status = "disabled";
 791                 };
 792
 793                 rotator: rotator@11c00000 {
 794                         compatible = "samsung,exynos5250-rotator";
 795                         reg = <0x11c00000 0x64>;
 796                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 797                         clocks = <&clock CLK_ROTATOR>;
 798                         clock-names = "rotator";
 799                         iommus = <&sysmmu_rotator>;
 800                 };
 801
 802                 gsc_0: video-scaler@13e00000 {
 803                         compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
 804                         reg = <0x13e00000 0x1000>;
 805                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 806                         clocks = <&clock CLK_GSCL0>;
 807                         clock-names = "gscl";
 808                         power-domains = <&gsc_pd>;
 809                         iommus = <&sysmmu_gscl0>;
 810                 };
 811
 812                 gsc_1: video-scaler@13e10000 {
 813                         compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
 814                         reg = <0x13e10000 0x1000>;
 815                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 816                         clocks = <&clock CLK_GSCL1>;
 817                         clock-names = "gscl";
 818                         power-domains = <&gsc_pd>;
 819                         iommus = <&sysmmu_gscl1>;
 820                 };
 821
 822                 gpu: gpu@11800000 {
 823                         compatible = "samsung,exynos5420-mali", "arm,mali-t628";
 824                         reg = <0x11800000 0x5000>;
 825                         interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
 826                                      <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 827                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 828                         interrupt-names = "job", "mmu", "gpu";
 829
 830                         clocks = <&clock CLK_G3D>;
 831                         clock-names = "core";
 832                         power-domains = <&g3d_pd>;
 833                         operating-points-v2 = <&gpu_opp_table>;
 834
 835                         status = "disabled";
 836                         #cooling-cells = <2>;
 837
 838                         gpu_opp_table: opp-table {
 839                                 compatible = "operating-points-v2";
 840
 841                                 opp-177000000 {
 842                                         opp-hz = /bits/ 64 <177000000>;
 843                                         opp-microvolt = <812500>;
 844                                 };
 845                                 opp-266000000 {
 846                                         opp-hz = /bits/ 64 <266000000>;
 847                                         opp-microvolt = <862500>;
 848                                 };
 849                                 opp-350000000 {
 850                                         opp-hz = /bits/ 64 <350000000>;
 851                                         opp-microvolt = <912500>;
 852                                 };
 853                                 opp-420000000 {
 854                                         opp-hz = /bits/ 64 <420000000>;
 855                                         opp-microvolt = <962500>;
 856                                 };
 857                                 opp-480000000 {
 858                                         opp-hz = /bits/ 64 <480000000>;
 859                                         opp-microvolt = <1000000>;
 860                                 };
 861                                 opp-543000000 {
 862                                         opp-hz = /bits/ 64 <543000000>;
 863                                         opp-microvolt = <1037500>;
 864                                 };
 865                                 opp-600000000 {
 866                                         opp-hz = /bits/ 64 <600000000>;
 867                                         opp-microvolt = <1150000>;
 868                                 };
 869                         };
 870                 };
 871
 872                 scaler_0: scaler@12800000 {
 873                         compatible = "samsung,exynos5420-scaler";
 874                         reg = <0x12800000 0x1294>;
 875                         interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>;
 876                         clocks = <&clock CLK_MSCL0>;
 877                         clock-names = "mscl";
 878                         power-domains = <&msc_pd>;
 879                         iommus = <&sysmmu_scaler0r>, <&sysmmu_scaler0w>;
 880                 };
 881
 882                 scaler_1: scaler@12810000 {
 883                         compatible = "samsung,exynos5420-scaler";
 884                         reg = <0x12810000 0x1294>;
 885                         interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>;
 886                         clocks = <&clock CLK_MSCL1>;
 887                         clock-names = "mscl";
 888                         power-domains = <&msc_pd>;
 889                         iommus = <&sysmmu_scaler1r>, <&sysmmu_scaler1w>;
 890                 };
 891
 892                 scaler_2: scaler@12820000 {
 893                         compatible = "samsung,exynos5420-scaler";
 894                         reg = <0x12820000 0x1294>;
 895                         interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>;
 896                         clocks = <&clock CLK_MSCL2>;
 897                         clock-names = "mscl";
 898                         power-domains = <&msc_pd>;
 899                         iommus = <&sysmmu_scaler2r>, <&sysmmu_scaler2w>;
 900                 };
 901
 902                 jpeg_0: jpeg@11f50000 {
 903                         compatible = "samsung,exynos5420-jpeg";
 904                         reg = <0x11f50000 0x1000>;
 905                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 906                         clock-names = "jpeg";
 907                         clocks = <&clock CLK_JPEG>;
 908                         iommus = <&sysmmu_jpeg0>;
 909                 };
 910
 911                 jpeg_1: jpeg@11f60000 {
 912                         compatible = "samsung,exynos5420-jpeg";
 913                         reg = <0x11f60000 0x1000>;
 914                         interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 915                         clock-names = "jpeg";
 916                         clocks = <&clock CLK_JPEG2>;
 917                         iommus = <&sysmmu_jpeg1>;
 918                 };
 919
 920                 pmu_system_controller: system-controller@10040000 {
 921                         compatible = "samsung,exynos5420-pmu", "simple-mfd", "syscon";
 922                         reg = <0x10040000 0x5000>;
 923                         clock-names = "clkout16";
 924                         clocks = <&clock CLK_FIN_PLL>;
 925                         #clock-cells = <1>;
 926                         interrupt-controller;
 927                         #interrupt-cells = <3>;
 928                         interrupt-parent = <&gic>;
 929
 930                         dp_phy: dp-phy {
 931                                 compatible = "samsung,exynos5420-dp-video-phy";
 932                                 #phy-cells = <0>;
 933                         };
 934
 935                         mipi_phy: mipi-phy {
 936                                 compatible = "samsung,exynos5420-mipi-video-phy";
 937                                 #phy-cells = <1>;
 938                         };
 939                 };
 940
 941                 tmu_cpu0: tmu@10060000 {
 942                         compatible = "samsung,exynos5420-tmu";
 943                         reg = <0x10060000 0x100>;
 944                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 945                         clocks = <&clock CLK_TMU>;
 946                         clock-names = "tmu_apbif";
 947                         #thermal-sensor-cells = <0>;
 948                 };
 949
 950                 tmu_cpu1: tmu@10064000 {
 951                         compatible = "samsung,exynos5420-tmu";
 952                         reg = <0x10064000 0x100>;
 953                         interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
 954                         clocks = <&clock CLK_TMU>;
 955                         clock-names = "tmu_apbif";
 956                         #thermal-sensor-cells = <0>;
 957                 };
 958
 959                 tmu_cpu2: tmu@10068000 {
 960                         compatible = "samsung,exynos5420-tmu-ext-triminfo";
 961                         reg = <0x10068000 0x100>, <0x1006c000 0x4>;
 962                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 963                         clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
 964                         clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 965                         #thermal-sensor-cells = <0>;
 966                 };
 967
 968                 tmu_cpu3: tmu@1006c000 {
 969                         compatible = "samsung,exynos5420-tmu-ext-triminfo";
 970                         reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
 971                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
 972                         clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
 973                         clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 974                         #thermal-sensor-cells = <0>;
 975                 };
 976
 977                 tmu_gpu: tmu@100a0000 {
 978                         compatible = "samsung,exynos5420-tmu-ext-triminfo";
 979                         reg = <0x100a0000 0x100>, <0x10068000 0x4>;
 980                         interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
 981                         clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
 982                         clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 983                         #thermal-sensor-cells = <0>;
 984                 };
 985
 986                 sysmmu_g2dr: sysmmu@10a60000 {
 987                         compatible = "samsung,exynos-sysmmu";
 988                         reg = <0x10a60000 0x1000>;
 989                         interrupt-parent = <&combiner>;
 990                         interrupts = <24 5>;
 991                         clock-names = "sysmmu", "master";
 992                         clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
 993                         #iommu-cells = <0>;
 994                 };
 995
 996                 sysmmu_g2dw: sysmmu@10a70000 {
 997                         compatible = "samsung,exynos-sysmmu";
 998                         reg = <0x10a70000 0x1000>;
 999                         interrupt-parent = <&combiner>;
1000                         interrupts = <22 2>;
1001                         clock-names = "sysmmu", "master";
1002                         clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
1003                         #iommu-cells = <0>;
1004                 };
1005
1006                 sysmmu_tv: sysmmu@14650000 {
1007                         compatible = "samsung,exynos-sysmmu";
1008                         reg = <0x14650000 0x1000>;
1009                         interrupt-parent = <&combiner>;
1010                         interrupts = <7 4>;
1011                         clock-names = "sysmmu", "master";
1012                         clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
1013                         power-domains = <&disp_pd>;
1014                         #iommu-cells = <0>;
1015                 };
1016
1017                 sysmmu_gscl0: sysmmu@13e80000 {
1018                         compatible = "samsung,exynos-sysmmu";
1019                         reg = <0x13e80000 0x1000>;
1020                         interrupt-parent = <&combiner>;
1021                         interrupts = <2 0>;
1022                         clock-names = "sysmmu", "master";
1023                         clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
1024                         power-domains = <&gsc_pd>;
1025                         #iommu-cells = <0>;
1026                 };
1027
1028                 sysmmu_gscl1: sysmmu@13e90000 {
1029                         compatible = "samsung,exynos-sysmmu";
1030                         reg = <0x13e90000 0x1000>;
1031                         interrupt-parent = <&combiner>;
1032                         interrupts = <2 2>;
1033                         clock-names = "sysmmu", "master";
1034                         clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1035                         power-domains = <&gsc_pd>;
1036                         #iommu-cells = <0>;
1037                 };
1038
1039                 sysmmu_scaler0r: sysmmu@12880000 {
1040                         compatible = "samsung,exynos-sysmmu";
1041                         reg = <0x12880000 0x1000>;
1042                         interrupt-parent = <&combiner>;
1043                         interrupts = <22 4>;
1044                         clock-names = "sysmmu", "master";
1045                         clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
1046                         power-domains = <&msc_pd>;
1047                         #iommu-cells = <0>;
1048                 };
1049
1050                 sysmmu_scaler1r: sysmmu@12890000 {
1051                         compatible = "samsung,exynos-sysmmu";
1052                         reg = <0x12890000 0x1000>;
1053                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1054                         clock-names = "sysmmu", "master";
1055                         clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
1056                         power-domains = <&msc_pd>;
1057                         #iommu-cells = <0>;
1058                 };
1059
1060                 sysmmu_scaler2r: sysmmu@128a0000 {
1061                         compatible = "samsung,exynos-sysmmu";
1062                         reg = <0x128a0000 0x1000>;
1063                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1064                         clock-names = "sysmmu", "master";
1065                         clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1066                         power-domains = <&msc_pd>;
1067                         #iommu-cells = <0>;
1068                 };
1069
1070                 sysmmu_scaler0w: sysmmu@128c0000 {
1071                         compatible = "samsung,exynos-sysmmu";
1072                         reg = <0x128c0000 0x1000>;
1073                         interrupt-parent = <&combiner>;
1074                         interrupts = <27 2>;
1075                         clock-names = "sysmmu", "master";
1076                         clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
1077                         power-domains = <&msc_pd>;
1078                         #iommu-cells = <0>;
1079                 };
1080
1081                 sysmmu_scaler1w: sysmmu@128d0000 {
1082                         compatible = "samsung,exynos-sysmmu";
1083                         reg = <0x128d0000 0x1000>;
1084                         interrupt-parent = <&combiner>;
1085                         interrupts = <22 6>;
1086                         clock-names = "sysmmu", "master";
1087                         clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
1088                         power-domains = <&msc_pd>;
1089                         #iommu-cells = <0>;
1090                 };
1091
1092                 sysmmu_scaler2w: sysmmu@128e0000 {
1093                         compatible = "samsung,exynos-sysmmu";
1094                         reg = <0x128e0000 0x1000>;
1095                         interrupt-parent = <&combiner>;
1096                         interrupts = <19 6>;
1097                         clock-names = "sysmmu", "master";
1098                         clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1099                         power-domains = <&msc_pd>;
1100                         #iommu-cells = <0>;
1101                 };
1102
1103                 sysmmu_rotator: sysmmu@11d40000 {
1104                         compatible = "samsung,exynos-sysmmu";
1105                         reg = <0x11d40000 0x1000>;
1106                         interrupt-parent = <&combiner>;
1107                         interrupts = <4 0>;
1108                         clock-names = "sysmmu", "master";
1109                         clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
1110                         #iommu-cells = <0>;
1111                 };
1112
1113                 sysmmu_jpeg0: sysmmu@11f10000 {
1114                         compatible = "samsung,exynos-sysmmu";
1115                         reg = <0x11f10000 0x1000>;
1116                         interrupt-parent = <&combiner>;
1117                         interrupts = <4 2>;
1118                         clock-names = "sysmmu", "master";
1119                         clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
1120                         #iommu-cells = <0>;
1121                 };
1122
1123                 sysmmu_jpeg1: sysmmu@11f20000 {
1124                         compatible = "samsung,exynos-sysmmu";
1125                         reg = <0x11f20000 0x1000>;
1126                         interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
1127                         clock-names = "sysmmu", "master";
1128                         clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
1129                         #iommu-cells = <0>;
1130                 };
1131
1132                 sysmmu_mfc_l: sysmmu@11200000 {
1133                         compatible = "samsung,exynos-sysmmu";
1134                         reg = <0x11200000 0x1000>;
1135                         interrupt-parent = <&combiner>;
1136                         interrupts = <6 2>;
1137                         clock-names = "sysmmu", "master";
1138                         clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
1139                         power-domains = <&mfc_pd>;
1140                         #iommu-cells = <0>;
1141                 };
1142
1143                 sysmmu_mfc_r: sysmmu@11210000 {
1144                         compatible = "samsung,exynos-sysmmu";
1145                         reg = <0x11210000 0x1000>;
1146                         interrupt-parent = <&combiner>;
1147                         interrupts = <8 5>;
1148                         clock-names = "sysmmu", "master";
1149                         clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
1150                         power-domains = <&mfc_pd>;
1151                         #iommu-cells = <0>;
1152                 };
1153
1154                 sysmmu_fimd1_0: sysmmu@14640000 {
1155                         compatible = "samsung,exynos-sysmmu";
1156                         reg = <0x14640000 0x1000>;
1157                         interrupt-parent = <&combiner>;
1158                         interrupts = <3 2>;
1159                         clock-names = "sysmmu", "master";
1160                         clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
1161                         power-domains = <&disp_pd>;
1162                         #iommu-cells = <0>;
1163                 };
1164
1165                 sysmmu_fimd1_1: sysmmu@14680000 {
1166                         compatible = "samsung,exynos-sysmmu";
1167                         reg = <0x14680000 0x1000>;
1168                         interrupt-parent = <&combiner>;
1169                         interrupts = <3 0>;
1170                         clock-names = "sysmmu", "master";
1171                         clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
1172                         power-domains = <&disp_pd>;
1173                         #iommu-cells = <0>;
1174                 };
1175         };
1176
1177         thermal-zones {
1178                 cpu0_thermal: cpu0-thermal {
1179                         thermal-sensors = <&tmu_cpu0>;
1180                         #include "exynos5420-trip-points.dtsi"
1181                 };
1182                 cpu1_thermal: cpu1-thermal {
1183                         thermal-sensors = <&tmu_cpu1>;
1184                         #include "exynos5420-trip-points.dtsi"
1185                 };
1186                 cpu2_thermal: cpu2-thermal {
1187                         thermal-sensors = <&tmu_cpu2>;
1188                         #include "exynos5420-trip-points.dtsi"
1189                 };
1190                 cpu3_thermal: cpu3-thermal {
1191                         thermal-sensors = <&tmu_cpu3>;
1192                         #include "exynos5420-trip-points.dtsi"
1193                 };
1194                 gpu_thermal: gpu-thermal {
1195                         thermal-sensors = <&tmu_gpu>;
1196                         #include "exynos5420-trip-points.dtsi"
1197                 };
1198         };
1199 };
1200
1201 &adc {
1202         clocks = <&clock CLK_TSADC>;
1203         clock-names = "adc";
1204         samsung,syscon-phandle = <&pmu_system_controller>;
1205 };
1206
1207 &dp {
1208         clocks = <&clock CLK_DP1>;
1209         clock-names = "dp";
1210         phys = <&dp_phy>;
1211         phy-names = "dp";
1212         power-domains = <&disp_pd>;
1213 };
1214
1215 &fimd {
1216         compatible = "samsung,exynos5420-fimd";
1217         clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1218         clock-names = "sclk_fimd", "fimd";
1219         power-domains = <&disp_pd>;
1220         iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
1221         iommu-names = "m0", "m1";
1222 };
1223
1224 &g2d {
1225         iommus = <&sysmmu_g2dr>, <&sysmmu_g2dw>;
1226         clocks = <&clock CLK_G2D>;
1227         clock-names = "fimg2d";
1228         status = "okay";
1229 };
1230
1231 &i2c_0 {
1232         clocks = <&clock CLK_I2C0>;
1233         clock-names = "i2c";
1234         pinctrl-names = "default";
1235         pinctrl-0 = <&i2c0_bus>;
1236 };
1237
1238 &i2c_1 {
1239         clocks = <&clock CLK_I2C1>;
1240         clock-names = "i2c";
1241         pinctrl-names = "default";
1242         pinctrl-0 = <&i2c1_bus>;
1243 };
1244
1245 &i2c_2 {
1246         clocks = <&clock CLK_I2C2>;
1247         clock-names = "i2c";
1248         pinctrl-names = "default";
1249         pinctrl-0 = <&i2c2_bus>;
1250 };
1251
1252 &i2c_3 {
1253         clocks = <&clock CLK_I2C3>;
1254         clock-names = "i2c";
1255         pinctrl-names = "default";
1256         pinctrl-0 = <&i2c3_bus>;
1257 };
1258
1259 &hsi2c_4 {
1260         clocks = <&clock CLK_USI0>;
1261         clock-names = "hsi2c";
1262         pinctrl-names = "default";
1263         pinctrl-0 = <&i2c4_hs_bus>;
1264 };
1265
1266 &hsi2c_5 {
1267         clocks = <&clock CLK_USI1>;
1268         clock-names = "hsi2c";
1269         pinctrl-names = "default";
1270         pinctrl-0 = <&i2c5_hs_bus>;
1271 };
1272
1273 &hsi2c_6 {
1274         clocks = <&clock CLK_USI2>;
1275         clock-names = "hsi2c";
1276         pinctrl-names = "default";
1277         pinctrl-0 = <&i2c6_hs_bus>;
1278 };
1279
1280 &hsi2c_7 {
1281         clocks = <&clock CLK_USI3>;
1282         clock-names = "hsi2c";
1283         pinctrl-names = "default";
1284         pinctrl-0 = <&i2c7_hs_bus>;
1285 };
1286
1287 &mct {
1288         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
1289         clock-names = "fin_pll", "mct";
1290 };
1291
1292 &prng {
1293         clocks = <&clock CLK_SSS>;
1294         clock-names = "secss";
1295 };
1296
1297 &pwm {
1298         clocks = <&clock CLK_PWM>;
1299         clock-names = "timers";
1300 };
1301
1302 &rtc {
1303         clocks = <&clock CLK_RTC>;
1304         clock-names = "rtc";
1305         interrupt-parent = <&pmu_system_controller>;
1306         status = "disabled";
1307 };
1308
1309 &serial_0 {
1310         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1311         clock-names = "uart", "clk_uart_baud0";
1312         dmas = <&pdma0 13>, <&pdma0 14>;
1313         dma-names = "rx", "tx";
1314 };
1315
1316 &serial_1 {
1317         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1318         clock-names = "uart", "clk_uart_baud0";
1319         dmas = <&pdma1 15>, <&pdma1 16>;
1320         dma-names = "rx", "tx";
1321 };
1322
1323 &serial_2 {
1324         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1325         clock-names = "uart", "clk_uart_baud0";
1326         dmas = <&pdma0 15>, <&pdma0 16>;
1327         dma-names = "rx", "tx";
1328 };
1329
1330 &serial_3 {
1331         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1332         clock-names = "uart", "clk_uart_baud0";
1333         dmas = <&pdma1 17>, <&pdma1 18>;
1334         dma-names = "rx", "tx";
1335 };
1336
1337 &sss {
1338         clocks = <&clock CLK_SSS>;
1339         clock-names = "secss";
1340 };
1341
1342 &trng {
1343         clocks = <&clock CLK_SSS>;
1344         clock-names = "secss";
1345 };
1346
1347 &usbdrd3_0 {
1348         clocks = <&clock CLK_USBD300>;
1349         clock-names = "usbdrd30";
1350 };
1351
1352 &usbdrd_phy0 {
1353         clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
1354         clock-names = "phy", "ref";
1355         samsung,pmu-syscon = <&pmu_system_controller>;
1356 };
1357
1358 &usbdrd3_1 {
1359         clocks = <&clock CLK_USBD301>;
1360         clock-names = "usbdrd30";
1361 };
1362
1363 &usbdrd_dwc3_1 {
1364         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1365 };
1366
1367 &usbdrd_phy1 {
1368         clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
1369         clock-names = "phy", "ref";
1370         samsung,pmu-syscon = <&pmu_system_controller>;
1371 };
1372
1373 &usbhost1 {
1374         clocks = <&clock CLK_USBH20>;
1375         clock-names = "usbhost";
1376 };
1377
1378 &usbhost2 {
1379         clocks = <&clock CLK_USBH20>;
1380         clock-names = "usbhost";
1381 };
1382
1383 &usb2_phy {
1384         clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
1385         clock-names = "phy", "ref";
1386         samsung,sysreg-phandle = <&sysreg_system_controller>;
1387         samsung,pmureg-phandle = <&pmu_system_controller>;
1388 };
1389
1390 &watchdog {
1391         clocks = <&clock CLK_WDT>;
1392         clock-names = "watchdog";
1393         samsung,syscon-phandle = <&pmu_system_controller>;
1394 };
1395
1396 #include "exynos5420-pinctrl.dtsi"
1397 #include "exynos-syscon-restart.dtsi"