src/arm/imx27.dtsi

   1 /*
   2  * Copyright 2012 Sascha Hauer, Pengutronix
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include "imx27-pinfunc.h"
  13
  14 #include <dt-bindings/clock/imx27-clock.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/input/input.h>
  17 #include <dt-bindings/interrupt-controller/irq.h>
  18
  19 / {
  20         #address-cells = <1>;
  21         #size-cells = <1>;
  22         /*
  23          * The decompressor and also some bootloaders rely on a
  24          * pre-existing /chosen node to be available to insert the
  25          * command line and merge other ATAGS info.
  26          * Also for U-Boot there must be a pre-existing /memory node.
  27          */
  28         chosen {};
  29         memory { device_type = "memory"; reg = <0 0>; };
  30
  31         aliases {
  32                 ethernet0 = &fec;
  33                 gpio0 = &gpio1;
  34                 gpio1 = &gpio2;
  35                 gpio2 = &gpio3;
  36                 gpio3 = &gpio4;
  37                 gpio4 = &gpio5;
  38                 gpio5 = &gpio6;
  39                 i2c0 = &i2c1;
  40                 i2c1 = &i2c2;
  41                 serial0 = &uart1;
  42                 serial1 = &uart2;
  43                 serial2 = &uart3;
  44                 serial3 = &uart4;
  45                 serial4 = &uart5;
  46                 serial5 = &uart6;
  47                 spi0 = &cspi1;
  48                 spi1 = &cspi2;
  49                 spi2 = &cspi3;
  50         };
  51
  52         aitc: aitc-interrupt-controller@e0000000 {
  53                 compatible = "fsl,imx27-aitc", "fsl,avic";
  54                 interrupt-controller;
  55                 #interrupt-cells = <1>;
  56                 reg = <0x10040000 0x1000>;
  57         };
  58
  59         clocks {
  60                 #address-cells = <1>;
  61                 #size-cells = <0>;
  62
  63                 osc26m {
  64                         compatible = "fsl,imx-osc26m", "fixed-clock";
  65                         #clock-cells = <0>;
  66                         clock-frequency = <26000000>;
  67                 };
  68         };
  69
  70         cpus {
  71                 #size-cells = <0>;
  72                 #address-cells = <1>;
  73
  74                 cpu: cpu@0 {
  75                         device_type = "cpu";
  76                         compatible = "arm,arm926ej-s";
  77                         operating-points = <
  78                                 /* kHz uV */
  79                                 266000 1300000
  80                                 399000 1450000
  81                         >;
  82                         clock-latency = <62500>;
  83                         clocks = <&clks IMX27_CLK_CPU_DIV>;
  84                         voltage-tolerance = <5>;
  85                 };
  86         };
  87
  88         soc {
  89                 #address-cells = <1>;
  90                 #size-cells = <1>;
  91                 compatible = "simple-bus";
  92                 interrupt-parent = <&aitc>;
  93                 ranges;
  94
  95                 aipi@10000000 { /* AIPI1 */
  96                         compatible = "fsl,aipi-bus", "simple-bus";
  97                         #address-cells = <1>;
  98                         #size-cells = <1>;
  99                         reg = <0x10000000 0x20000>;
 100                         ranges;
 101
 102                         dma: dma@10001000 {
 103                                 compatible = "fsl,imx27-dma";
 104                                 reg = <0x10001000 0x1000>;
 105                                 interrupts = <32>;
 106                                 clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
 107                                          <&clks IMX27_CLK_DMA_AHB_GATE>;
 108                                 clock-names = "ipg", "ahb";
 109                                 #dma-cells = <1>;
 110                                 #dma-channels = <16>;
 111                         };
 112
 113                         wdog: wdog@10002000 {
 114                                 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
 115                                 reg = <0x10002000 0x1000>;
 116                                 interrupts = <27>;
 117                                 clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
 118                         };
 119
 120                         gpt1: timer@10003000 {
 121                                 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
 122                                 reg = <0x10003000 0x1000>;
 123                                 interrupts = <26>;
 124                                 clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
 125                                          <&clks IMX27_CLK_PER1_GATE>;
 126                                 clock-names = "ipg", "per";
 127                         };
 128
 129                         gpt2: timer@10004000 {
 130                                 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
 131                                 reg = <0x10004000 0x1000>;
 132                                 interrupts = <25>;
 133                                 clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
 134                                          <&clks IMX27_CLK_PER1_GATE>;
 135                                 clock-names = "ipg", "per";
 136                         };
 137
 138                         gpt3: timer@10005000 {
 139                                 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
 140                                 reg = <0x10005000 0x1000>;
 141                                 interrupts = <24>;
 142                                 clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
 143                                          <&clks IMX27_CLK_PER1_GATE>;
 144                                 clock-names = "ipg", "per";
 145                         };
 146
 147                         pwm: pwm@10006000 {
 148                                 #pwm-cells = <2>;
 149                                 compatible = "fsl,imx27-pwm";
 150                                 reg = <0x10006000 0x1000>;
 151                                 interrupts = <23>;
 152                                 clocks = <&clks IMX27_CLK_PWM_IPG_GATE>,
 153                                          <&clks IMX27_CLK_PER1_GATE>;
 154                                 clock-names = "ipg", "per";
 155                         };
 156
 157                         rtc: rtc@10007000 {
 158                                 compatible = "fsl,imx21-rtc";
 159                                 reg = <0x10007000 0x1000>;
 160                                 interrupts = <22>;
 161                                 clocks = <&clks IMX27_CLK_CKIL>,
 162                                          <&clks IMX27_CLK_RTC_IPG_GATE>;
 163                                 clock-names = "ref", "ipg";
 164                         };
 165
 166                         kpp: kpp@10008000 {
 167                                 compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
 168                                 reg = <0x10008000 0x1000>;
 169                                 interrupts = <21>;
 170                                 clocks = <&clks IMX27_CLK_KPP_IPG_GATE>;
 171                                 status = "disabled";
 172                         };
 173
 174                         owire: owire@10009000 {
 175                                 compatible = "fsl,imx27-owire", "fsl,imx21-owire";
 176                                 reg = <0x10009000 0x1000>;
 177                                 clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>;
 178                                 status = "disabled";
 179                         };
 180
 181                         uart1: serial@1000a000 {
 182                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 183                                 reg = <0x1000a000 0x1000>;
 184                                 interrupts = <20>;
 185                                 clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
 186                                          <&clks IMX27_CLK_PER1_GATE>;
 187                                 clock-names = "ipg", "per";
 188                                 status = "disabled";
 189                         };
 190
 191                         uart2: serial@1000b000 {
 192                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 193                                 reg = <0x1000b000 0x1000>;
 194                                 interrupts = <19>;
 195                                 clocks = <&clks IMX27_CLK_UART2_IPG_GATE>,
 196                                          <&clks IMX27_CLK_PER1_GATE>;
 197                                 clock-names = "ipg", "per";
 198                                 status = "disabled";
 199                         };
 200
 201                         uart3: serial@1000c000 {
 202                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 203                                 reg = <0x1000c000 0x1000>;
 204                                 interrupts = <18>;
 205                                 clocks = <&clks IMX27_CLK_UART3_IPG_GATE>,
 206                                          <&clks IMX27_CLK_PER1_GATE>;
 207                                 clock-names = "ipg", "per";
 208                                 status = "disabled";
 209                         };
 210
 211                         uart4: serial@1000d000 {
 212                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 213                                 reg = <0x1000d000 0x1000>;
 214                                 interrupts = <17>;
 215                                 clocks = <&clks IMX27_CLK_UART4_IPG_GATE>,
 216                                          <&clks IMX27_CLK_PER1_GATE>;
 217                                 clock-names = "ipg", "per";
 218                                 status = "disabled";
 219                         };
 220
 221                         cspi1: cspi@1000e000 {
 222                                 #address-cells = <1>;
 223                                 #size-cells = <0>;
 224                                 compatible = "fsl,imx27-cspi";
 225                                 reg = <0x1000e000 0x1000>;
 226                                 interrupts = <16>;
 227                                 clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>,
 228                                          <&clks IMX27_CLK_PER2_GATE>;
 229                                 clock-names = "ipg", "per";
 230                                 status = "disabled";
 231                         };
 232
 233                         cspi2: cspi@1000f000 {
 234                                 #address-cells = <1>;
 235                                 #size-cells = <0>;
 236                                 compatible = "fsl,imx27-cspi";
 237                                 reg = <0x1000f000 0x1000>;
 238                                 interrupts = <15>;
 239                                 clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>,
 240                                          <&clks IMX27_CLK_PER2_GATE>;
 241                                 clock-names = "ipg", "per";
 242                                 status = "disabled";
 243                         };
 244
 245                         ssi1: ssi@10010000 {
 246                                 #sound-dai-cells = <0>;
 247                                 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
 248                                 reg = <0x10010000 0x1000>;
 249                                 interrupts = <14>;
 250                                 clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>;
 251                                 dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
 252                                 dma-names = "rx0", "tx0", "rx1", "tx1";
 253                                 fsl,fifo-depth = <8>;
 254                                 status = "disabled";
 255                         };
 256
 257                         ssi2: ssi@10011000 {
 258                                 #sound-dai-cells = <0>;
 259                                 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
 260                                 reg = <0x10011000 0x1000>;
 261                                 interrupts = <13>;
 262                                 clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>;
 263                                 dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
 264                                 dma-names = "rx0", "tx0", "rx1", "tx1";
 265                                 fsl,fifo-depth = <8>;
 266                                 status = "disabled";
 267                         };
 268
 269                         i2c1: i2c@10012000 {
 270                                 #address-cells = <1>;
 271                                 #size-cells = <0>;
 272                                 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
 273                                 reg = <0x10012000 0x1000>;
 274                                 interrupts = <12>;
 275                                 clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>;
 276                                 status = "disabled";
 277                         };
 278
 279                         sdhci1: sdhci@10013000 {
 280                                 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
 281                                 reg = <0x10013000 0x1000>;
 282                                 interrupts = <11>;
 283                                 clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>,
 284                                          <&clks IMX27_CLK_PER2_GATE>;
 285                                 clock-names = "ipg", "per";
 286                                 dmas = <&dma 7>;
 287                                 dma-names = "rx-tx";
 288                                 status = "disabled";
 289                         };
 290
 291                         sdhci2: sdhci@10014000 {
 292                                 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
 293                                 reg = <0x10014000 0x1000>;
 294                                 interrupts = <10>;
 295                                 clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>,
 296                                          <&clks IMX27_CLK_PER2_GATE>;
 297                                 clock-names = "ipg", "per";
 298                                 dmas = <&dma 6>;
 299                                 dma-names = "rx-tx";
 300                                 status = "disabled";
 301                         };
 302
 303                         iomuxc: iomuxc@10015000 {
 304                                 compatible = "fsl,imx27-iomuxc";
 305                                 reg = <0x10015000 0x600>;
 306                                 #address-cells = <1>;
 307                                 #size-cells = <1>;
 308                                 ranges;
 309
 310                                 gpio1: gpio@10015000 {
 311                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 312                                         reg = <0x10015000 0x100>;
 313                                         clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
 314                                         interrupts = <8>;
 315                                         gpio-controller;
 316                                         #gpio-cells = <2>;
 317                                         interrupt-controller;
 318                                         #interrupt-cells = <2>;
 319                                 };
 320
 321                                 gpio2: gpio@10015100 {
 322                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 323                                         reg = <0x10015100 0x100>;
 324                                         clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
 325                                         interrupts = <8>;
 326                                         gpio-controller;
 327                                         #gpio-cells = <2>;
 328                                         interrupt-controller;
 329                                         #interrupt-cells = <2>;
 330                                 };
 331
 332                                 gpio3: gpio@10015200 {
 333                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 334                                         reg = <0x10015200 0x100>;
 335                                         clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
 336                                         interrupts = <8>;
 337                                         gpio-controller;
 338                                         #gpio-cells = <2>;
 339                                         interrupt-controller;
 340                                         #interrupt-cells = <2>;
 341                                 };
 342
 343                                 gpio4: gpio@10015300 {
 344                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 345                                         reg = <0x10015300 0x100>;
 346                                         clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
 347                                         interrupts = <8>;
 348                                         gpio-controller;
 349                                         #gpio-cells = <2>;
 350                                         interrupt-controller;
 351                                         #interrupt-cells = <2>;
 352                                 };
 353
 354                                 gpio5: gpio@10015400 {
 355                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 356                                         reg = <0x10015400 0x100>;
 357                                         clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
 358                                         interrupts = <8>;
 359                                         gpio-controller;
 360                                         #gpio-cells = <2>;
 361                                         interrupt-controller;
 362                                         #interrupt-cells = <2>;
 363                                 };
 364
 365                                 gpio6: gpio@10015500 {
 366                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 367                                         reg = <0x10015500 0x100>;
 368                                         clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
 369                                         interrupts = <8>;
 370                                         gpio-controller;
 371                                         #gpio-cells = <2>;
 372                                         interrupt-controller;
 373                                         #interrupt-cells = <2>;
 374                                 };
 375                         };
 376
 377                         audmux: audmux@10016000 {
 378                                 compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
 379                                 reg = <0x10016000 0x1000>;
 380                                 clocks = <&clks IMX27_CLK_DUMMY>;
 381                                 clock-names = "audmux";
 382                                 status = "disabled";
 383                         };
 384
 385                         cspi3: cspi@10017000 {
 386                                 #address-cells = <1>;
 387                                 #size-cells = <0>;
 388                                 compatible = "fsl,imx27-cspi";
 389                                 reg = <0x10017000 0x1000>;
 390                                 interrupts = <6>;
 391                                 clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>,
 392                                          <&clks IMX27_CLK_PER2_GATE>;
 393                                 clock-names = "ipg", "per";
 394                                 status = "disabled";
 395                         };
 396
 397                         gpt4: timer@10019000 {
 398                                 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
 399                                 reg = <0x10019000 0x1000>;
 400                                 interrupts = <4>;
 401                                 clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>,
 402                                          <&clks IMX27_CLK_PER1_GATE>;
 403                                 clock-names = "ipg", "per";
 404                         };
 405
 406                         gpt5: timer@1001a000 {
 407                                 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
 408                                 reg = <0x1001a000 0x1000>;
 409                                 interrupts = <3>;
 410                                 clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>,
 411                                          <&clks IMX27_CLK_PER1_GATE>;
 412                                 clock-names = "ipg", "per";
 413                         };
 414
 415                         uart5: serial@1001b000 {
 416                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 417                                 reg = <0x1001b000 0x1000>;
 418                                 interrupts = <49>;
 419                                 clocks = <&clks IMX27_CLK_UART5_IPG_GATE>,
 420                                          <&clks IMX27_CLK_PER1_GATE>;
 421                                 clock-names = "ipg", "per";
 422                                 status = "disabled";
 423                         };
 424
 425                         uart6: serial@1001c000 {
 426                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 427                                 reg = <0x1001c000 0x1000>;
 428                                 interrupts = <48>;
 429                                 clocks = <&clks IMX27_CLK_UART6_IPG_GATE>,
 430                                          <&clks IMX27_CLK_PER1_GATE>;
 431                                 clock-names = "ipg", "per";
 432                                 status = "disabled";
 433                         };
 434
 435                         i2c2: i2c@1001d000 {
 436                                 #address-cells = <1>;
 437                                 #size-cells = <0>;
 438                                 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
 439                                 reg = <0x1001d000 0x1000>;
 440                                 interrupts = <1>;
 441                                 clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>;
 442                                 status = "disabled";
 443                         };
 444
 445                         sdhci3: sdhci@1001e000 {
 446                                 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
 447                                 reg = <0x1001e000 0x1000>;
 448                                 interrupts = <9>;
 449                                 clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>,
 450                                          <&clks IMX27_CLK_PER2_GATE>;
 451                                 clock-names = "ipg", "per";
 452                                 dmas = <&dma 36>;
 453                                 dma-names = "rx-tx";
 454                                 status = "disabled";
 455                         };
 456
 457                         gpt6: timer@1001f000 {
 458                                 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
 459                                 reg = <0x1001f000 0x1000>;
 460                                 interrupts = <2>;
 461                                 clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>,
 462                                          <&clks IMX27_CLK_PER1_GATE>;
 463                                 clock-names = "ipg", "per";
 464                         };
 465                 };
 466
 467                 aipi@10020000 { /* AIPI2 */
 468                         compatible = "fsl,aipi-bus", "simple-bus";
 469                         #address-cells = <1>;
 470                         #size-cells = <1>;
 471                         reg = <0x10020000 0x20000>;
 472                         ranges;
 473
 474                         fb: fb@10021000 {
 475                                 compatible = "fsl,imx27-fb", "fsl,imx21-fb";
 476                                 interrupts = <61>;
 477                                 reg = <0x10021000 0x1000>;
 478                                 clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>,
 479                                          <&clks IMX27_CLK_LCDC_AHB_GATE>,
 480                                          <&clks IMX27_CLK_PER3_GATE>;
 481                                 clock-names = "ipg", "ahb", "per";
 482                                 status = "disabled";
 483                         };
 484
 485                         coda: coda@10023000 {
 486                                 compatible = "fsl,imx27-vpu", "cnm,codadx6";
 487                                 reg = <0x10023000 0x0200>;
 488                                 interrupts = <53>;
 489                                 clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
 490                                          <&clks IMX27_CLK_VPU_AHB_GATE>;
 491                                 clock-names = "per", "ahb";
 492                                 iram = <&iram>;
 493                         };
 494
 495                         usbotg: usb@10024000 {
 496                                 compatible = "fsl,imx27-usb";
 497                                 reg = <0x10024000 0x200>;
 498                                 interrupts = <56>;
 499                                 clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
 500                                         <&clks IMX27_CLK_USB_AHB_GATE>,
 501                                         <&clks IMX27_CLK_USB_DIV>;
 502                                 clock-names = "ipg", "ahb", "per";
 503                                 fsl,usbmisc = <&usbmisc 0>;
 504                                 status = "disabled";
 505                         };
 506
 507                         usbh1: usb@10024200 {
 508                                 compatible = "fsl,imx27-usb";
 509                                 reg = <0x10024200 0x200>;
 510                                 interrupts = <54>;
 511                                 clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
 512                                         <&clks IMX27_CLK_USB_AHB_GATE>,
 513                                         <&clks IMX27_CLK_USB_DIV>;
 514                                 clock-names = "ipg", "ahb", "per";
 515                                 fsl,usbmisc = <&usbmisc 1>;
 516                                 dr_mode = "host";
 517                                 status = "disabled";
 518                         };
 519
 520                         usbh2: usb@10024400 {
 521                                 compatible = "fsl,imx27-usb";
 522                                 reg = <0x10024400 0x200>;
 523                                 interrupts = <55>;
 524                                 clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
 525                                         <&clks IMX27_CLK_USB_AHB_GATE>,
 526                                         <&clks IMX27_CLK_USB_DIV>;
 527                                 clock-names = "ipg", "ahb", "per";
 528                                 fsl,usbmisc = <&usbmisc 2>;
 529                                 dr_mode = "host";
 530                                 status = "disabled";
 531                         };
 532
 533                         usbmisc: usbmisc@10024600 {
 534                                 #index-cells = <1>;
 535                                 compatible = "fsl,imx27-usbmisc";
 536                                 reg = <0x10024600 0x200>;
 537                         };
 538
 539                         sahara2: sahara@10025000 {
 540                                 compatible = "fsl,imx27-sahara";
 541                                 reg = <0x10025000 0x1000>;
 542                                 interrupts = <59>;
 543                                 clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>,
 544                                          <&clks IMX27_CLK_SAHARA_AHB_GATE>;
 545                                 clock-names = "ipg", "ahb";
 546                         };
 547
 548                         clks: ccm@10027000{
 549                                 compatible = "fsl,imx27-ccm";
 550                                 reg = <0x10027000 0x1000>;
 551                                 #clock-cells = <1>;
 552                         };
 553
 554                         iim: iim@10028000 {
 555                                 compatible = "fsl,imx27-iim";
 556                                 reg = <0x10028000 0x1000>;
 557                                 interrupts = <62>;
 558                                 clocks = <&clks IMX27_CLK_IIM_IPG_GATE>;
 559                         };
 560
 561                         fec: ethernet@1002b000 {
 562                                 compatible = "fsl,imx27-fec";
 563                                 reg = <0x1002b000 0x1000>;
 564                                 interrupts = <50>;
 565                                 clocks = <&clks IMX27_CLK_FEC_IPG_GATE>,
 566                                          <&clks IMX27_CLK_FEC_AHB_GATE>;
 567                                 clock-names = "ipg", "ahb";
 568                                 status = "disabled";
 569                         };
 570                 };
 571
 572                 nfc: nand@d8000000 {
 573                         #address-cells = <1>;
 574                         #size-cells = <1>;
 575                         compatible = "fsl,imx27-nand";
 576                         reg = <0xd8000000 0x1000>;
 577                         interrupts = <29>;
 578                         clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>;
 579                         status = "disabled";
 580                 };
 581
 582                 weim: weim@d8002000 {
 583                         #address-cells = <2>;
 584                         #size-cells = <1>;
 585                         compatible = "fsl,imx27-weim";
 586                         reg = <0xd8002000 0x1000>;
 587                         clocks = <&clks IMX27_CLK_EMI_AHB_GATE>;
 588                         ranges = <
 589                                 0 0 0xc0000000 0x08000000
 590                                 1 0 0xc8000000 0x08000000
 591                                 2 0 0xd0000000 0x02000000
 592                                 3 0 0xd2000000 0x02000000
 593                                 4 0 0xd4000000 0x02000000
 594                                 5 0 0xd6000000 0x02000000
 595                         >;
 596                         status = "disabled";
 597                 };
 598
 599                 iram: iram@ffff4c00 {
 600                         compatible = "mmio-sram";
 601                         reg = <0xffff4c00 0xb400>;
 602                 };
 603         };
 604 };