1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright 2011 Freescale Semiconductor, Inc.
4 // Copyright 2011 Linaro Ltd.
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 * The decompressor and also some bootloaders rely on a
15 * pre-existing /chosen node to be available to insert the
16 * command line and merge other ATAGS info.
54 compatible = "fsl,imx-ckil", "fixed-clock";
56 clock-frequency = <32768>;
60 compatible = "fsl,imx-ckih1", "fixed-clock";
62 clock-frequency = <0>;
66 compatible = "fsl,imx-osc", "fixed-clock";
68 clock-frequency = <24000000>;
73 compatible = "fsl,imx6q-tempmon";
74 interrupt-parent = <&gpc>;
75 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
76 fsl,tempmon = <&anatop>;
77 fsl,tempmon-data = <&ocotp>;
78 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
79 #thermal-sensor-cells = <0>;
85 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
98 lvds0_mux_0: endpoint {
99 remote-endpoint = <&ipu1_di0_lvds0>;
106 lvds0_mux_1: endpoint {
107 remote-endpoint = <&ipu1_di1_lvds0>;
113 #address-cells = <1>;
121 lvds1_mux_0: endpoint {
122 remote-endpoint = <&ipu1_di0_lvds1>;
129 lvds1_mux_1: endpoint {
130 remote-endpoint = <&ipu1_di1_lvds1>;
137 compatible = "arm,cortex-a9-pmu";
138 interrupt-parent = <&gpc>;
139 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
142 usbphynop1: usbphynop1 {
143 compatible = "usb-nop-xceiv";
147 usbphynop2: usbphynop2 {
148 compatible = "usb-nop-xceiv";
153 #address-cells = <1>;
155 compatible = "simple-bus";
156 interrupt-parent = <&gpc>;
159 dma_apbh: dma-apbh@110000 {
160 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
161 reg = <0x00110000 0x2000>;
162 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
163 <0 13 IRQ_TYPE_LEVEL_HIGH>,
164 <0 13 IRQ_TYPE_LEVEL_HIGH>,
165 <0 13 IRQ_TYPE_LEVEL_HIGH>;
166 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
169 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
172 gpmi: gpmi-nand@112000 {
173 compatible = "fsl,imx6q-gpmi-nand";
174 #address-cells = <1>;
176 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
177 reg-names = "gpmi-nand", "bch";
178 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
179 interrupt-names = "bch";
180 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
181 <&clks IMX6QDL_CLK_GPMI_APB>,
182 <&clks IMX6QDL_CLK_GPMI_BCH>,
183 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
184 <&clks IMX6QDL_CLK_PER1_BCH>;
185 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
186 "gpmi_bch_apb", "per1_bch";
187 dmas = <&dma_apbh 0>;
193 #address-cells = <1>;
195 reg = <0x00120000 0x9000>;
196 interrupts = <0 115 0x04>;
198 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
199 <&clks IMX6QDL_CLK_HDMI_ISFR>;
200 clock-names = "iahb", "isfr";
206 hdmi_mux_0: endpoint {
207 remote-endpoint = <&ipu1_di0_hdmi>;
214 hdmi_mux_1: endpoint {
215 remote-endpoint = <&ipu1_di1_hdmi>;
221 compatible = "vivante,gc";
222 reg = <0x00130000 0x4000>;
223 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
225 <&clks IMX6QDL_CLK_GPU3D_CORE>,
226 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
227 clock-names = "bus", "core", "shader";
228 power-domains = <&pd_pu>;
229 #cooling-cells = <2>;
233 compatible = "vivante,gc";
234 reg = <0x00134000 0x4000>;
235 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
237 <&clks IMX6QDL_CLK_GPU2D_CORE>;
238 clock-names = "bus", "core";
239 power-domains = <&pd_pu>;
240 #cooling-cells = <2>;
244 compatible = "arm,cortex-a9-twd-timer";
245 reg = <0x00a00600 0x20>;
246 interrupts = <1 13 0xf01>;
247 interrupt-parent = <&intc>;
248 clocks = <&clks IMX6QDL_CLK_TWD>;
251 intc: interrupt-controller@a01000 {
252 compatible = "arm,cortex-a9-gic";
253 #interrupt-cells = <3>;
254 interrupt-controller;
255 reg = <0x00a01000 0x1000>,
257 interrupt-parent = <&intc>;
260 L2: l2-cache@a02000 {
261 compatible = "arm,pl310-cache";
262 reg = <0x00a02000 0x1000>;
263 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
266 arm,tag-latency = <4 2 3>;
267 arm,data-latency = <4 2 3>;
272 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
273 reg = <0x01ffc000 0x04000>,
274 <0x01f00000 0x80000>;
275 reg-names = "dbi", "config";
276 #address-cells = <3>;
279 bus-range = <0x00 0xff>;
280 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
281 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
284 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
285 interrupt-names = "msi";
286 #interrupt-cells = <1>;
287 interrupt-map-mask = <0 0 0 0x7>;
288 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
289 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
290 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
291 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
293 <&clks IMX6QDL_CLK_LVDS1_GATE>,
294 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
295 clock-names = "pcie", "pcie_bus", "pcie_phy";
299 aips-bus@2000000 { /* AIPS1 */
300 compatible = "fsl,aips-bus", "simple-bus";
301 #address-cells = <1>;
303 reg = <0x02000000 0x100000>;
307 compatible = "fsl,spba-bus", "simple-bus";
308 #address-cells = <1>;
310 reg = <0x02000000 0x40000>;
313 spdif: spdif@2004000 {
314 compatible = "fsl,imx35-spdif";
315 reg = <0x02004000 0x4000>;
316 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
317 dmas = <&sdma 14 18 0>,
319 dma-names = "rx", "tx";
320 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
321 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
322 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
323 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
324 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
325 clock-names = "core", "rxtx0",
333 ecspi1: spi@2008000 {
334 #address-cells = <1>;
336 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
337 reg = <0x02008000 0x4000>;
338 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
340 <&clks IMX6QDL_CLK_ECSPI1>;
341 clock-names = "ipg", "per";
342 dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
343 dma-names = "rx", "tx";
347 ecspi2: spi@200c000 {
348 #address-cells = <1>;
350 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
351 reg = <0x0200c000 0x4000>;
352 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
354 <&clks IMX6QDL_CLK_ECSPI2>;
355 clock-names = "ipg", "per";
356 dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
357 dma-names = "rx", "tx";
361 ecspi3: spi@2010000 {
362 #address-cells = <1>;
364 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
365 reg = <0x02010000 0x4000>;
366 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
368 <&clks IMX6QDL_CLK_ECSPI3>;
369 clock-names = "ipg", "per";
370 dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
371 dma-names = "rx", "tx";
375 ecspi4: spi@2014000 {
376 #address-cells = <1>;
378 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
379 reg = <0x02014000 0x4000>;
380 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
382 <&clks IMX6QDL_CLK_ECSPI4>;
383 clock-names = "ipg", "per";
384 dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
385 dma-names = "rx", "tx";
389 uart1: serial@2020000 {
390 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
391 reg = <0x02020000 0x4000>;
392 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
394 <&clks IMX6QDL_CLK_UART_SERIAL>;
395 clock-names = "ipg", "per";
396 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
397 dma-names = "rx", "tx";
402 #sound-dai-cells = <0>;
403 compatible = "fsl,imx35-esai";
404 reg = <0x02024000 0x4000>;
405 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
407 <&clks IMX6QDL_CLK_ESAI_MEM>,
408 <&clks IMX6QDL_CLK_ESAI_EXTAL>,
409 <&clks IMX6QDL_CLK_ESAI_IPG>,
410 <&clks IMX6QDL_CLK_SPBA>;
411 clock-names = "core", "mem", "extal", "fsys", "spba";
412 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
413 dma-names = "rx", "tx";
418 #sound-dai-cells = <0>;
419 compatible = "fsl,imx6q-ssi",
421 reg = <0x02028000 0x4000>;
422 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
423 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
424 <&clks IMX6QDL_CLK_SSI1>;
425 clock-names = "ipg", "baud";
426 dmas = <&sdma 37 1 0>,
428 dma-names = "rx", "tx";
429 fsl,fifo-depth = <15>;
434 #sound-dai-cells = <0>;
435 compatible = "fsl,imx6q-ssi",
437 reg = <0x0202c000 0x4000>;
438 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
440 <&clks IMX6QDL_CLK_SSI2>;
441 clock-names = "ipg", "baud";
442 dmas = <&sdma 41 1 0>,
444 dma-names = "rx", "tx";
445 fsl,fifo-depth = <15>;
450 #sound-dai-cells = <0>;
451 compatible = "fsl,imx6q-ssi",
453 reg = <0x02030000 0x4000>;
454 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
456 <&clks IMX6QDL_CLK_SSI3>;
457 clock-names = "ipg", "baud";
458 dmas = <&sdma 45 1 0>,
460 dma-names = "rx", "tx";
461 fsl,fifo-depth = <15>;
466 compatible = "fsl,imx53-asrc";
467 reg = <0x02034000 0x4000>;
468 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
470 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
471 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
472 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
473 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
474 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
475 <&clks IMX6QDL_CLK_SPBA>;
476 clock-names = "mem", "ipg", "asrck_0",
477 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
478 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
479 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
480 "asrck_d", "asrck_e", "asrck_f", "spba";
481 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
482 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
483 dma-names = "rxa", "rxb", "rxc",
485 fsl,asrc-rate = <48000>;
486 fsl,asrc-width = <16>;
491 reg = <0x0203c000 0x4000>;
496 compatible = "cnm,coda960";
497 reg = <0x02040000 0x3c000>;
498 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
499 <0 3 IRQ_TYPE_LEVEL_HIGH>;
500 interrupt-names = "bit", "jpeg";
501 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
502 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
503 clock-names = "per", "ahb";
504 power-domains = <&pd_pu>;
509 aipstz@207c000 { /* AIPSTZ1 */
510 reg = <0x0207c000 0x4000>;
515 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
516 reg = <0x02080000 0x4000>;
517 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&clks IMX6QDL_CLK_IPG>,
519 <&clks IMX6QDL_CLK_PWM1>;
520 clock-names = "ipg", "per";
526 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
527 reg = <0x02084000 0x4000>;
528 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&clks IMX6QDL_CLK_IPG>,
530 <&clks IMX6QDL_CLK_PWM2>;
531 clock-names = "ipg", "per";
537 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
538 reg = <0x02088000 0x4000>;
539 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&clks IMX6QDL_CLK_IPG>,
541 <&clks IMX6QDL_CLK_PWM3>;
542 clock-names = "ipg", "per";
548 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
549 reg = <0x0208c000 0x4000>;
550 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&clks IMX6QDL_CLK_IPG>,
552 <&clks IMX6QDL_CLK_PWM4>;
553 clock-names = "ipg", "per";
557 can1: flexcan@2090000 {
558 compatible = "fsl,imx6q-flexcan";
559 reg = <0x02090000 0x4000>;
560 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
562 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
563 clock-names = "ipg", "per";
564 fsl,stop-mode = <&gpr 0x34 28 0x10 17>;
568 can2: flexcan@2094000 {
569 compatible = "fsl,imx6q-flexcan";
570 reg = <0x02094000 0x4000>;
571 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
573 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
574 clock-names = "ipg", "per";
575 fsl,stop-mode = <&gpr 0x34 29 0x10 18>;
580 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
581 reg = <0x02098000 0x4000>;
582 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
584 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
585 <&clks IMX6QDL_CLK_GPT_3M>;
586 clock-names = "ipg", "per", "osc_per";
589 gpio1: gpio@209c000 {
590 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
591 reg = <0x0209c000 0x4000>;
592 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
593 <0 67 IRQ_TYPE_LEVEL_HIGH>;
596 interrupt-controller;
597 #interrupt-cells = <2>;
600 gpio2: gpio@20a0000 {
601 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
602 reg = <0x020a0000 0x4000>;
603 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
604 <0 69 IRQ_TYPE_LEVEL_HIGH>;
607 interrupt-controller;
608 #interrupt-cells = <2>;
611 gpio3: gpio@20a4000 {
612 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
613 reg = <0x020a4000 0x4000>;
614 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
615 <0 71 IRQ_TYPE_LEVEL_HIGH>;
618 interrupt-controller;
619 #interrupt-cells = <2>;
622 gpio4: gpio@20a8000 {
623 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
624 reg = <0x020a8000 0x4000>;
625 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
626 <0 73 IRQ_TYPE_LEVEL_HIGH>;
629 interrupt-controller;
630 #interrupt-cells = <2>;
633 gpio5: gpio@20ac000 {
634 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
635 reg = <0x020ac000 0x4000>;
636 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
637 <0 75 IRQ_TYPE_LEVEL_HIGH>;
640 interrupt-controller;
641 #interrupt-cells = <2>;
644 gpio6: gpio@20b0000 {
645 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
646 reg = <0x020b0000 0x4000>;
647 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
648 <0 77 IRQ_TYPE_LEVEL_HIGH>;
651 interrupt-controller;
652 #interrupt-cells = <2>;
655 gpio7: gpio@20b4000 {
656 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
657 reg = <0x020b4000 0x4000>;
658 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
659 <0 79 IRQ_TYPE_LEVEL_HIGH>;
662 interrupt-controller;
663 #interrupt-cells = <2>;
667 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
668 reg = <0x020b8000 0x4000>;
669 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&clks IMX6QDL_CLK_IPG>;
674 wdog1: wdog@20bc000 {
675 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
676 reg = <0x020bc000 0x4000>;
677 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
678 clocks = <&clks IMX6QDL_CLK_DUMMY>;
681 wdog2: wdog@20c0000 {
682 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
683 reg = <0x020c0000 0x4000>;
684 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&clks IMX6QDL_CLK_DUMMY>;
690 compatible = "fsl,imx6q-ccm";
691 reg = <0x020c4000 0x4000>;
692 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
693 <0 88 IRQ_TYPE_LEVEL_HIGH>;
697 anatop: anatop@20c8000 {
698 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
699 reg = <0x020c8000 0x1000>;
700 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
701 <0 54 IRQ_TYPE_LEVEL_HIGH>,
702 <0 127 IRQ_TYPE_LEVEL_HIGH>;
705 compatible = "fsl,anatop-regulator";
706 regulator-name = "vdd1p1";
707 regulator-min-microvolt = <1000000>;
708 regulator-max-microvolt = <1200000>;
710 anatop-reg-offset = <0x110>;
711 anatop-vol-bit-shift = <8>;
712 anatop-vol-bit-width = <5>;
713 anatop-min-bit-val = <4>;
714 anatop-min-voltage = <800000>;
715 anatop-max-voltage = <1375000>;
716 anatop-enable-bit = <0>;
720 compatible = "fsl,anatop-regulator";
721 regulator-name = "vdd3p0";
722 regulator-min-microvolt = <2800000>;
723 regulator-max-microvolt = <3150000>;
725 anatop-reg-offset = <0x120>;
726 anatop-vol-bit-shift = <8>;
727 anatop-vol-bit-width = <5>;
728 anatop-min-bit-val = <0>;
729 anatop-min-voltage = <2625000>;
730 anatop-max-voltage = <3400000>;
731 anatop-enable-bit = <0>;
735 compatible = "fsl,anatop-regulator";
736 regulator-name = "vdd2p5";
737 regulator-min-microvolt = <2250000>;
738 regulator-max-microvolt = <2750000>;
740 anatop-reg-offset = <0x130>;
741 anatop-vol-bit-shift = <8>;
742 anatop-vol-bit-width = <5>;
743 anatop-min-bit-val = <0>;
744 anatop-min-voltage = <2100000>;
745 anatop-max-voltage = <2875000>;
746 anatop-enable-bit = <0>;
749 reg_arm: regulator-vddcore {
750 compatible = "fsl,anatop-regulator";
751 regulator-name = "vddarm";
752 regulator-min-microvolt = <725000>;
753 regulator-max-microvolt = <1450000>;
755 anatop-reg-offset = <0x140>;
756 anatop-vol-bit-shift = <0>;
757 anatop-vol-bit-width = <5>;
758 anatop-delay-reg-offset = <0x170>;
759 anatop-delay-bit-shift = <24>;
760 anatop-delay-bit-width = <2>;
761 anatop-min-bit-val = <1>;
762 anatop-min-voltage = <725000>;
763 anatop-max-voltage = <1450000>;
766 reg_pu: regulator-vddpu {
767 compatible = "fsl,anatop-regulator";
768 regulator-name = "vddpu";
769 regulator-min-microvolt = <725000>;
770 regulator-max-microvolt = <1450000>;
771 regulator-enable-ramp-delay = <150>;
772 anatop-reg-offset = <0x140>;
773 anatop-vol-bit-shift = <9>;
774 anatop-vol-bit-width = <5>;
775 anatop-delay-reg-offset = <0x170>;
776 anatop-delay-bit-shift = <26>;
777 anatop-delay-bit-width = <2>;
778 anatop-min-bit-val = <1>;
779 anatop-min-voltage = <725000>;
780 anatop-max-voltage = <1450000>;
783 reg_soc: regulator-vddsoc {
784 compatible = "fsl,anatop-regulator";
785 regulator-name = "vddsoc";
786 regulator-min-microvolt = <725000>;
787 regulator-max-microvolt = <1450000>;
789 anatop-reg-offset = <0x140>;
790 anatop-vol-bit-shift = <18>;
791 anatop-vol-bit-width = <5>;
792 anatop-delay-reg-offset = <0x170>;
793 anatop-delay-bit-shift = <28>;
794 anatop-delay-bit-width = <2>;
795 anatop-min-bit-val = <1>;
796 anatop-min-voltage = <725000>;
797 anatop-max-voltage = <1450000>;
801 usbphy1: usbphy@20c9000 {
802 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
803 reg = <0x020c9000 0x1000>;
804 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
806 fsl,anatop = <&anatop>;
809 usbphy2: usbphy@20ca000 {
810 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
811 reg = <0x020ca000 0x1000>;
812 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
813 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
814 fsl,anatop = <&anatop>;
818 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
819 reg = <0x020cc000 0x4000>;
821 snvs_rtc: snvs-rtc-lp {
822 compatible = "fsl,sec-v4.0-mon-rtc-lp";
825 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
826 <0 20 IRQ_TYPE_LEVEL_HIGH>;
829 snvs_poweroff: snvs-poweroff {
830 compatible = "syscon-poweroff";
838 snvs_pwrkey: snvs-powerkey {
839 compatible = "fsl,sec-v4.0-pwrkey";
841 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
842 linux,keycode = <KEY_POWER>;
846 snvs_lpgpr: snvs-lpgpr {
847 compatible = "fsl,imx6q-snvs-lpgpr";
851 epit1: epit@20d0000 { /* EPIT1 */
852 reg = <0x020d0000 0x4000>;
853 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
856 epit2: epit@20d4000 { /* EPIT2 */
857 reg = <0x020d4000 0x4000>;
858 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
862 compatible = "fsl,imx6q-src", "fsl,imx51-src";
863 reg = <0x020d8000 0x4000>;
864 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
865 <0 96 IRQ_TYPE_LEVEL_HIGH>;
870 compatible = "fsl,imx6q-gpc";
871 reg = <0x020dc000 0x4000>;
872 interrupt-controller;
873 #interrupt-cells = <3>;
874 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
875 <0 90 IRQ_TYPE_LEVEL_HIGH>;
876 interrupt-parent = <&intc>;
877 clocks = <&clks IMX6QDL_CLK_IPG>;
881 #address-cells = <1>;
886 #power-domain-cells = <0>;
888 pd_pu: power-domain@1 {
890 #power-domain-cells = <0>;
891 power-supply = <®_pu>;
892 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
893 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
894 <&clks IMX6QDL_CLK_GPU2D_CORE>,
895 <&clks IMX6QDL_CLK_GPU2D_AXI>,
896 <&clks IMX6QDL_CLK_OPENVG_AXI>,
897 <&clks IMX6QDL_CLK_VPU_AXI>;
902 gpr: iomuxc-gpr@20e0000 {
903 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
904 reg = <0x20e0000 0x38>;
906 mux: mux-controller {
907 compatible = "mmio-mux";
908 #mux-control-cells = <1>;
912 iomuxc: iomuxc@20e0000 {
913 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
914 reg = <0x20e0000 0x4000>;
917 dcic1: dcic@20e4000 {
918 reg = <0x020e4000 0x4000>;
919 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
922 dcic2: dcic@20e8000 {
923 reg = <0x020e8000 0x4000>;
924 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
928 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
929 reg = <0x020ec000 0x4000>;
930 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&clks IMX6QDL_CLK_IPG>,
932 <&clks IMX6QDL_CLK_SDMA>;
933 clock-names = "ipg", "ahb";
935 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
939 aips-bus@2100000 { /* AIPS2 */
940 compatible = "fsl,aips-bus", "simple-bus";
941 #address-cells = <1>;
943 reg = <0x02100000 0x100000>;
946 crypto: caam@2100000 {
947 compatible = "fsl,sec-v4.0";
948 #address-cells = <1>;
950 reg = <0x2100000 0x10000>;
951 ranges = <0 0x2100000 0x10000>;
952 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
953 <&clks IMX6QDL_CLK_CAAM_ACLK>,
954 <&clks IMX6QDL_CLK_CAAM_IPG>,
955 <&clks IMX6QDL_CLK_EIM_SLOW>;
956 clock-names = "mem", "aclk", "ipg", "emi_slow";
959 compatible = "fsl,sec-v4.0-job-ring";
960 reg = <0x1000 0x1000>;
961 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
965 compatible = "fsl,sec-v4.0-job-ring";
966 reg = <0x2000 0x1000>;
967 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
971 aipstz@217c000 { /* AIPSTZ2 */
972 reg = <0x0217c000 0x4000>;
975 usbotg: usb@2184000 {
976 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
977 reg = <0x02184000 0x200>;
978 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
979 clocks = <&clks IMX6QDL_CLK_USBOH3>;
980 fsl,usbphy = <&usbphy1>;
981 fsl,usbmisc = <&usbmisc 0>;
982 ahb-burst-config = <0x0>;
983 tx-burst-size-dword = <0x10>;
984 rx-burst-size-dword = <0x10>;
989 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
990 reg = <0x02184200 0x200>;
991 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&clks IMX6QDL_CLK_USBOH3>;
993 fsl,usbphy = <&usbphy2>;
994 fsl,usbmisc = <&usbmisc 1>;
996 ahb-burst-config = <0x0>;
997 tx-burst-size-dword = <0x10>;
998 rx-burst-size-dword = <0x10>;
1002 usbh2: usb@2184400 {
1003 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1004 reg = <0x02184400 0x200>;
1005 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
1006 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1007 fsl,usbphy = <&usbphynop1>;
1009 fsl,usbmisc = <&usbmisc 2>;
1011 ahb-burst-config = <0x0>;
1012 tx-burst-size-dword = <0x10>;
1013 rx-burst-size-dword = <0x10>;
1014 status = "disabled";
1017 usbh3: usb@2184600 {
1018 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1019 reg = <0x02184600 0x200>;
1020 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
1021 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1022 fsl,usbphy = <&usbphynop2>;
1024 fsl,usbmisc = <&usbmisc 3>;
1026 ahb-burst-config = <0x0>;
1027 tx-burst-size-dword = <0x10>;
1028 rx-burst-size-dword = <0x10>;
1029 status = "disabled";
1032 usbmisc: usbmisc@2184800 {
1034 compatible = "fsl,imx6q-usbmisc";
1035 reg = <0x02184800 0x200>;
1036 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1039 fec: ethernet@2188000 {
1040 compatible = "fsl,imx6q-fec";
1041 reg = <0x02188000 0x4000>;
1042 interrupt-names = "int0", "pps";
1043 interrupts-extended =
1044 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
1045 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
1046 clocks = <&clks IMX6QDL_CLK_ENET>,
1047 <&clks IMX6QDL_CLK_ENET>,
1048 <&clks IMX6QDL_CLK_ENET_REF>;
1049 clock-names = "ipg", "ahb", "ptp";
1050 status = "disabled";
1054 reg = <0x0218c000 0x4000>;
1055 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1056 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1057 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1060 usdhc1: usdhc@2190000 {
1061 compatible = "fsl,imx6q-usdhc";
1062 reg = <0x02190000 0x4000>;
1063 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1064 clocks = <&clks IMX6QDL_CLK_USDHC1>,
1065 <&clks IMX6QDL_CLK_USDHC1>,
1066 <&clks IMX6QDL_CLK_USDHC1>;
1067 clock-names = "ipg", "ahb", "per";
1069 status = "disabled";
1072 usdhc2: usdhc@2194000 {
1073 compatible = "fsl,imx6q-usdhc";
1074 reg = <0x02194000 0x4000>;
1075 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&clks IMX6QDL_CLK_USDHC2>,
1077 <&clks IMX6QDL_CLK_USDHC2>,
1078 <&clks IMX6QDL_CLK_USDHC2>;
1079 clock-names = "ipg", "ahb", "per";
1081 status = "disabled";
1084 usdhc3: usdhc@2198000 {
1085 compatible = "fsl,imx6q-usdhc";
1086 reg = <0x02198000 0x4000>;
1087 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1088 clocks = <&clks IMX6QDL_CLK_USDHC3>,
1089 <&clks IMX6QDL_CLK_USDHC3>,
1090 <&clks IMX6QDL_CLK_USDHC3>;
1091 clock-names = "ipg", "ahb", "per";
1093 status = "disabled";
1096 usdhc4: usdhc@219c000 {
1097 compatible = "fsl,imx6q-usdhc";
1098 reg = <0x0219c000 0x4000>;
1099 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1100 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1101 <&clks IMX6QDL_CLK_USDHC4>,
1102 <&clks IMX6QDL_CLK_USDHC4>;
1103 clock-names = "ipg", "ahb", "per";
1105 status = "disabled";
1109 #address-cells = <1>;
1111 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1112 reg = <0x021a0000 0x4000>;
1113 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1114 clocks = <&clks IMX6QDL_CLK_I2C1>;
1115 status = "disabled";
1119 #address-cells = <1>;
1121 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1122 reg = <0x021a4000 0x4000>;
1123 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1124 clocks = <&clks IMX6QDL_CLK_I2C2>;
1125 status = "disabled";
1129 #address-cells = <1>;
1131 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1132 reg = <0x021a8000 0x4000>;
1133 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1134 clocks = <&clks IMX6QDL_CLK_I2C3>;
1135 status = "disabled";
1139 reg = <0x021ac000 0x4000>;
1142 mmdc0: memory-controller@21b0000 { /* MMDC0 */
1143 compatible = "fsl,imx6q-mmdc";
1144 reg = <0x021b0000 0x4000>;
1145 clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
1148 mmdc1: memory-controller@21b4000 { /* MMDC1 */
1149 compatible = "fsl,imx6q-mmdc";
1150 reg = <0x021b4000 0x4000>;
1151 status = "disabled";
1154 weim: weim@21b8000 {
1155 #address-cells = <2>;
1157 compatible = "fsl,imx6q-weim";
1158 reg = <0x021b8000 0x4000>;
1159 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1160 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1161 fsl,weim-cs-gpr = <&gpr>;
1162 status = "disabled";
1165 ocotp: ocotp@21bc000 {
1166 compatible = "fsl,imx6q-ocotp", "syscon";
1167 reg = <0x021bc000 0x4000>;
1168 clocks = <&clks IMX6QDL_CLK_IIM>;
1171 tzasc@21d0000 { /* TZASC1 */
1172 reg = <0x021d0000 0x4000>;
1173 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1176 tzasc@21d4000 { /* TZASC2 */
1177 reg = <0x021d4000 0x4000>;
1178 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1181 audmux: audmux@21d8000 {
1182 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1183 reg = <0x021d8000 0x4000>;
1184 status = "disabled";
1187 mipi_csi: mipi@21dc000 {
1188 compatible = "fsl,imx6-mipi-csi2";
1189 reg = <0x021dc000 0x4000>;
1190 #address-cells = <1>;
1192 interrupts = <0 100 0x04>, <0 101 0x04>;
1193 clocks = <&clks IMX6QDL_CLK_HSI_TX>,
1194 <&clks IMX6QDL_CLK_VIDEO_27M>,
1195 <&clks IMX6QDL_CLK_EIM_PODF>;
1196 clock-names = "dphy", "ref", "pix";
1197 status = "disabled";
1200 mipi_dsi: mipi@21e0000 {
1201 reg = <0x021e0000 0x4000>;
1202 status = "disabled";
1205 #address-cells = <1>;
1211 mipi_mux_0: endpoint {
1212 remote-endpoint = <&ipu1_di0_mipi>;
1219 mipi_mux_1: endpoint {
1220 remote-endpoint = <&ipu1_di1_mipi>;
1227 compatible = "fsl,imx6q-vdoa";
1228 reg = <0x021e4000 0x4000>;
1229 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1230 clocks = <&clks IMX6QDL_CLK_VDOA>;
1233 uart2: serial@21e8000 {
1234 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1235 reg = <0x021e8000 0x4000>;
1236 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1237 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1238 <&clks IMX6QDL_CLK_UART_SERIAL>;
1239 clock-names = "ipg", "per";
1240 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1241 dma-names = "rx", "tx";
1242 status = "disabled";
1245 uart3: serial@21ec000 {
1246 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1247 reg = <0x021ec000 0x4000>;
1248 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1249 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1250 <&clks IMX6QDL_CLK_UART_SERIAL>;
1251 clock-names = "ipg", "per";
1252 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1253 dma-names = "rx", "tx";
1254 status = "disabled";
1257 uart4: serial@21f0000 {
1258 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1259 reg = <0x021f0000 0x4000>;
1260 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1261 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1262 <&clks IMX6QDL_CLK_UART_SERIAL>;
1263 clock-names = "ipg", "per";
1264 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1265 dma-names = "rx", "tx";
1266 status = "disabled";
1269 uart5: serial@21f4000 {
1270 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1271 reg = <0x021f4000 0x4000>;
1272 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1273 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1274 <&clks IMX6QDL_CLK_UART_SERIAL>;
1275 clock-names = "ipg", "per";
1276 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1277 dma-names = "rx", "tx";
1278 status = "disabled";
1283 #address-cells = <1>;
1285 compatible = "fsl,imx6q-ipu";
1286 reg = <0x02400000 0x400000>;
1287 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1288 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1289 clocks = <&clks IMX6QDL_CLK_IPU1>,
1290 <&clks IMX6QDL_CLK_IPU1_DI0>,
1291 <&clks IMX6QDL_CLK_IPU1_DI1>;
1292 clock-names = "bus", "di0", "di1";
1298 ipu1_csi0_from_ipu1_csi0_mux: endpoint {
1299 remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
1308 #address-cells = <1>;
1312 ipu1_di0_disp0: endpoint@0 {
1316 ipu1_di0_hdmi: endpoint@1 {
1318 remote-endpoint = <&hdmi_mux_0>;
1321 ipu1_di0_mipi: endpoint@2 {
1323 remote-endpoint = <&mipi_mux_0>;
1326 ipu1_di0_lvds0: endpoint@3 {
1328 remote-endpoint = <&lvds0_mux_0>;
1331 ipu1_di0_lvds1: endpoint@4 {
1333 remote-endpoint = <&lvds1_mux_0>;
1338 #address-cells = <1>;
1342 ipu1_di1_disp1: endpoint@0 {
1346 ipu1_di1_hdmi: endpoint@1 {
1348 remote-endpoint = <&hdmi_mux_1>;
1351 ipu1_di1_mipi: endpoint@2 {
1353 remote-endpoint = <&mipi_mux_1>;
1356 ipu1_di1_lvds0: endpoint@3 {
1358 remote-endpoint = <&lvds0_mux_1>;
1361 ipu1_di1_lvds1: endpoint@4 {
1363 remote-endpoint = <&lvds1_mux_1>;