1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
6 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Qualcomm IPQ8064";
16 compatible = "qcom,ipq8064";
17 interrupt-parent = <&intc>;
24 compatible = "qcom,krait";
25 enable-method = "qcom,kpss-acc-v1";
28 next-level-cache = <&L2>;
34 compatible = "qcom,krait";
35 enable-method = "qcom,kpss-acc-v1";
38 next-level-cache = <&L2>;
50 device_type = "memory";
55 compatible = "qcom,krait-pmu";
56 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
57 IRQ_TYPE_LEVEL_HIGH)>;
66 reg = <0x40000000 0x1000000>;
71 reg = <0x41000000 0x200000>;
78 compatible = "fixed-clock";
80 clock-frequency = <25000000>;
84 compatible = "fixed-clock";
86 clock-frequency = <25000000>;
89 sleep_clk: sleep_clk {
90 compatible = "fixed-clock";
91 clock-frequency = <32768>;
98 compatible = "qcom,scm-ipq806x", "qcom,scm";
103 #address-cells = <1>;
106 compatible = "simple-bus";
109 compatible = "qcom,lpass-cpu";
111 clocks = <&lcc AHBIX_CLK>,
114 clock-names = "ahbix-clk",
117 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
118 interrupt-names = "lpass-irq-lpaif";
119 reg = <0x28100000 0x10000>;
120 reg-names = "lpass-lpaif";
123 qcom_pinmux: pinmux@800000 {
124 compatible = "qcom,ipq8064-pinctrl";
125 reg = <0x800000 0x4000>;
128 gpio-ranges = <&qcom_pinmux 0 0 69>;
130 interrupt-controller;
131 #interrupt-cells = <2>;
132 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
134 pcie0_pins: pcie0_pinmux {
137 function = "pcie1_rst";
138 drive-strength = <12>;
143 pcie1_pins: pcie1_pinmux {
146 function = "pcie2_rst";
147 drive-strength = <12>;
152 pcie2_pins: pcie2_pinmux {
155 function = "pcie3_rst";
156 drive-strength = <12>;
163 pins = "gpio18", "gpio19", "gpio21";
165 drive-strength = <10>;
170 leds_pins: leds_pins {
172 pins = "gpio7", "gpio8", "gpio9",
175 drive-strength = <2>;
181 buttons_pins: buttons_pins {
184 drive-strength = <2>;
190 intc: interrupt-controller@2000000 {
191 compatible = "qcom,msm-qgic2";
192 interrupt-controller;
193 #interrupt-cells = <3>;
194 reg = <0x02000000 0x1000>,
199 compatible = "qcom,kpss-timer",
200 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
201 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
202 IRQ_TYPE_EDGE_RISING)>,
203 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
204 IRQ_TYPE_EDGE_RISING)>,
205 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
206 IRQ_TYPE_EDGE_RISING)>,
207 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
208 IRQ_TYPE_EDGE_RISING)>,
209 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
210 IRQ_TYPE_EDGE_RISING)>;
211 reg = <0x0200a000 0x100>;
212 clock-frequency = <25000000>,
214 clocks = <&sleep_clk>;
215 clock-names = "sleep";
216 cpu-offset = <0x80000>;
219 acc0: clock-controller@2088000 {
220 compatible = "qcom,kpss-acc-v1";
221 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
224 acc1: clock-controller@2098000 {
225 compatible = "qcom,kpss-acc-v1";
226 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
229 saw0: regulator@2089000 {
230 compatible = "qcom,saw2";
231 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
235 saw1: regulator@2099000 {
236 compatible = "qcom,saw2";
237 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
241 gsbi2: gsbi@12480000 {
242 compatible = "qcom,gsbi-v1.0.0";
244 reg = <0x12480000 0x100>;
245 clocks = <&gcc GSBI2_H_CLK>;
246 clock-names = "iface";
247 #address-cells = <1>;
252 syscon-tcsr = <&tcsr>;
255 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
256 reg = <0x12490000 0x1000>,
258 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
260 clock-names = "core", "iface";
265 compatible = "qcom,i2c-qup-v1.1.1";
266 reg = <0x124a0000 0x1000>;
267 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
270 clock-names = "core", "iface";
273 #address-cells = <1>;
279 gsbi4: gsbi@16300000 {
280 compatible = "qcom,gsbi-v1.0.0";
282 reg = <0x16300000 0x100>;
283 clocks = <&gcc GSBI4_H_CLK>;
284 clock-names = "iface";
285 #address-cells = <1>;
290 syscon-tcsr = <&tcsr>;
292 gsbi4_serial: serial@16340000 {
293 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
294 reg = <0x16340000 0x1000>,
296 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
298 clock-names = "core", "iface";
303 compatible = "qcom,i2c-qup-v1.1.1";
304 reg = <0x16380000 0x1000>;
305 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
308 clock-names = "core", "iface";
311 #address-cells = <1>;
316 gsbi5: gsbi@1a200000 {
317 compatible = "qcom,gsbi-v1.0.0";
319 reg = <0x1a200000 0x100>;
320 clocks = <&gcc GSBI5_H_CLK>;
321 clock-names = "iface";
322 #address-cells = <1>;
327 syscon-tcsr = <&tcsr>;
330 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
331 reg = <0x1a240000 0x1000>,
333 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
335 clock-names = "core", "iface";
340 compatible = "qcom,i2c-qup-v1.1.1";
341 reg = <0x1a280000 0x1000>;
342 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
345 clock-names = "core", "iface";
348 #address-cells = <1>;
353 compatible = "qcom,spi-qup-v1.1.1";
354 reg = <0x1a280000 0x1000>;
355 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
358 clock-names = "core", "iface";
361 #address-cells = <1>;
366 gsbi7: gsbi@16600000 {
368 compatible = "qcom,gsbi-v1.0.0";
370 reg = <0x16600000 0x100>;
371 clocks = <&gcc GSBI7_H_CLK>;
372 clock-names = "iface";
373 #address-cells = <1>;
376 syscon-tcsr = <&tcsr>;
378 gsbi7_serial: serial@16640000 {
379 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
380 reg = <0x16640000 0x1000>,
382 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
384 clock-names = "core", "iface";
389 sata_phy: sata-phy@1b400000 {
390 compatible = "qcom,ipq806x-sata-phy";
391 reg = <0x1b400000 0x200>;
393 clocks = <&gcc SATA_PHY_CFG_CLK>;
401 compatible = "qcom,ipq806x-ahci", "generic-ahci";
402 reg = <0x29000000 0x180>;
404 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&gcc SFAB_SATA_S_H_CLK>,
409 <&gcc SATA_RXOOB_CLK>,
410 <&gcc SATA_PMALIVE_CLK>;
411 clock-names = "slave_face", "iface", "core",
414 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
415 assigned-clock-rates = <100000000>, <100000000>;
418 phy-names = "sata-phy";
423 compatible = "qcom,ssbi";
424 reg = <0x00500000 0x1000>;
425 qcom,controller-type = "pmic-arbiter";
428 gcc: clock-controller@900000 {
429 compatible = "qcom,gcc-ipq8064";
430 reg = <0x00900000 0x4000>;
435 tcsr: syscon@1a400000 {
436 compatible = "qcom,tcsr-ipq8064", "syscon";
437 reg = <0x1a400000 0x100>;
440 lcc: clock-controller@28000000 {
441 compatible = "qcom,lcc-ipq8064";
442 reg = <0x28000000 0x1000>;
447 pcie0: pci@1b500000 {
448 compatible = "qcom,pcie-ipq8064";
449 reg = <0x1b500000 0x1000
452 0x0ff00000 0x100000>;
453 reg-names = "dbi", "elbi", "parf", "config";
455 linux,pci-domain = <0>;
456 bus-range = <0x00 0xff>;
458 #address-cells = <3>;
461 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
462 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
464 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
465 interrupt-names = "msi";
466 #interrupt-cells = <1>;
467 interrupt-map-mask = <0 0 0 0x7>;
468 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
469 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
470 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
471 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
473 clocks = <&gcc PCIE_A_CLK>,
477 <&gcc PCIE_ALT_REF_CLK>;
478 clock-names = "core", "iface", "phy", "aux", "ref";
480 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
481 assigned-clock-rates = <100000000>;
483 resets = <&gcc PCIE_ACLK_RESET>,
484 <&gcc PCIE_HCLK_RESET>,
485 <&gcc PCIE_POR_RESET>,
486 <&gcc PCIE_PCI_RESET>,
487 <&gcc PCIE_PHY_RESET>,
488 <&gcc PCIE_EXT_RESET>;
489 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
491 pinctrl-0 = <&pcie0_pins>;
492 pinctrl-names = "default";
495 perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
498 pcie1: pci@1b700000 {
499 compatible = "qcom,pcie-ipq8064";
500 reg = <0x1b700000 0x1000
503 0x31f00000 0x100000>;
504 reg-names = "dbi", "elbi", "parf", "config";
506 linux,pci-domain = <1>;
507 bus-range = <0x00 0xff>;
509 #address-cells = <3>;
512 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
513 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
515 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
516 interrupt-names = "msi";
517 #interrupt-cells = <1>;
518 interrupt-map-mask = <0 0 0 0x7>;
519 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
520 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
521 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
522 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
524 clocks = <&gcc PCIE_1_A_CLK>,
526 <&gcc PCIE_1_PHY_CLK>,
527 <&gcc PCIE_1_AUX_CLK>,
528 <&gcc PCIE_1_ALT_REF_CLK>;
529 clock-names = "core", "iface", "phy", "aux", "ref";
531 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
532 assigned-clock-rates = <100000000>;
534 resets = <&gcc PCIE_1_ACLK_RESET>,
535 <&gcc PCIE_1_HCLK_RESET>,
536 <&gcc PCIE_1_POR_RESET>,
537 <&gcc PCIE_1_PCI_RESET>,
538 <&gcc PCIE_1_PHY_RESET>,
539 <&gcc PCIE_1_EXT_RESET>;
540 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
542 pinctrl-0 = <&pcie1_pins>;
543 pinctrl-names = "default";
546 perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
549 pcie2: pci@1b900000 {
550 compatible = "qcom,pcie-ipq8064";
551 reg = <0x1b900000 0x1000
554 0x35f00000 0x100000>;
555 reg-names = "dbi", "elbi", "parf", "config";
557 linux,pci-domain = <2>;
558 bus-range = <0x00 0xff>;
560 #address-cells = <3>;
563 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
564 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
566 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
567 interrupt-names = "msi";
568 #interrupt-cells = <1>;
569 interrupt-map-mask = <0 0 0 0x7>;
570 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
571 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
572 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
573 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
575 clocks = <&gcc PCIE_2_A_CLK>,
577 <&gcc PCIE_2_PHY_CLK>,
578 <&gcc PCIE_2_AUX_CLK>,
579 <&gcc PCIE_2_ALT_REF_CLK>;
580 clock-names = "core", "iface", "phy", "aux", "ref";
582 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
583 assigned-clock-rates = <100000000>;
585 resets = <&gcc PCIE_2_ACLK_RESET>,
586 <&gcc PCIE_2_HCLK_RESET>,
587 <&gcc PCIE_2_POR_RESET>,
588 <&gcc PCIE_2_PCI_RESET>,
589 <&gcc PCIE_2_PHY_RESET>,
590 <&gcc PCIE_2_EXT_RESET>;
591 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
593 pinctrl-0 = <&pcie2_pins>;
594 pinctrl-names = "default";
597 perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
600 vsdcc_fixed: vsdcc-regulator {
601 compatible = "regulator-fixed";
602 regulator-name = "SDCC Power";
603 regulator-min-microvolt = <3300000>;
604 regulator-max-microvolt = <3300000>;
608 sdcc1bam:dma@12402000 {
609 compatible = "qcom,bam-v1.3.0";
610 reg = <0x12402000 0x8000>;
611 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&gcc SDC1_H_CLK>;
613 clock-names = "bam_clk";
618 sdcc3bam:dma@12182000 {
619 compatible = "qcom,bam-v1.3.0";
620 reg = <0x12182000 0x8000>;
621 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&gcc SDC3_H_CLK>;
623 clock-names = "bam_clk";
629 compatible = "simple-bus";
630 #address-cells = <1>;
636 compatible = "arm,pl18x", "arm,primecell";
637 arm,primecell-periphid = <0x00051180>;
638 reg = <0x12400000 0x2000>;
639 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
640 interrupt-names = "cmd_irq";
641 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
642 clock-names = "mclk", "apb_pclk";
644 max-frequency = <96000000>;
649 vmmc-supply = <&vsdcc_fixed>;
650 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
651 dma-names = "tx", "rx";
655 compatible = "arm,pl18x", "arm,primecell";
656 arm,primecell-periphid = <0x00051180>;
658 reg = <0x12180000 0x2000>;
659 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
660 interrupt-names = "cmd_irq";
661 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
662 clock-names = "mclk", "apb_pclk";
666 max-frequency = <192000000>;
670 vqmmc-supply = <&vsdcc_fixed>;
671 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
672 dma-names = "tx", "rx";