2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/clock/rv1108-cru.h>
45 #include <dt-bindings/pinctrl/rockchip.h>
50 compatible = "rockchip,rv1108";
52 interrupt-parent = <&gic>;
70 compatible = "arm,cortex-a7";
72 clocks = <&cru ARMCLK>;
73 operating-points-v2 = <&cpu_opp_table>;
77 cpu_opp_table: opp_table {
78 compatible = "operating-points-v2";
81 opp-hz = /bits/ 64 <408000000>;
82 opp-microvolt = <975000>;
83 clock-latency-ns = <40000>;
86 opp-hz = /bits/ 64 <600000000>;
87 opp-microvolt = <975000>;
88 clock-latency-ns = <40000>;
91 opp-hz = /bits/ 64 <816000000>;
92 opp-microvolt = <1025000>;
93 clock-latency-ns = <40000>;
96 opp-hz = /bits/ 64 <1008000000>;
97 opp-microvolt = <1150000>;
98 clock-latency-ns = <40000>;
103 compatible = "arm,cortex-a7-pmu";
104 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
108 compatible = "arm,armv7-timer";
109 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
110 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
111 clock-frequency = <24000000>;
115 compatible = "fixed-clock";
116 clock-frequency = <24000000>;
117 clock-output-names = "xin24m";
122 compatible = "simple-bus";
123 #address-cells = <1>;
127 pdma: pdma@102a0000 {
128 compatible = "arm,pl330", "arm,primecell";
129 reg = <0x102a0000 0x4000>;
130 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
132 arm,pl330-broken-no-flushp;
133 clocks = <&cru ACLK_DMAC>;
134 clock-names = "apb_pclk";
138 bus_intmem@10080000 {
139 compatible = "mmio-sram";
140 reg = <0x10080000 0x2000>;
141 #address-cells = <1>;
143 ranges = <0 0x10080000 0x2000>;
146 uart2: serial@10210000 {
147 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
148 reg = <0x10210000 0x100>;
149 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
152 clock-frequency = <24000000>;
153 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
154 clock-names = "baudclk", "apb_pclk";
155 pinctrl-names = "default";
156 pinctrl-0 = <&uart2m0_xfer>;
160 uart1: serial@10220000 {
161 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
162 reg = <0x10220000 0x100>;
163 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
166 clock-frequency = <24000000>;
167 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
168 clock-names = "baudclk", "apb_pclk";
169 pinctrl-names = "default";
170 pinctrl-0 = <&uart1_xfer>;
174 uart0: serial@10230000 {
175 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
176 reg = <0x10230000 0x100>;
177 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
180 clock-frequency = <24000000>;
181 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
182 clock-names = "baudclk", "apb_pclk";
183 pinctrl-names = "default";
184 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
189 compatible = "rockchip,rv1108-i2c";
190 reg = <0x10240000 0x1000>;
191 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
192 #address-cells = <1>;
194 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
195 clock-names = "i2c", "pclk";
196 pinctrl-names = "default";
197 pinctrl-0 = <&i2c1_xfer>;
198 rockchip,grf = <&grf>;
203 compatible = "rockchip,rv1108-i2c";
204 reg = <0x10250000 0x1000>;
205 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
206 #address-cells = <1>;
208 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
209 clock-names = "i2c", "pclk";
210 pinctrl-names = "default";
211 pinctrl-0 = <&i2c2m1_xfer>;
212 rockchip,grf = <&grf>;
217 compatible = "rockchip,rv1108-i2c";
218 reg = <0x10260000 0x1000>;
219 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
220 #address-cells = <1>;
222 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
223 clock-names = "i2c", "pclk";
224 pinctrl-names = "default";
225 pinctrl-0 = <&i2c3_xfer>;
226 rockchip,grf = <&grf>;
231 compatible = "rockchip,rv1108-spi";
232 reg = <0x10270000 0x1000>;
233 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
235 clock-names = "spiclk", "apb_pclk";
236 dmas = <&pdma 8>, <&pdma 9>;
238 #address-cells = <1>;
244 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
245 reg = <0x10280000 0x10>;
246 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
248 clock-names = "pwm", "pclk";
249 pinctrl-names = "default";
250 pinctrl-0 = <&pwm4_pin>;
256 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
257 reg = <0x10280010 0x10>;
258 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
260 clock-names = "pwm", "pclk";
261 pinctrl-names = "default";
262 pinctrl-0 = <&pwm5_pin>;
268 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
269 reg = <0x10280020 0x10>;
270 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
272 clock-names = "pwm", "pclk";
273 pinctrl-names = "default";
274 pinctrl-0 = <&pwm6_pin>;
280 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
281 reg = <0x10280030 0x10>;
282 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
284 clock-names = "pwm", "pclk";
285 pinctrl-names = "default";
286 pinctrl-0 = <&pwm7_pin>;
291 grf: syscon@10300000 {
292 compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
293 reg = <0x10300000 0x1000>;
294 #address-cells = <1>;
297 u2phy: usb2-phy@100 {
298 compatible = "rockchip,rv1108-usb2phy";
300 clocks = <&cru SCLK_USBPHY>;
301 clock-names = "phyclk";
303 clock-output-names = "usbphy";
304 rockchip,usbgrf = <&usbgrf>;
307 u2phy_otg: otg-port {
308 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
309 interrupt-names = "otg-mux";
314 u2phy_host: host-port {
315 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
316 interrupt-names = "linestate";
323 watchdog: wdt@10360000 {
324 compatible = "snps,dw-wdt";
325 reg = <0x10360000 0x100>;
326 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&cru PCLK_WDT>;
328 clock-names = "pclk_wdt";
333 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
334 reg = <0x1038c000 0x100>;
335 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
336 #io-channel-cells = <1>;
337 clock-frequency = <1000000>;
338 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
339 clock-names = "saradc", "apb_pclk";
344 compatible = "rockchip,rv1108-i2c";
345 reg = <0x20000000 0x1000>;
346 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
347 #address-cells = <1>;
349 clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
350 clock-names = "i2c", "pclk";
351 pinctrl-names = "default";
352 pinctrl-0 = <&i2c0_xfer>;
353 rockchip,grf = <&grf>;
358 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
359 reg = <0x20040000 0x10>;
360 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
362 clock-names = "pwm", "pclk";
363 pinctrl-names = "default";
364 pinctrl-0 = <&pwm0_pin>;
370 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
371 reg = <0x20040010 0x10>;
372 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
374 clock-names = "pwm", "pclk";
375 pinctrl-names = "default";
376 pinctrl-0 = <&pwm1_pin>;
382 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
383 reg = <0x20040020 0x10>;
384 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
386 clock-names = "pwm", "pclk";
387 pinctrl-names = "default";
388 pinctrl-0 = <&pwm2_pin>;
394 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
395 reg = <0x20040030 0x10>;
396 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
398 clock-names = "pwm", "pclk";
399 pinctrl-names = "default";
400 pinctrl-0 = <&pwm3_pin>;
405 pmugrf: syscon@20060000 {
406 compatible = "rockchip,rv1108-pmugrf", "syscon";
407 reg = <0x20060000 0x1000>;
410 usbgrf: syscon@202a0000 {
411 compatible = "rockchip,rv1108-usbgrf", "syscon";
412 reg = <0x202a0000 0x1000>;
415 cru: clock-controller@20200000 {
416 compatible = "rockchip,rv1108-cru";
417 reg = <0x20200000 0x1000>;
418 rockchip,grf = <&grf>;
423 emmc: dwmmc@30110000 {
424 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
425 reg = <0x30110000 0x4000>;
426 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
428 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
429 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
430 fifo-depth = <0x100>;
431 max-frequency = <150000000>;
435 sdio: dwmmc@30120000 {
436 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
437 reg = <0x30120000 0x4000>;
438 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
440 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
441 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
442 fifo-depth = <0x100>;
443 max-frequency = <150000000>;
447 sdmmc: dwmmc@30130000 {
448 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
449 reg = <0x30130000 0x4000>;
450 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
452 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
453 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
454 fifo-depth = <0x100>;
455 max-frequency = <100000000>;
456 pinctrl-names = "default";
457 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
461 usb_host_ehci: usb@30140000 {
462 compatible = "generic-ehci";
463 reg = <0x30140000 0x20000>;
464 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&cru HCLK_HOST0>, <&u2phy>;
466 clock-names = "usbhost", "utmi";
467 phys = <&u2phy_host>;
472 usb_host_ohci: usb@30160000 {
473 compatible = "generic-ohci";
474 reg = <0x30160000 0x20000>;
475 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&cru HCLK_HOST0>, <&u2phy>;
477 clock-names = "usbhost", "utmi";
478 phys = <&u2phy_host>;
483 usb_otg: usb@30180000 {
484 compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
486 reg = <0x30180000 0x40000>;
487 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&cru HCLK_OTG>;
491 g-np-tx-fifo-size = <16>;
492 g-rx-fifo-size = <280>;
493 g-tx-fifo-size = <256 128 128 64 32 16>;
496 phy-names = "usb2-phy";
500 gic: interrupt-controller@32010000 {
501 compatible = "arm,gic-400";
502 interrupt-controller;
503 #interrupt-cells = <3>;
504 #address-cells = <0>;
506 reg = <0x32011000 0x1000>,
510 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
514 compatible = "rockchip,rv1108-pinctrl";
515 rockchip,grf = <&grf>;
516 rockchip,pmu = <&pmugrf>;
517 #address-cells = <1>;
521 gpio0: gpio0@20030000 {
522 compatible = "rockchip,gpio-bank";
523 reg = <0x20030000 0x100>;
524 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
530 interrupt-controller;
531 #interrupt-cells = <2>;
534 gpio1: gpio1@10310000 {
535 compatible = "rockchip,gpio-bank";
536 reg = <0x10310000 0x100>;
537 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
543 interrupt-controller;
544 #interrupt-cells = <2>;
547 gpio2: gpio2@10320000 {
548 compatible = "rockchip,gpio-bank";
549 reg = <0x10320000 0x100>;
550 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
556 interrupt-controller;
557 #interrupt-cells = <2>;
560 gpio3: gpio3@10330000 {
561 compatible = "rockchip,gpio-bank";
562 reg = <0x10330000 0x100>;
563 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
569 interrupt-controller;
570 #interrupt-cells = <2>;
573 pcfg_pull_up: pcfg-pull-up {
577 pcfg_pull_down: pcfg-pull-down {
581 pcfg_pull_none: pcfg-pull-none {
585 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
586 drive-strength = <8>;
589 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
590 drive-strength = <12>;
593 pcfg_pull_none_smt: pcfg-pull-none-smt {
595 input-schmitt-enable;
598 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
600 drive-strength = <8>;
603 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
604 drive-strength = <4>;
607 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
609 drive-strength = <4>;
612 pcfg_output_high: pcfg-output-high {
616 pcfg_output_low: pcfg-output-low {
620 pcfg_input_high: pcfg-input-high {
626 i2c0_xfer: i2c0-xfer {
627 rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>,
628 <0 RK_PB2 RK_FUNC_1 &pcfg_pull_none_smt>;
633 i2c1_xfer: i2c1-xfer {
634 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
635 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
640 i2c2m1_xfer: i2c2m1-xfer {
641 rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
642 <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
645 i2c2m1_gpio: i2c2m1-gpio {
646 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
647 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
652 i2c2m05v_xfer: i2c2m05v-xfer {
653 rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
654 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
657 i2c2m05v_gpio: i2c2m05v-gpio {
658 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
659 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
664 i2c3_xfer: i2c3-xfer {
665 rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
666 <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
672 rockchip,pins = <0 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
678 rockchip,pins = <0 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
684 rockchip,pins = <0 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
690 rockchip,pins = <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
696 rockchip,pins = <1 RK_PC1 RK_FUNC_3 &pcfg_pull_none>;
702 rockchip,pins = <1 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
708 rockchip,pins = <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>;
714 rockchip,pins = <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
719 sdmmc_clk: sdmmc-clk {
720 rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
723 sdmmc_cmd: sdmmc-cmd {
724 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
728 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
731 sdmmc_bus1: sdmmc-bus1 {
732 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
735 sdmmc_bus4: sdmmc-bus4 {
736 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
737 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
738 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
739 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
744 uart0_xfer: uart0-xfer {
745 rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
746 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
749 uart0_cts: uart0-cts {
750 rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
753 uart0_rts: uart0-rts {
754 rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
757 uart0_rts_gpio: uart0-rts-gpio {
758 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
763 uart1_xfer: uart1-xfer {
764 rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
765 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
768 uart1_cts: uart1-cts {
769 rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
772 uart1_rts: uart1-rts {
773 rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
778 uart2m0_xfer: uart2m0-xfer {
779 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
780 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
785 uart2m1_xfer: uart2m1-xfer {
786 rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
787 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
792 uart2_5v_cts: uart2_5v-cts {
793 rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
796 uart2_5v_rts: uart2_5v-rts {
797 rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;