src/arm/sun9i-a80.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46
  47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
  48 #include <dt-bindings/clock/sun9i-a80-de.h>
  49 #include <dt-bindings/clock/sun9i-a80-usb.h>
  50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
  51 #include <dt-bindings/reset/sun9i-a80-de.h>
  52 #include <dt-bindings/reset/sun9i-a80-usb.h>
  53
  54 / {
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57         interrupt-parent = <&gic>;
  58
  59         aliases {
  60                 ethernet0 = &gmac;
  61         };
  62
  63         cpus {
  64                 #address-cells = <1>;
  65                 #size-cells = <0>;
  66
  67                 cpu0: cpu@0 {
  68                         compatible = "arm,cortex-a7";
  69                         device_type = "cpu";
  70                         cci-control-port = <&cci_control0>;
  71                         clock-frequency = <12000000>;
  72                         enable-method = "allwinner,sun9i-a80-smp";
  73                         reg = <0x0>;
  74                 };
  75
  76                 cpu1: cpu@1 {
  77                         compatible = "arm,cortex-a7";
  78                         device_type = "cpu";
  79                         cci-control-port = <&cci_control0>;
  80                         clock-frequency = <12000000>;
  81                         enable-method = "allwinner,sun9i-a80-smp";
  82                         reg = <0x1>;
  83                 };
  84
  85                 cpu2: cpu@2 {
  86                         compatible = "arm,cortex-a7";
  87                         device_type = "cpu";
  88                         cci-control-port = <&cci_control0>;
  89                         clock-frequency = <12000000>;
  90                         enable-method = "allwinner,sun9i-a80-smp";
  91                         reg = <0x2>;
  92                 };
  93
  94                 cpu3: cpu@3 {
  95                         compatible = "arm,cortex-a7";
  96                         device_type = "cpu";
  97                         cci-control-port = <&cci_control0>;
  98                         clock-frequency = <12000000>;
  99                         enable-method = "allwinner,sun9i-a80-smp";
 100                         reg = <0x3>;
 101                 };
 102
 103                 cpu4: cpu@100 {
 104                         compatible = "arm,cortex-a15";
 105                         device_type = "cpu";
 106                         cci-control-port = <&cci_control1>;
 107                         clock-frequency = <18000000>;
 108                         enable-method = "allwinner,sun9i-a80-smp";
 109                         reg = <0x100>;
 110                 };
 111
 112                 cpu5: cpu@101 {
 113                         compatible = "arm,cortex-a15";
 114                         device_type = "cpu";
 115                         cci-control-port = <&cci_control1>;
 116                         clock-frequency = <18000000>;
 117                         enable-method = "allwinner,sun9i-a80-smp";
 118                         reg = <0x101>;
 119                 };
 120
 121                 cpu6: cpu@102 {
 122                         compatible = "arm,cortex-a15";
 123                         device_type = "cpu";
 124                         cci-control-port = <&cci_control1>;
 125                         clock-frequency = <18000000>;
 126                         enable-method = "allwinner,sun9i-a80-smp";
 127                         reg = <0x102>;
 128                 };
 129
 130                 cpu7: cpu@103 {
 131                         compatible = "arm,cortex-a15";
 132                         device_type = "cpu";
 133                         cci-control-port = <&cci_control1>;
 134                         clock-frequency = <18000000>;
 135                         enable-method = "allwinner,sun9i-a80-smp";
 136                         reg = <0x103>;
 137                 };
 138         };
 139
 140         timer {
 141                 compatible = "arm,armv7-timer";
 142                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 143                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 144                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 145                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 146                 clock-frequency = <24000000>;
 147                 arm,cpu-registers-not-fw-configured;
 148         };
 149
 150         clocks {
 151                 #address-cells = <1>;
 152                 #size-cells = <1>;
 153                 /*
 154                  * map 64 bit address range down to 32 bits,
 155                  * as the peripherals are all under 512MB.
 156                  */
 157                 ranges = <0 0 0 0x20000000>;
 158
 159                 /*
 160                  * This clock is actually configurable from the PRCM address
 161                  * space. The external 24M oscillator can be turned off, and
 162                  * the clock switched to an internal 16M RC oscillator. Under
 163                  * normal operation there's no reason to do this, and the
 164                  * default is to use the external good one, so just model this
 165                  * as a fixed clock. Also it is not entirely clear if the
 166                  * osc24M mux in the PRCM affects the entire clock tree, which
 167                  * would also throw all the PLL clock rates off, or just the
 168                  * downstream clocks in the PRCM.
 169                  */
 170                 osc24M: clk-24M {
 171                         #clock-cells = <0>;
 172                         compatible = "fixed-clock";
 173                         clock-frequency = <24000000>;
 174                         clock-output-names = "osc24M";
 175                 };
 176
 177                 /*
 178                  * The 32k clock is from an external source, normally the
 179                  * AC100 codec/RTC chip. This serves as a placeholder for
 180                  * board dts files to specify the source.
 181                  */
 182                 osc32k: clk-32k {
 183                         #clock-cells = <0>;
 184                         compatible = "fixed-factor-clock";
 185                         clock-div = <1>;
 186                         clock-mult = <1>;
 187                         clock-output-names = "osc32k";
 188                 };
 189
 190                 /*
 191                  * The following two are dummy clocks, placeholders
 192                  * used in the gmac_tx clock. The gmac driver will
 193                  * choose one parent depending on the PHY interface
 194                  * mode, using clk_set_rate auto-reparenting.
 195                  *
 196                  * The actual TX clock rate is not controlled by the
 197                  * gmac_tx clock.
 198                  */
 199                 mii_phy_tx_clk: mii_phy_tx_clk {
 200                         #clock-cells = <0>;
 201                         compatible = "fixed-clock";
 202                         clock-frequency = <25000000>;
 203                         clock-output-names = "mii_phy_tx";
 204                 };
 205
 206                 gmac_int_tx_clk: gmac_int_tx_clk {
 207                         #clock-cells = <0>;
 208                         compatible = "fixed-clock";
 209                         clock-frequency = <125000000>;
 210                         clock-output-names = "gmac_int_tx";
 211                 };
 212
 213                 gmac_tx_clk: clk@800030 {
 214                         #clock-cells = <0>;
 215                         compatible = "allwinner,sun7i-a20-gmac-clk";
 216                         reg = <0x00800030 0x4>;
 217                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 218                         clock-output-names = "gmac_tx";
 219                 };
 220
 221                 cpus_clk: clk@8001410 {
 222                         compatible = "allwinner,sun9i-a80-cpus-clk";
 223                         reg = <0x08001410 0x4>;
 224                         #clock-cells = <0>;
 225                         clocks = <&osc32k>, <&osc24M>,
 226                                  <&ccu CLK_PLL_PERIPH0>,
 227                                  <&ccu CLK_PLL_AUDIO>;
 228                         clock-output-names = "cpus";
 229                 };
 230
 231                 ahbs: clk-ahbs {
 232                         compatible = "fixed-factor-clock";
 233                         #clock-cells = <0>;
 234                         clock-div = <1>;
 235                         clock-mult = <1>;
 236                         clocks = <&cpus_clk>;
 237                         clock-output-names = "ahbs";
 238                 };
 239
 240                 apbs: clk@800141c {
 241                         compatible = "allwinner,sun8i-a23-apb0-clk";
 242                         reg = <0x0800141c 0x4>;
 243                         #clock-cells = <0>;
 244                         clocks = <&ahbs>;
 245                         clock-output-names = "apbs";
 246                 };
 247
 248                 apbs_gates: clk@8001428 {
 249                         compatible = "allwinner,sun9i-a80-apbs-gates-clk";
 250                         reg = <0x08001428 0x4>;
 251                         #clock-cells = <1>;
 252                         clocks = <&apbs>;
 253                         clock-indices = <0>, <1>,
 254                                         <2>, <3>,
 255                                         <4>, <5>,
 256                                         <6>, <7>,
 257                                         <12>, <13>,
 258                                         <16>, <17>,
 259                                         <18>, <20>;
 260                         clock-output-names = "apbs_pio", "apbs_ir",
 261                                         "apbs_timer", "apbs_rsb",
 262                                         "apbs_uart", "apbs_1wire",
 263                                         "apbs_i2c0", "apbs_i2c1",
 264                                         "apbs_ps2_0", "apbs_ps2_1",
 265                                         "apbs_dma", "apbs_i2s0",
 266                                         "apbs_i2s1", "apbs_twd";
 267                 };
 268
 269                 r_1wire_clk: clk@8001450 {
 270                         reg = <0x08001450 0x4>;
 271                         #clock-cells = <0>;
 272                         compatible = "allwinner,sun4i-a10-mod0-clk";
 273                         clocks = <&osc32k>, <&osc24M>;
 274                         clock-output-names = "r_1wire";
 275                 };
 276
 277                 r_ir_clk: clk@8001454 {
 278                         reg = <0x08001454 0x4>;
 279                         #clock-cells = <0>;
 280                         compatible = "allwinner,sun4i-a10-mod0-clk";
 281                         clocks = <&osc32k>, <&osc24M>;
 282                         clock-output-names = "r_ir";
 283                 };
 284         };
 285
 286         de: display-engine {
 287                 compatible = "allwinner,sun9i-a80-display-engine";
 288                 allwinner,pipelines = <&fe0>, <&fe1>;
 289                 status = "disabled";
 290         };
 291
 292         soc@20000 {
 293                 compatible = "simple-bus";
 294                 #address-cells = <1>;
 295                 #size-cells = <1>;
 296                 /*
 297                  * map 64 bit address range down to 32 bits,
 298                  * as the peripherals are all under 512MB.
 299                  */
 300                 ranges = <0 0 0 0x20000000>;
 301
 302                 sram_b: sram@20000 {
 303                         /* 256 KiB secure SRAM at 0x20000 */
 304                         compatible = "mmio-sram";
 305                         reg = <0x00020000 0x40000>;
 306
 307                         #address-cells = <1>;
 308                         #size-cells = <1>;
 309                         ranges = <0 0x00020000 0x40000>;
 310
 311                         smp-sram@1000 {
 312                                 /*
 313                                  * This is checked by BROM to determine if
 314                                  * cpu0 should jump to SMP entry vector
 315                                  */
 316                                 compatible = "allwinner,sun9i-a80-smp-sram";
 317                                 reg = <0x1000 0x8>;
 318                         };
 319                 };
 320
 321                 gmac: ethernet@830000 {
 322                         compatible = "allwinner,sun7i-a20-gmac";
 323                         reg = <0x00830000 0x1054>;
 324                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 325                         interrupt-names = "macirq";
 326                         clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>;
 327                         clock-names = "stmmaceth", "allwinner_gmac_tx";
 328                         resets = <&ccu RST_BUS_GMAC>;
 329                         reset-names = "stmmaceth";
 330                         snps,pbl = <2>;
 331                         snps,fixed-burst;
 332                         snps,force_sf_dma_mode;
 333                         status = "disabled";
 334
 335                         mdio: mdio {
 336                                 compatible = "snps,dwmac-mdio";
 337                                 #address-cells = <1>;
 338                                 #size-cells = <0>;
 339                         };
 340                 };
 341
 342                 ehci0: usb@a00000 {
 343                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
 344                         reg = <0x00a00000 0x100>;
 345                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 346                         clocks = <&usb_clocks CLK_BUS_HCI0>;
 347                         resets = <&usb_clocks RST_USB0_HCI>;
 348                         phys = <&usbphy1>;
 349                         phy-names = "usb";
 350                         status = "disabled";
 351                 };
 352
 353                 ohci0: usb@a00400 {
 354                         compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
 355                         reg = <0x00a00400 0x100>;
 356                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 357                         clocks = <&usb_clocks CLK_BUS_HCI0>,
 358                                  <&usb_clocks CLK_USB_OHCI0>;
 359                         resets = <&usb_clocks RST_USB0_HCI>;
 360                         phys = <&usbphy1>;
 361                         phy-names = "usb";
 362                         status = "disabled";
 363                 };
 364
 365                 usbphy1: phy@a00800 {
 366                         compatible = "allwinner,sun9i-a80-usb-phy";
 367                         reg = <0x00a00800 0x4>;
 368                         clocks = <&usb_clocks CLK_USB0_PHY>;
 369                         clock-names = "phy";
 370                         resets = <&usb_clocks RST_USB0_PHY>;
 371                         reset-names = "phy";
 372                         status = "disabled";
 373                         #phy-cells = <0>;
 374                 };
 375
 376                 ehci1: usb@a01000 {
 377                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
 378                         reg = <0x00a01000 0x100>;
 379                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 380                         clocks = <&usb_clocks CLK_BUS_HCI1>;
 381                         resets = <&usb_clocks RST_USB1_HCI>;
 382                         phys = <&usbphy2>;
 383                         phy-names = "usb";
 384                         status = "disabled";
 385                 };
 386
 387                 usbphy2: phy@a01800 {
 388                         compatible = "allwinner,sun9i-a80-usb-phy";
 389                         reg = <0x00a01800 0x4>;
 390                         clocks = <&usb_clocks CLK_USB1_HSIC>,
 391                                  <&usb_clocks CLK_USB_HSIC>,
 392                                  <&usb_clocks CLK_USB1_PHY>;
 393                         clock-names = "hsic_480M",
 394                                       "hsic_12M",
 395                                       "phy";
 396                         resets = <&usb_clocks RST_USB1_HSIC>,
 397                                  <&usb_clocks RST_USB1_PHY>;
 398                         reset-names = "hsic",
 399                                       "phy";
 400                         status = "disabled";
 401                         #phy-cells = <0>;
 402                         /* usb1 is always used with HSIC */
 403                         phy_type = "hsic";
 404                 };
 405
 406                 ehci2: usb@a02000 {
 407                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
 408                         reg = <0x00a02000 0x100>;
 409                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 410                         clocks = <&usb_clocks CLK_BUS_HCI2>;
 411                         resets = <&usb_clocks RST_USB2_HCI>;
 412                         phys = <&usbphy3>;
 413                         phy-names = "usb";
 414                         status = "disabled";
 415                 };
 416
 417                 ohci2: usb@a02400 {
 418                         compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
 419                         reg = <0x00a02400 0x100>;
 420                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 421                         clocks = <&usb_clocks CLK_BUS_HCI2>,
 422                                  <&usb_clocks CLK_USB_OHCI2>;
 423                         resets = <&usb_clocks RST_USB2_HCI>;
 424                         phys = <&usbphy3>;
 425                         phy-names = "usb";
 426                         status = "disabled";
 427                 };
 428
 429                 usbphy3: phy@a02800 {
 430                         compatible = "allwinner,sun9i-a80-usb-phy";
 431                         reg = <0x00a02800 0x4>;
 432                         clocks = <&usb_clocks CLK_USB2_HSIC>,
 433                                  <&usb_clocks CLK_USB_HSIC>,
 434                                  <&usb_clocks CLK_USB2_PHY>;
 435                         clock-names = "hsic_480M",
 436                                       "hsic_12M",
 437                                       "phy";
 438                         resets = <&usb_clocks RST_USB2_HSIC>,
 439                                  <&usb_clocks RST_USB2_PHY>;
 440                         reset-names = "hsic",
 441                                       "phy";
 442                         status = "disabled";
 443                         #phy-cells = <0>;
 444                 };
 445
 446                 usb_clocks: clock@a08000 {
 447                         compatible = "allwinner,sun9i-a80-usb-clks";
 448                         reg = <0x00a08000 0x8>;
 449                         clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
 450                         clock-names = "bus", "hosc";
 451                         #clock-cells = <1>;
 452                         #reset-cells = <1>;
 453                 };
 454
 455                 cpucfg@1700000 {
 456                         compatible = "allwinner,sun9i-a80-cpucfg";
 457                         reg = <0x01700000 0x100>;
 458                 };
 459
 460                 mmc0: mmc@1c0f000 {
 461                         compatible = "allwinner,sun9i-a80-mmc";
 462                         reg = <0x01c0f000 0x1000>;
 463                         clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>,
 464                                  <&ccu CLK_MMC0_OUTPUT>,
 465                                  <&ccu CLK_MMC0_SAMPLE>;
 466                         clock-names = "ahb", "mmc", "output", "sample";
 467                         resets = <&mmc_config_clk 0>;
 468                         reset-names = "ahb";
 469                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 470                         status = "disabled";
 471                         #address-cells = <1>;
 472                         #size-cells = <0>;
 473                 };
 474
 475                 mmc1: mmc@1c10000 {
 476                         compatible = "allwinner,sun9i-a80-mmc";
 477                         reg = <0x01c10000 0x1000>;
 478                         clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>,
 479                                  <&ccu CLK_MMC1_OUTPUT>,
 480                                  <&ccu CLK_MMC1_SAMPLE>;
 481                         clock-names = "ahb", "mmc", "output", "sample";
 482                         resets = <&mmc_config_clk 1>;
 483                         reset-names = "ahb";
 484                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 485                         status = "disabled";
 486                         #address-cells = <1>;
 487                         #size-cells = <0>;
 488                 };
 489
 490                 mmc2: mmc@1c11000 {
 491                         compatible = "allwinner,sun9i-a80-mmc";
 492                         reg = <0x01c11000 0x1000>;
 493                         clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>,
 494                                  <&ccu CLK_MMC2_OUTPUT>,
 495                                  <&ccu CLK_MMC2_SAMPLE>;
 496                         clock-names = "ahb", "mmc", "output", "sample";
 497                         resets = <&mmc_config_clk 2>;
 498                         reset-names = "ahb";
 499                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 500                         status = "disabled";
 501                         #address-cells = <1>;
 502                         #size-cells = <0>;
 503                 };
 504
 505                 mmc3: mmc@1c12000 {
 506                         compatible = "allwinner,sun9i-a80-mmc";
 507                         reg = <0x01c12000 0x1000>;
 508                         clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>,
 509                                  <&ccu CLK_MMC3_OUTPUT>,
 510                                  <&ccu CLK_MMC3_SAMPLE>;
 511                         clock-names = "ahb", "mmc", "output", "sample";
 512                         resets = <&mmc_config_clk 3>;
 513                         reset-names = "ahb";
 514                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 515                         status = "disabled";
 516                         #address-cells = <1>;
 517                         #size-cells = <0>;
 518                 };
 519
 520                 mmc_config_clk: clk@1c13000 {
 521                         compatible = "allwinner,sun9i-a80-mmc-config-clk";
 522                         reg = <0x01c13000 0x10>;
 523                         clocks = <&ccu CLK_BUS_MMC>;
 524                         clock-names = "ahb";
 525                         resets = <&ccu RST_BUS_MMC>;
 526                         reset-names = "ahb";
 527                         #clock-cells = <1>;
 528                         #reset-cells = <1>;
 529                         clock-output-names = "mmc0_config", "mmc1_config",
 530                                              "mmc2_config", "mmc3_config";
 531                 };
 532
 533                 gic: interrupt-controller@1c41000 {
 534                         compatible = "arm,gic-400";
 535                         reg = <0x01c41000 0x1000>,
 536                               <0x01c42000 0x2000>,
 537                               <0x01c44000 0x2000>,
 538                               <0x01c46000 0x2000>;
 539                         interrupt-controller;
 540                         #interrupt-cells = <3>;
 541                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 542                 };
 543
 544                 cci: cci@1c90000 {
 545                         compatible = "arm,cci-400";
 546                         #address-cells = <1>;
 547                         #size-cells = <1>;
 548                         reg = <0x01c90000 0x1000>;
 549                         ranges = <0x0 0x01c90000 0x10000>;
 550
 551                         cci_control0: slave-if@4000 {
 552                                 compatible = "arm,cci-400-ctrl-if";
 553                                 interface-type = "ace";
 554                                 reg = <0x4000 0x1000>;
 555                         };
 556
 557                         cci_control1: slave-if@5000 {
 558                                 compatible = "arm,cci-400-ctrl-if";
 559                                 interface-type = "ace";
 560                                 reg = <0x5000 0x1000>;
 561                         };
 562
 563                         pmu@9000 {
 564                                  compatible = "arm,cci-400-pmu,r1";
 565                                  reg = <0x9000 0x5000>;
 566                                  interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 567                                               <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 568                                               <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 569                                               <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 570                                               <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 571                         };
 572                 };
 573
 574                 de_clocks: clock@3000000 {
 575                         compatible = "allwinner,sun9i-a80-de-clks";
 576                         reg = <0x03000000 0x30>;
 577                         clocks = <&ccu CLK_DE>,
 578                                  <&ccu CLK_SDRAM>,
 579                                  <&ccu CLK_BUS_DE>;
 580                         clock-names = "mod",
 581                                       "dram",
 582                                       "bus";
 583                         resets = <&ccu RST_BUS_DE>;
 584                         #clock-cells = <1>;
 585                         #reset-cells = <1>;
 586                 };
 587
 588                 fe0: display-frontend@3100000 {
 589                         compatible = "allwinner,sun9i-a80-display-frontend";
 590                         reg = <0x03100000 0x40000>;
 591                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 592                         clocks = <&de_clocks CLK_BUS_FE0>, <&de_clocks CLK_FE0>,
 593                                  <&de_clocks CLK_DRAM_FE0>;
 594                         clock-names = "ahb", "mod",
 595                                       "ram";
 596                         resets = <&de_clocks RST_FE0>;
 597
 598                         ports {
 599                                 #address-cells = <1>;
 600                                 #size-cells = <0>;
 601
 602                                 fe0_out: port@1 {
 603                                         reg = <1>;
 604
 605                                         fe0_out_deu0: endpoint {
 606                                                 remote-endpoint = <&deu0_in_fe0>;
 607                                         };
 608                                 };
 609                         };
 610                 };
 611
 612                 fe1: display-frontend@3140000 {
 613                         compatible = "allwinner,sun9i-a80-display-frontend";
 614                         reg = <0x03140000 0x40000>;
 615                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 616                         clocks = <&de_clocks CLK_BUS_FE1>, <&de_clocks CLK_FE1>,
 617                                  <&de_clocks CLK_DRAM_FE1>;
 618                         clock-names = "ahb", "mod",
 619                                       "ram";
 620                         resets = <&de_clocks RST_FE0>;
 621
 622                         ports {
 623                                 #address-cells = <1>;
 624                                 #size-cells = <0>;
 625
 626                                 fe1_out: port@1 {
 627                                         reg = <1>;
 628
 629                                         fe1_out_deu1: endpoint {
 630                                                 remote-endpoint = <&deu1_in_fe1>;
 631                                         };
 632                                 };
 633                         };
 634                 };
 635
 636                 be0: display-backend@3200000 {
 637                         compatible = "allwinner,sun9i-a80-display-backend";
 638                         reg = <0x03200000 0x40000>;
 639                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 640                         clocks = <&de_clocks CLK_BUS_BE0>, <&de_clocks CLK_BE0>,
 641                                  <&de_clocks CLK_DRAM_BE0>;
 642                         clock-names = "ahb", "mod",
 643                                       "ram";
 644                         resets = <&de_clocks RST_BE0>;
 645
 646                         ports {
 647                                 #address-cells = <1>;
 648                                 #size-cells = <0>;
 649
 650                                 be0_in: port@0 {
 651                                         #address-cells = <1>;
 652                                         #size-cells = <0>;
 653                                         reg = <0>;
 654
 655                                         be0_in_deu0: endpoint@0 {
 656                                                 reg = <0>;
 657                                                 remote-endpoint = <&deu0_out_be0>;
 658                                         };
 659
 660                                         be0_in_deu1: endpoint@1 {
 661                                                 reg = <1>;
 662                                                 remote-endpoint = <&deu1_out_be0>;
 663                                         };
 664                                 };
 665
 666                                 be0_out: port@1 {
 667                                         reg = <1>;
 668
 669                                         be0_out_drc0: endpoint {
 670                                                 remote-endpoint = <&drc0_in_be0>;
 671                                         };
 672                                 };
 673                         };
 674                 };
 675
 676                 be1: display-backend@3240000 {
 677                         compatible = "allwinner,sun9i-a80-display-backend";
 678                         reg = <0x03240000 0x40000>;
 679                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 680                         clocks = <&de_clocks CLK_BUS_BE1>, <&de_clocks CLK_BE1>,
 681                                  <&de_clocks CLK_DRAM_BE1>;
 682                         clock-names = "ahb", "mod",
 683                                       "ram";
 684                         resets = <&de_clocks RST_BE1>;
 685
 686                         ports {
 687                                 #address-cells = <1>;
 688                                 #size-cells = <0>;
 689
 690                                 be1_in: port@0 {
 691                                         #address-cells = <1>;
 692                                         #size-cells = <0>;
 693                                         reg = <0>;
 694
 695                                         be1_in_deu0: endpoint@0 {
 696                                                 reg = <0>;
 697                                                 remote-endpoint = <&deu0_out_be1>;
 698                                         };
 699
 700                                         be1_in_deu1: endpoint@1 {
 701                                                 reg = <1>;
 702                                                 remote-endpoint = <&deu1_out_be1>;
 703                                         };
 704                                 };
 705
 706                                 be1_out: port@1 {
 707                                         reg = <1>;
 708
 709                                         be1_out_drc1: endpoint {
 710                                                 remote-endpoint = <&drc1_in_be1>;
 711                                         };
 712                                 };
 713                         };
 714                 };
 715
 716                 deu0: deu@3300000 {
 717                         compatible = "allwinner,sun9i-a80-deu";
 718                         reg = <0x03300000 0x40000>;
 719                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 720                         clocks = <&de_clocks CLK_BUS_DEU0>,
 721                                  <&de_clocks CLK_IEP_DEU0>,
 722                                  <&de_clocks CLK_DRAM_DEU0>;
 723                         clock-names = "ahb",
 724                                       "mod",
 725                                       "ram";
 726                         resets = <&de_clocks RST_DEU0>;
 727
 728                         ports {
 729                                 #address-cells = <1>;
 730                                 #size-cells = <0>;
 731
 732                                 deu0_in: port@0 {
 733                                         reg = <0>;
 734
 735                                         deu0_in_fe0: endpoint {
 736                                                 remote-endpoint = <&fe0_out_deu0>;
 737                                         };
 738                                 };
 739
 740                                 deu0_out: port@1 {
 741                                         #address-cells = <1>;
 742                                         #size-cells = <0>;
 743                                         reg = <1>;
 744
 745                                         deu0_out_be0: endpoint@0 {
 746                                                 reg = <0>;
 747                                                 remote-endpoint = <&be0_in_deu0>;
 748                                         };
 749
 750                                         deu0_out_be1: endpoint@1 {
 751                                                 reg = <1>;
 752                                                 remote-endpoint = <&be1_in_deu0>;
 753                                         };
 754                                 };
 755                         };
 756                 };
 757
 758                 deu1: deu@3340000 {
 759                         compatible = "allwinner,sun9i-a80-deu";
 760                         reg = <0x03340000 0x40000>;
 761                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 762                         clocks = <&de_clocks CLK_BUS_DEU1>,
 763                                  <&de_clocks CLK_IEP_DEU1>,
 764                                  <&de_clocks CLK_DRAM_DEU1>;
 765                         clock-names = "ahb",
 766                                       "mod",
 767                                       "ram";
 768                         resets = <&de_clocks RST_DEU1>;
 769
 770                         ports {
 771                                 #address-cells = <1>;
 772                                 #size-cells = <0>;
 773
 774                                 deu1_in: port@0 {
 775                                         reg = <0>;
 776
 777                                         deu1_in_fe1: endpoint {
 778                                                 remote-endpoint = <&fe1_out_deu1>;
 779                                         };
 780                                 };
 781
 782                                 deu1_out: port@1 {
 783                                         #address-cells = <1>;
 784                                         #size-cells = <0>;
 785                                         reg = <1>;
 786
 787                                         deu1_out_be0: endpoint@0 {
 788                                                 reg = <0>;
 789                                                 remote-endpoint = <&be0_in_deu1>;
 790                                         };
 791
 792                                         deu1_out_be1: endpoint@1 {
 793                                                 reg = <1>;
 794                                                 remote-endpoint = <&be1_in_deu1>;
 795                                         };
 796                                 };
 797                         };
 798                 };
 799
 800                 drc0: drc@3400000 {
 801                         compatible = "allwinner,sun9i-a80-drc";
 802                         reg = <0x03400000 0x40000>;
 803                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 804                         clocks = <&de_clocks CLK_BUS_DRC0>,
 805                                  <&de_clocks CLK_IEP_DRC0>,
 806                                  <&de_clocks CLK_DRAM_DRC0>;
 807                         clock-names = "ahb",
 808                                       "mod",
 809                                       "ram";
 810                         resets = <&de_clocks RST_DRC0>;
 811
 812                         ports {
 813                                 #address-cells = <1>;
 814                                 #size-cells = <0>;
 815
 816                                 drc0_in: port@0 {
 817                                         reg = <0>;
 818
 819                                         drc0_in_be0: endpoint {
 820                                                 remote-endpoint = <&be0_out_drc0>;
 821                                         };
 822                                 };
 823
 824                                 drc0_out: port@1 {
 825                                         reg = <1>;
 826
 827                                         drc0_out_tcon0: endpoint {
 828                                                 remote-endpoint = <&tcon0_in_drc0>;
 829                                         };
 830                                 };
 831                         };
 832                 };
 833
 834                 drc1: drc@3440000 {
 835                         compatible = "allwinner,sun9i-a80-drc";
 836                         reg = <0x03440000 0x40000>;
 837                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 838                         clocks = <&de_clocks CLK_BUS_DRC1>,
 839                                  <&de_clocks CLK_IEP_DRC1>,
 840                                  <&de_clocks CLK_DRAM_DRC1>;
 841                         clock-names = "ahb",
 842                                       "mod",
 843                                       "ram";
 844                         resets = <&de_clocks RST_DRC1>;
 845
 846                         ports {
 847                                 #address-cells = <1>;
 848                                 #size-cells = <0>;
 849
 850                                 drc1_in: port@0 {
 851                                         reg = <0>;
 852
 853                                         drc1_in_be1: endpoint {
 854                                                 remote-endpoint = <&be1_out_drc1>;
 855                                         };
 856                                 };
 857
 858                                 drc1_out: port@1 {
 859                                         reg = <1>;
 860
 861                                         drc1_out_tcon1: endpoint {
 862                                                 remote-endpoint = <&tcon1_in_drc1>;
 863                                         };
 864                                 };
 865                         };
 866                 };
 867
 868                 tcon0: lcd-controller@3c00000 {
 869                         compatible = "allwinner,sun9i-a80-tcon-lcd";
 870                         reg = <0x03c00000 0x10000>;
 871                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 872                         clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;
 873                         clock-names = "ahb", "tcon-ch0";
 874                         resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>;
 875                         reset-names = "lcd", "edp";
 876                         clock-output-names = "tcon0-pixel-clock";
 877                         #clock-cells = <0>;
 878
 879                         ports {
 880                                 #address-cells = <1>;
 881                                 #size-cells = <0>;
 882
 883                                 tcon0_in: port@0 {
 884                                         reg = <0>;
 885
 886                                         tcon0_in_drc0: endpoint {
 887                                                 remote-endpoint = <&drc0_out_tcon0>;
 888                                         };
 889                                 };
 890
 891                                 tcon0_out: port@1 {
 892                                         reg = <1>;
 893                                 };
 894                         };
 895                 };
 896
 897                 tcon1: lcd-controller@3c10000 {
 898                         compatible = "allwinner,sun9i-a80-tcon-tv";
 899                         reg = <0x03c10000 0x10000>;
 900                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 901                         clocks = <&ccu CLK_BUS_LCD1>, <&ccu CLK_LCD1>;
 902                         clock-names = "ahb", "tcon-ch1";
 903                         resets = <&ccu RST_BUS_LCD1>, <&ccu RST_BUS_EDP>;
 904                         reset-names = "lcd", "edp";
 905
 906                         ports {
 907                                 #address-cells = <1>;
 908                                 #size-cells = <0>;
 909
 910                                 tcon1_in: port@0 {
 911                                         reg = <0>;
 912
 913                                         tcon1_in_drc1: endpoint {
 914                                                 remote-endpoint = <&drc1_out_tcon1>;
 915                                         };
 916                                 };
 917
 918                                 tcon1_out: port@1 {
 919                                         reg = <1>;
 920                                 };
 921                         };
 922                 };
 923
 924                 ccu: clock@6000000 {
 925                         compatible = "allwinner,sun9i-a80-ccu";
 926                         reg = <0x06000000 0x800>;
 927                         clocks = <&osc24M>, <&osc32k>;
 928                         clock-names = "hosc", "losc";
 929                         #clock-cells = <1>;
 930                         #reset-cells = <1>;
 931                 };
 932
 933                 timer@6000c00 {
 934                         compatible = "allwinner,sun4i-a10-timer";
 935                         reg = <0x06000c00 0xa0>;
 936                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 937                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 938                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 939                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 940                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 941                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 942
 943                         clocks = <&osc24M>;
 944                 };
 945
 946                 wdt: watchdog@6000ca0 {
 947                         compatible = "allwinner,sun6i-a31-wdt";
 948                         reg = <0x06000ca0 0x20>;
 949                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 950                 };
 951
 952                 pio: pinctrl@6000800 {
 953                         compatible = "allwinner,sun9i-a80-pinctrl";
 954                         reg = <0x06000800 0x400>;
 955                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 956                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 957                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 958                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 959                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 960                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
 961                         clock-names = "apb", "hosc", "losc";
 962                         gpio-controller;
 963                         interrupt-controller;
 964                         #interrupt-cells = <3>;
 965                         #gpio-cells = <3>;
 966
 967                         gmac_rgmii_pins: gmac-rgmii-pins {
 968                                 pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5",
 969                                        "PA7", "PA8", "PA9", "PA10", "PA12",
 970                                        "PA13", "PA15", "PA16", "PA17";
 971                                 function = "gmac";
 972                                 /*
 973                                  * data lines in RGMII mode use DDR mode
 974                                  * and need a higher signal drive strength
 975                                  */
 976                                 drive-strength = <40>;
 977                         };
 978
 979                         i2c3_pins: i2c3-pins {
 980                                 pins = "PG10", "PG11";
 981                                 function = "i2c3";
 982                         };
 983
 984                         lcd0_rgb888_pins: lcd0-rgb888-pins {
 985                                 pins = "PD0", "PD1", "PD2", "PD3",
 986                                        "PD4", "PD5", "PD6", "PD7",
 987                                        "PD8", "PD9", "PD10", "PD11",
 988                                        "PD12", "PD13", "PD14", "PD15",
 989                                        "PD16", "PD17", "PD18", "PD19",
 990                                        "PD20", "PD21", "PD22", "PD23",
 991                                        "PD24", "PD25", "PD26", "PD27";
 992                                 function = "lcd0";
 993                         };
 994
 995                         mmc0_pins: mmc0-pins {
 996                                 pins = "PF0", "PF1" ,"PF2", "PF3",
 997                                        "PF4", "PF5";
 998                                 function = "mmc0";
 999                                 drive-strength = <30>;
1000                                 bias-pull-up;
1001                         };
1002
1003                         mmc1_pins: mmc1-pins {
1004                                 pins = "PG0", "PG1" ,"PG2", "PG3",
1005                                                  "PG4", "PG5";
1006                                 function = "mmc1";
1007                                 drive-strength = <30>;
1008                                 bias-pull-up;
1009                         };
1010
1011                         mmc2_8bit_pins: mmc2-8bit-pins {
1012                                 pins = "PC6", "PC7", "PC8", "PC9",
1013                                        "PC10", "PC11", "PC12",
1014                                        "PC13", "PC14", "PC15",
1015                                        "PC16";
1016                                 function = "mmc2";
1017                                 drive-strength = <30>;
1018                                 bias-pull-up;
1019                         };
1020
1021                         uart0_ph_pins: uart0-ph-pins {
1022                                 pins = "PH12", "PH13";
1023                                 function = "uart0";
1024                         };
1025
1026                         uart4_pins: uart4-pins {
1027                                 pins = "PG12", "PG13", "PG14", "PG15";
1028                                 function = "uart4";
1029                         };
1030                 };
1031
1032                 uart0: serial@7000000 {
1033                         compatible = "snps,dw-apb-uart";
1034                         reg = <0x07000000 0x400>;
1035                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
1036                         reg-shift = <2>;
1037                         reg-io-width = <4>;
1038                         clocks = <&ccu CLK_BUS_UART0>;
1039                         resets = <&ccu RST_BUS_UART0>;
1040                         status = "disabled";
1041                 };
1042
1043                 uart1: serial@7000400 {
1044                         compatible = "snps,dw-apb-uart";
1045                         reg = <0x07000400 0x400>;
1046                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1047                         reg-shift = <2>;
1048                         reg-io-width = <4>;
1049                         clocks = <&ccu CLK_BUS_UART1>;
1050                         resets = <&ccu RST_BUS_UART1>;
1051                         status = "disabled";
1052                 };
1053
1054                 uart2: serial@7000800 {
1055                         compatible = "snps,dw-apb-uart";
1056                         reg = <0x07000800 0x400>;
1057                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1058                         reg-shift = <2>;
1059                         reg-io-width = <4>;
1060                         clocks = <&ccu CLK_BUS_UART2>;
1061                         resets = <&ccu RST_BUS_UART2>;
1062                         status = "disabled";
1063                 };
1064
1065                 uart3: serial@7000c00 {
1066                         compatible = "snps,dw-apb-uart";
1067                         reg = <0x07000c00 0x400>;
1068                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1069                         reg-shift = <2>;
1070                         reg-io-width = <4>;
1071                         clocks = <&ccu CLK_BUS_UART3>;
1072                         resets = <&ccu RST_BUS_UART3>;
1073                         status = "disabled";
1074                 };
1075
1076                 uart4: serial@7001000 {
1077                         compatible = "snps,dw-apb-uart";
1078                         reg = <0x07001000 0x400>;
1079                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1080                         reg-shift = <2>;
1081                         reg-io-width = <4>;
1082                         clocks = <&ccu CLK_BUS_UART4>;
1083                         resets = <&ccu RST_BUS_UART4>;
1084                         status = "disabled";
1085                 };
1086
1087                 uart5: serial@7001400 {
1088                         compatible = "snps,dw-apb-uart";
1089                         reg = <0x07001400 0x400>;
1090                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1091                         reg-shift = <2>;
1092                         reg-io-width = <4>;
1093                         clocks = <&ccu CLK_BUS_UART5>;
1094                         resets = <&ccu RST_BUS_UART5>;
1095                         status = "disabled";
1096                 };
1097
1098                 i2c0: i2c@7002800 {
1099                         compatible = "allwinner,sun6i-a31-i2c";
1100                         reg = <0x07002800 0x400>;
1101                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1102                         clocks = <&ccu CLK_BUS_I2C0>;
1103                         resets = <&ccu RST_BUS_I2C0>;
1104                         status = "disabled";
1105                         #address-cells = <1>;
1106                         #size-cells = <0>;
1107                 };
1108
1109                 i2c1: i2c@7002c00 {
1110                         compatible = "allwinner,sun6i-a31-i2c";
1111                         reg = <0x07002c00 0x400>;
1112                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1113                         clocks = <&ccu CLK_BUS_I2C1>;
1114                         resets = <&ccu RST_BUS_I2C1>;
1115                         status = "disabled";
1116                         #address-cells = <1>;
1117                         #size-cells = <0>;
1118                 };
1119
1120                 i2c2: i2c@7003000 {
1121                         compatible = "allwinner,sun6i-a31-i2c";
1122                         reg = <0x07003000 0x400>;
1123                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1124                         clocks = <&ccu CLK_BUS_I2C2>;
1125                         resets = <&ccu RST_BUS_I2C2>;
1126                         status = "disabled";
1127                         #address-cells = <1>;
1128                         #size-cells = <0>;
1129                 };
1130
1131                 i2c3: i2c@7003400 {
1132                         compatible = "allwinner,sun6i-a31-i2c";
1133                         reg = <0x07003400 0x400>;
1134                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1135                         clocks = <&ccu CLK_BUS_I2C3>;
1136                         resets = <&ccu RST_BUS_I2C3>;
1137                         status = "disabled";
1138                         #address-cells = <1>;
1139                         #size-cells = <0>;
1140                 };
1141
1142                 i2c4: i2c@7003800 {
1143                         compatible = "allwinner,sun6i-a31-i2c";
1144                         reg = <0x07003800 0x400>;
1145                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1146                         clocks = <&ccu CLK_BUS_I2C4>;
1147                         resets = <&ccu RST_BUS_I2C4>;
1148                         status = "disabled";
1149                         #address-cells = <1>;
1150                         #size-cells = <0>;
1151                 };
1152
1153                 r_wdt: watchdog@8001000 {
1154                         compatible = "allwinner,sun6i-a31-wdt";
1155                         reg = <0x08001000 0x20>;
1156                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1157                 };
1158
1159                 prcm@8001400 {
1160                         compatible = "allwinner,sun9i-a80-prcm";
1161                         reg = <0x08001400 0x200>;
1162                 };
1163
1164                 apbs_rst: reset@80014b0 {
1165                         reg = <0x080014b0 0x4>;
1166                         compatible = "allwinner,sun6i-a31-clock-reset";
1167                         #reset-cells = <1>;
1168                 };
1169
1170                 nmi_intc: interrupt-controller@80015a0 {
1171                         compatible = "allwinner,sun9i-a80-nmi";
1172                         interrupt-controller;
1173                         #interrupt-cells = <2>;
1174                         reg = <0x080015a0 0xc>;
1175                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1176                 };
1177
1178                 r_ir: ir@8002000 {
1179                         compatible = "allwinner,sun6i-a31-ir";
1180                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1181                         pinctrl-names = "default";
1182                         pinctrl-0 = <&r_ir_pins>;
1183                         clocks = <&apbs_gates 1>, <&r_ir_clk>;
1184                         clock-names = "apb", "ir";
1185                         resets = <&apbs_rst 1>;
1186                         reg = <0x08002000 0x40>;
1187                         status = "disabled";
1188                 };
1189
1190                 r_uart: serial@8002800 {
1191                         compatible = "snps,dw-apb-uart";
1192                         reg = <0x08002800 0x400>;
1193                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1194                         reg-shift = <2>;
1195                         reg-io-width = <4>;
1196                         clocks = <&apbs_gates 4>;
1197                         resets = <&apbs_rst 4>;
1198                         status = "disabled";
1199                 };
1200
1201                 r_pio: pinctrl@8002c00 {
1202                         compatible = "allwinner,sun9i-a80-r-pinctrl";
1203                         reg = <0x08002c00 0x400>;
1204                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1205                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1206                         clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
1207                         clock-names = "apb", "hosc", "losc";
1208                         resets = <&apbs_rst 0>;
1209                         gpio-controller;
1210                         interrupt-controller;
1211                         #interrupt-cells = <3>;
1212                         #gpio-cells = <3>;
1213
1214                         r_ir_pins: r-ir-pins {
1215                                 pins = "PL6";
1216                                 function = "s_cir_rx";
1217                         };
1218
1219                         r_rsb_pins: r-rsb-pins {
1220                                 pins = "PN0", "PN1";
1221                                 function = "s_rsb";
1222                                 drive-strength = <20>;
1223                                 bias-pull-up;
1224                         };
1225                 };
1226
1227                 r_rsb: rsb@8003400 {
1228                         compatible = "allwinner,sun8i-a23-rsb";
1229                         reg = <0x08003400 0x400>;
1230                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1231                         clocks = <&apbs_gates 3>;
1232                         clock-frequency = <3000000>;
1233                         resets = <&apbs_rst 3>;
1234                         pinctrl-names = "default";
1235                         pinctrl-0 = <&r_rsb_pins>;
1236                         status = "disabled";
1237                         #address-cells = <1>;
1238                         #size-cells = <0>;
1239                 };
1240         };
1241 };