src/arm/uniphier-sld8.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Device Tree Source for UniPhier sLD8 SoC
   4 //
   5 // Copyright (C) 2015-2016 Socionext Inc.
   6 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   7
   8 #include <dt-bindings/gpio/uniphier-gpio.h>
   9
  10 / {
  11         compatible = "socionext,uniphier-sld8";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         enable-method = "psci";
  24                         next-level-cache = <&l2>;
  25                 };
  26         };
  27
  28         psci {
  29                 compatible = "arm,psci-0.2";
  30                 method = "smc";
  31         };
  32
  33         clocks {
  34                 refclk: ref {
  35                         compatible = "fixed-clock";
  36                         #clock-cells = <0>;
  37                         clock-frequency = <25000000>;
  38                 };
  39
  40                 arm_timer_clk: arm-timer {
  41                         #clock-cells = <0>;
  42                         compatible = "fixed-clock";
  43                         clock-frequency = <50000000>;
  44                 };
  45         };
  46
  47         soc {
  48                 compatible = "simple-bus";
  49                 #address-cells = <1>;
  50                 #size-cells = <1>;
  51                 ranges;
  52                 interrupt-parent = <&intc>;
  53
  54                 l2: cache-controller@500c0000 {
  55                         compatible = "socionext,uniphier-system-cache";
  56                         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
  57                               <0x506c0000 0x400>;
  58                         interrupts = <0 174 4>, <0 175 4>;
  59                         cache-unified;
  60                         cache-size = <(256 * 1024)>;
  61                         cache-sets = <256>;
  62                         cache-line-size = <128>;
  63                         cache-level = <2>;
  64                 };
  65
  66                 spi: spi@54006000 {
  67                         compatible = "socionext,uniphier-scssi";
  68                         status = "disabled";
  69                         reg = <0x54006000 0x100>;
  70                         #address-cells = <1>;
  71                         #size-cells = <0>;
  72                         interrupts = <0 39 4>;
  73                         pinctrl-names = "default";
  74                         pinctrl-0 = <&pinctrl_spi0>;
  75                         clocks = <&peri_clk 11>;
  76                         resets = <&peri_rst 11>;
  77                 };
  78
  79                 serial0: serial@54006800 {
  80                         compatible = "socionext,uniphier-uart";
  81                         status = "disabled";
  82                         reg = <0x54006800 0x40>;
  83                         interrupts = <0 33 4>;
  84                         pinctrl-names = "default";
  85                         pinctrl-0 = <&pinctrl_uart0>;
  86                         clocks = <&peri_clk 0>;
  87                         resets = <&peri_rst 0>;
  88                 };
  89
  90                 serial1: serial@54006900 {
  91                         compatible = "socionext,uniphier-uart";
  92                         status = "disabled";
  93                         reg = <0x54006900 0x40>;
  94                         interrupts = <0 35 4>;
  95                         pinctrl-names = "default";
  96                         pinctrl-0 = <&pinctrl_uart1>;
  97                         clocks = <&peri_clk 1>;
  98                         resets = <&peri_rst 1>;
  99                 };
 100
 101                 serial2: serial@54006a00 {
 102                         compatible = "socionext,uniphier-uart";
 103                         status = "disabled";
 104                         reg = <0x54006a00 0x40>;
 105                         interrupts = <0 37 4>;
 106                         pinctrl-names = "default";
 107                         pinctrl-0 = <&pinctrl_uart2>;
 108                         clocks = <&peri_clk 2>;
 109                         resets = <&peri_rst 2>;
 110                 };
 111
 112                 serial3: serial@54006b00 {
 113                         compatible = "socionext,uniphier-uart";
 114                         status = "disabled";
 115                         reg = <0x54006b00 0x40>;
 116                         interrupts = <0 29 4>;
 117                         pinctrl-names = "default";
 118                         pinctrl-0 = <&pinctrl_uart3>;
 119                         clocks = <&peri_clk 3>;
 120                         resets = <&peri_rst 3>;
 121                 };
 122
 123                 gpio: gpio@55000000 {
 124                         compatible = "socionext,uniphier-gpio";
 125                         reg = <0x55000000 0x200>;
 126                         interrupt-parent = <&aidet>;
 127                         interrupt-controller;
 128                         #interrupt-cells = <2>;
 129                         gpio-controller;
 130                         #gpio-cells = <2>;
 131                         gpio-ranges = <&pinctrl 0 0 0>,
 132                                       <&pinctrl 104 0 0>,
 133                                       <&pinctrl 112 0 0>;
 134                         gpio-ranges-group-names = "gpio_range0",
 135                                                   "gpio_range1",
 136                                                   "gpio_range2";
 137                         ngpios = <136>;
 138                         socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
 139                 };
 140
 141                 i2c0: i2c@58400000 {
 142                         compatible = "socionext,uniphier-i2c";
 143                         status = "disabled";
 144                         reg = <0x58400000 0x40>;
 145                         #address-cells = <1>;
 146                         #size-cells = <0>;
 147                         interrupts = <0 41 1>;
 148                         pinctrl-names = "default";
 149                         pinctrl-0 = <&pinctrl_i2c0>;
 150                         clocks = <&peri_clk 4>;
 151                         resets = <&peri_rst 4>;
 152                         clock-frequency = <100000>;
 153                 };
 154
 155                 i2c1: i2c@58480000 {
 156                         compatible = "socionext,uniphier-i2c";
 157                         status = "disabled";
 158                         reg = <0x58480000 0x40>;
 159                         #address-cells = <1>;
 160                         #size-cells = <0>;
 161                         interrupts = <0 42 1>;
 162                         pinctrl-names = "default";
 163                         pinctrl-0 = <&pinctrl_i2c1>;
 164                         clocks = <&peri_clk 5>;
 165                         resets = <&peri_rst 5>;
 166                         clock-frequency = <100000>;
 167                 };
 168
 169                 /* chip-internal connection for DMD */
 170                 i2c2: i2c@58500000 {
 171                         compatible = "socionext,uniphier-i2c";
 172                         reg = <0x58500000 0x40>;
 173                         #address-cells = <1>;
 174                         #size-cells = <0>;
 175                         interrupts = <0 43 1>;
 176                         pinctrl-names = "default";
 177                         pinctrl-0 = <&pinctrl_i2c2>;
 178                         clocks = <&peri_clk 6>;
 179                         resets = <&peri_rst 6>;
 180                         clock-frequency = <400000>;
 181                 };
 182
 183                 i2c3: i2c@58580000 {
 184                         compatible = "socionext,uniphier-i2c";
 185                         status = "disabled";
 186                         reg = <0x58580000 0x40>;
 187                         #address-cells = <1>;
 188                         #size-cells = <0>;
 189                         interrupts = <0 44 1>;
 190                         pinctrl-names = "default";
 191                         pinctrl-0 = <&pinctrl_i2c3>;
 192                         clocks = <&peri_clk 7>;
 193                         resets = <&peri_rst 7>;
 194                         clock-frequency = <100000>;
 195                 };
 196
 197                 system_bus: system-bus@58c00000 {
 198                         compatible = "socionext,uniphier-system-bus";
 199                         status = "disabled";
 200                         reg = <0x58c00000 0x400>;
 201                         #address-cells = <2>;
 202                         #size-cells = <1>;
 203                         pinctrl-names = "default";
 204                         pinctrl-0 = <&pinctrl_system_bus>;
 205                 };
 206
 207                 smpctrl@59801000 {
 208                         compatible = "socionext,uniphier-smpctrl";
 209                         reg = <0x59801000 0x400>;
 210                 };
 211
 212                 mioctrl@59810000 {
 213                         compatible = "socionext,uniphier-sld8-mioctrl",
 214                                      "simple-mfd", "syscon";
 215                         reg = <0x59810000 0x800>;
 216
 217                         mio_clk: clock {
 218                                 compatible = "socionext,uniphier-sld8-mio-clock";
 219                                 #clock-cells = <1>;
 220                         };
 221
 222                         mio_rst: reset {
 223                                 compatible = "socionext,uniphier-sld8-mio-reset";
 224                                 #reset-cells = <1>;
 225                         };
 226                 };
 227
 228                 perictrl@59820000 {
 229                         compatible = "socionext,uniphier-sld8-perictrl",
 230                                      "simple-mfd", "syscon";
 231                         reg = <0x59820000 0x200>;
 232
 233                         peri_clk: clock {
 234                                 compatible = "socionext,uniphier-sld8-peri-clock";
 235                                 #clock-cells = <1>;
 236                         };
 237
 238                         peri_rst: reset {
 239                                 compatible = "socionext,uniphier-sld8-peri-reset";
 240                                 #reset-cells = <1>;
 241                         };
 242                 };
 243
 244                 dmac: dma-controller@5a000000 {
 245                         compatible = "socionext,uniphier-mio-dmac";
 246                         reg = <0x5a000000 0x1000>;
 247                         interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
 248                                      <0 71 4>, <0 72 4>, <0 73 4>;
 249                         clocks = <&mio_clk 7>;
 250                         resets = <&mio_rst 7>;
 251                         #dma-cells = <1>;
 252                 };
 253
 254                 sd: mmc@5a400000 {
 255                         compatible = "socionext,uniphier-sd-v2.91";
 256                         status = "disabled";
 257                         reg = <0x5a400000 0x200>;
 258                         interrupts = <0 76 4>;
 259                         pinctrl-names = "default", "uhs";
 260                         pinctrl-0 = <&pinctrl_sd>;
 261                         pinctrl-1 = <&pinctrl_sd_uhs>;
 262                         clocks = <&mio_clk 0>;
 263                         reset-names = "host", "bridge";
 264                         resets = <&mio_rst 0>, <&mio_rst 3>;
 265                         dma-names = "rx-tx";
 266                         dmas = <&dmac 4>;
 267                         bus-width = <4>;
 268                         cap-sd-highspeed;
 269                         sd-uhs-sdr12;
 270                         sd-uhs-sdr25;
 271                         sd-uhs-sdr50;
 272                 };
 273
 274                 emmc: mmc@5a500000 {
 275                         compatible = "socionext,uniphier-sd-v2.91";
 276                         status = "disabled";
 277                         reg = <0x5a500000 0x200>;
 278                         interrupts = <0 78 4>;
 279                         pinctrl-names = "default";
 280                         pinctrl-0 = <&pinctrl_emmc>;
 281                         clocks = <&mio_clk 1>;
 282                         reset-names = "host", "bridge", "hw";
 283                         resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
 284                         dma-names = "rx-tx";
 285                         dmas = <&dmac 6>;
 286                         bus-width = <8>;
 287                         cap-mmc-highspeed;
 288                         cap-mmc-hw-reset;
 289                         non-removable;
 290                 };
 291
 292                 usb0: usb@5a800100 {
 293                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 294                         status = "disabled";
 295                         reg = <0x5a800100 0x100>;
 296                         interrupts = <0 80 4>;
 297                         pinctrl-names = "default";
 298                         pinctrl-0 = <&pinctrl_usb0>;
 299                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
 300                                  <&mio_clk 12>;
 301                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 302                                  <&mio_rst 12>;
 303                         has-transaction-translator;
 304                 };
 305
 306                 usb1: usb@5a810100 {
 307                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 308                         status = "disabled";
 309                         reg = <0x5a810100 0x100>;
 310                         interrupts = <0 81 4>;
 311                         pinctrl-names = "default";
 312                         pinctrl-0 = <&pinctrl_usb1>;
 313                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
 314                                  <&mio_clk 13>;
 315                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 316                                  <&mio_rst 13>;
 317                         has-transaction-translator;
 318                 };
 319
 320                 usb2: usb@5a820100 {
 321                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 322                         status = "disabled";
 323                         reg = <0x5a820100 0x100>;
 324                         interrupts = <0 82 4>;
 325                         pinctrl-names = "default";
 326                         pinctrl-0 = <&pinctrl_usb2>;
 327                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
 328                                  <&mio_clk 14>;
 329                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
 330                                  <&mio_rst 14>;
 331                         has-transaction-translator;
 332                 };
 333
 334                 soc-glue@5f800000 {
 335                         compatible = "socionext,uniphier-sld8-soc-glue",
 336                                      "simple-mfd", "syscon";
 337                         reg = <0x5f800000 0x2000>;
 338
 339                         pinctrl: pinctrl {
 340                                 compatible = "socionext,uniphier-sld8-pinctrl";
 341                         };
 342                 };
 343
 344                 soc-glue@5f900000 {
 345                         compatible = "socionext,uniphier-sld8-soc-glue-debug",
 346                                      "simple-mfd";
 347                         #address-cells = <1>;
 348                         #size-cells = <1>;
 349                         ranges = <0 0x5f900000 0x2000>;
 350
 351                         efuse@100 {
 352                                 compatible = "socionext,uniphier-efuse";
 353                                 reg = <0x100 0x28>;
 354                         };
 355
 356                         efuse@200 {
 357                                 compatible = "socionext,uniphier-efuse";
 358                                 reg = <0x200 0x14>;
 359                         };
 360                 };
 361
 362                 timer@60000200 {
 363                         compatible = "arm,cortex-a9-global-timer";
 364                         reg = <0x60000200 0x20>;
 365                         interrupts = <1 11 0x104>;
 366                         clocks = <&arm_timer_clk>;
 367                 };
 368
 369                 timer@60000600 {
 370                         compatible = "arm,cortex-a9-twd-timer";
 371                         reg = <0x60000600 0x20>;
 372                         interrupts = <1 13 0x104>;
 373                         clocks = <&arm_timer_clk>;
 374                 };
 375
 376                 intc: interrupt-controller@60001000 {
 377                         compatible = "arm,cortex-a9-gic";
 378                         reg = <0x60001000 0x1000>,
 379                               <0x60000100 0x100>;
 380                         #interrupt-cells = <3>;
 381                         interrupt-controller;
 382                 };
 383
 384                 aidet: interrupt-controller@61830000 {
 385                         compatible = "socionext,uniphier-sld8-aidet";
 386                         reg = <0x61830000 0x200>;
 387                         interrupt-controller;
 388                         #interrupt-cells = <2>;
 389                 };
 390
 391                 sysctrl@61840000 {
 392                         compatible = "socionext,uniphier-sld8-sysctrl",
 393                                      "simple-mfd", "syscon";
 394                         reg = <0x61840000 0x10000>;
 395
 396                         sys_clk: clock {
 397                                 compatible = "socionext,uniphier-sld8-clock";
 398                                 #clock-cells = <1>;
 399                         };
 400
 401                         sys_rst: reset {
 402                                 compatible = "socionext,uniphier-sld8-reset";
 403                                 #reset-cells = <1>;
 404                         };
 405                 };
 406
 407                 nand: nand-controller@68000000 {
 408                         compatible = "socionext,uniphier-denali-nand-v5a";
 409                         status = "disabled";
 410                         reg-names = "nand_data", "denali_reg";
 411                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 412                         #address-cells = <1>;
 413                         #size-cells = <0>;
 414                         interrupts = <0 65 4>;
 415                         pinctrl-names = "default";
 416                         pinctrl-0 = <&pinctrl_nand>;
 417                         clock-names = "nand", "nand_x", "ecc";
 418                         clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
 419                         reset-names = "nand", "reg";
 420                         resets = <&sys_rst 2>, <&sys_rst 2>;
 421                 };
 422         };
 423 };
 424
 425 #include "uniphier-pinctrl.dtsi"