src/arm64/amlogic/meson-gxbb.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2016 Andreas Färber
   4  */
   5
   6 #include "meson-gx.dtsi"
   7 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
   8 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
   9 #include <dt-bindings/clock/gxbb-clkc.h>
  10 #include <dt-bindings/clock/gxbb-aoclkc.h>
  11 #include <dt-bindings/reset/gxbb-aoclkc.h>
  12
  13 / {
  14         compatible = "amlogic,meson-gxbb";
  15
  16         soc {
  17                 usb0_phy: phy@c0000000 {
  18                         compatible = "amlogic,meson-gxbb-usb2-phy";
  19                         #phy-cells = <0>;
  20                         reg = <0x0 0xc0000000 0x0 0x20>;
  21                         resets = <&reset RESET_USB_OTG>;
  22                         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
  23                         clock-names = "usb_general", "usb";
  24                         status = "disabled";
  25                 };
  26
  27                 usb1_phy: phy@c0000020 {
  28                         compatible = "amlogic,meson-gxbb-usb2-phy";
  29                         #phy-cells = <0>;
  30                         reg = <0x0 0xc0000020 0x0 0x20>;
  31                         resets = <&reset RESET_USB_OTG>;
  32                         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
  33                         clock-names = "usb_general", "usb";
  34                         status = "disabled";
  35                 };
  36
  37                 usb0: usb@c9000000 {
  38                         compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
  39                         reg = <0x0 0xc9000000 0x0 0x40000>;
  40                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  41                         clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
  42                         clock-names = "otg";
  43                         phys = <&usb0_phy>;
  44                         phy-names = "usb2-phy";
  45                         dr_mode = "host";
  46                         status = "disabled";
  47                 };
  48
  49                 usb1: usb@c9100000 {
  50                         compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
  51                         reg = <0x0 0xc9100000 0x0 0x40000>;
  52                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  53                         clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
  54                         clock-names = "otg";
  55                         phys = <&usb1_phy>;
  56                         phy-names = "usb2-phy";
  57                         dr_mode = "host";
  58                         status = "disabled";
  59                 };
  60         };
  61 };
  62
  63 &aiu {
  64         compatible = "amlogic,aiu-gxbb", "amlogic,aiu";
  65         clocks = <&clkc CLKID_AIU_GLUE>,
  66                  <&clkc CLKID_I2S_OUT>,
  67                  <&clkc CLKID_AOCLK_GATE>,
  68                  <&clkc CLKID_CTS_AMCLK>,
  69                  <&clkc CLKID_MIXER_IFACE>,
  70                  <&clkc CLKID_IEC958>,
  71                  <&clkc CLKID_IEC958_GATE>,
  72                  <&clkc CLKID_CTS_MCLK_I958>,
  73                  <&clkc CLKID_CTS_I958>;
  74         clock-names = "pclk",
  75                       "i2s_pclk",
  76                       "i2s_aoclk",
  77                       "i2s_mclk",
  78                       "i2s_mixer",
  79                       "spdif_pclk",
  80                       "spdif_aoclk",
  81                       "spdif_mclk",
  82                       "spdif_mclk_sel";
  83         resets = <&reset RESET_AIU>;
  84 };
  85
  86 &aobus {
  87         pinctrl_aobus: pinctrl@14 {
  88                 compatible = "amlogic,meson-gxbb-aobus-pinctrl";
  89                 #address-cells = <2>;
  90                 #size-cells = <2>;
  91                 ranges;
  92
  93                 gpio_ao: bank@14 {
  94                         reg = <0x0 0x00014 0x0 0x8>,
  95                               <0x0 0x0002c 0x0 0x4>,
  96                               <0x0 0x00024 0x0 0x8>;
  97                         reg-names = "mux", "pull", "gpio";
  98                         gpio-controller;
  99                         #gpio-cells = <2>;
 100                         gpio-ranges = <&pinctrl_aobus 0 0 14>;
 101                 };
 102
 103                 uart_ao_a_pins: uart_ao_a {
 104                         mux {
 105                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
 106                                 function = "uart_ao";
 107                                 bias-disable;
 108                         };
 109                 };
 110
 111                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
 112                         mux {
 113                                 groups = "uart_cts_ao_a",
 114                                        "uart_rts_ao_a";
 115                                 function = "uart_ao";
 116                                 bias-disable;
 117                         };
 118                 };
 119
 120                 uart_ao_b_pins: uart_ao_b {
 121                         mux {
 122                                 groups = "uart_tx_ao_b", "uart_rx_ao_b";
 123                                 function = "uart_ao_b";
 124                                 bias-disable;
 125                         };
 126                 };
 127
 128                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
 129                         mux {
 130                                 groups = "uart_cts_ao_b",
 131                                        "uart_rts_ao_b";
 132                                 function = "uart_ao_b";
 133                                 bias-disable;
 134                         };
 135                 };
 136
 137                 remote_input_ao_pins: remote_input_ao {
 138                         mux {
 139                                 groups = "remote_input_ao";
 140                                 function = "remote_input_ao";
 141                                 bias-disable;
 142                         };
 143                 };
 144
 145                 i2c_ao_pins: i2c_ao {
 146                         mux {
 147                                 groups = "i2c_sck_ao",
 148                                        "i2c_sda_ao";
 149                                 function = "i2c_ao";
 150                                 bias-disable;
 151                         };
 152                 };
 153
 154                 pwm_ao_a_3_pins: pwm_ao_a_3 {
 155                         mux {
 156                                 groups = "pwm_ao_a_3";
 157                                 function = "pwm_ao_a_3";
 158                                 bias-disable;
 159                         };
 160                 };
 161
 162                 pwm_ao_a_6_pins: pwm_ao_a_6 {
 163                         mux {
 164                                 groups = "pwm_ao_a_6";
 165                                 function = "pwm_ao_a_6";
 166                                 bias-disable;
 167                         };
 168                 };
 169
 170                 pwm_ao_a_12_pins: pwm_ao_a_12 {
 171                         mux {
 172                                 groups = "pwm_ao_a_12";
 173                                 function = "pwm_ao_a_12";
 174                                 bias-disable;
 175                         };
 176                 };
 177
 178                 pwm_ao_b_pins: pwm_ao_b {
 179                         mux {
 180                                 groups = "pwm_ao_b";
 181                                 function = "pwm_ao_b";
 182                                 bias-disable;
 183                         };
 184                 };
 185
 186                 i2s_am_clk_pins: i2s_am_clk {
 187                         mux {
 188                                 groups = "i2s_am_clk";
 189                                 function = "i2s_out_ao";
 190                                 bias-disable;
 191                         };
 192                 };
 193
 194                 i2s_out_ao_clk_pins: i2s_out_ao_clk {
 195                         mux {
 196                                 groups = "i2s_out_ao_clk";
 197                                 function = "i2s_out_ao";
 198                                 bias-disable;
 199                         };
 200                 };
 201
 202                 i2s_out_lr_clk_pins: i2s_out_lr_clk {
 203                         mux {
 204                                 groups = "i2s_out_lr_clk";
 205                                 function = "i2s_out_ao";
 206                                 bias-disable;
 207                         };
 208                 };
 209
 210                 i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
 211                         mux {
 212                                 groups = "i2s_out_ch01_ao";
 213                                 function = "i2s_out_ao";
 214                                 bias-disable;
 215                         };
 216                 };
 217
 218                 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
 219                         mux {
 220                                 groups = "i2s_out_ch23_ao";
 221                                 function = "i2s_out_ao";
 222                                 bias-disable;
 223                         };
 224                 };
 225
 226                 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
 227                         mux {
 228                                 groups = "i2s_out_ch45_ao";
 229                                 function = "i2s_out_ao";
 230                                 bias-disable;
 231                         };
 232                 };
 233
 234                 spdif_out_ao_6_pins: spdif_out_ao_6 {
 235                         mux {
 236                                 groups = "spdif_out_ao_6";
 237                                 function = "spdif_out_ao";
 238                         };
 239                 };
 240
 241                 spdif_out_ao_13_pins: spdif_out_ao_13 {
 242                         mux {
 243                                 groups = "spdif_out_ao_13";
 244                                 function = "spdif_out_ao";
 245                                 bias-disable;
 246                         };
 247                 };
 248
 249                 ao_cec_pins: ao_cec {
 250                         mux {
 251                                 groups = "ao_cec";
 252                                 function = "cec_ao";
 253                                 bias-disable;
 254                         };
 255                 };
 256
 257                 ee_cec_pins: ee_cec {
 258                         mux {
 259                                 groups = "ee_cec";
 260                                 function = "cec_ao";
 261                                 bias-disable;
 262                         };
 263                 };
 264         };
 265 };
 266
 267 &apb {
 268         mali: gpu@c0000 {
 269                 compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
 270                 reg = <0x0 0xc0000 0x0 0x40000>;
 271                 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 272                              <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 273                              <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
 274                              <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 275                              <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
 276                              <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 277                              <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
 278                              <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
 279                              <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 280                              <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 281                 interrupt-names = "gp", "gpmmu", "pp", "pmu",
 282                         "pp0", "ppmmu0", "pp1", "ppmmu1",
 283                         "pp2", "ppmmu2";
 284                 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
 285                 clock-names = "bus", "core";
 286
 287                 /*
 288                  * Mali clocking is provided by two identical clock paths
 289                  * MALI_0 and MALI_1 muxed to a single clock by a glitch
 290                  * free mux to safely change frequency while running.
 291                  */
 292                 assigned-clocks = <&clkc CLKID_GP0_PLL>,
 293                                   <&clkc CLKID_MALI_0_SEL>,
 294                                   <&clkc CLKID_MALI_0>,
 295                                   <&clkc CLKID_MALI>; /* Glitch free mux */
 296                 assigned-clock-parents = <0>, /* Do Nothing */
 297                                          <&clkc CLKID_GP0_PLL>,
 298                                          <0>, /* Do Nothing */
 299                                          <&clkc CLKID_MALI_0>;
 300                 assigned-clock-rates = <744000000>,
 301                                        <0>, /* Do Nothing */
 302                                        <744000000>,
 303                                        <0>; /* Do Nothing */
 304         };
 305 };
 306
 307 &cbus {
 308         spifc: spi@8c80 {
 309                 compatible = "amlogic,meson-gxbb-spifc";
 310                 reg = <0x0 0x08c80 0x0 0x80>;
 311                 #address-cells = <1>;
 312                 #size-cells = <0>;
 313                 clocks = <&clkc CLKID_SPI>;
 314                 status = "disabled";
 315         };
 316 };
 317
 318 &cec_AO {
 319         clocks = <&clkc_AO CLKID_AO_CEC_32K>;
 320         clock-names = "core";
 321 };
 322
 323 &clkc_AO {
 324         compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
 325         clocks = <&xtal>, <&clkc CLKID_CLK81>;
 326         clock-names = "xtal", "mpeg-clk";
 327 };
 328
 329 &efuse {
 330         clocks = <&clkc CLKID_EFUSE>;
 331 };
 332
 333 &ethmac {
 334         clocks = <&clkc CLKID_ETH>,
 335                  <&clkc CLKID_FCLK_DIV2>,
 336                  <&clkc CLKID_MPLL2>;
 337         clock-names = "stmmaceth", "clkin0", "clkin1";
 338 };
 339
 340 &gpio_intc {
 341         compatible = "amlogic,meson-gpio-intc",
 342                      "amlogic,meson-gxbb-gpio-intc";
 343         status = "okay";
 344 };
 345
 346 &hdmi_tx {
 347         compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
 348         resets = <&reset RESET_HDMITX_CAPB3>,
 349                  <&reset RESET_HDMI_SYSTEM_RESET>,
 350                  <&reset RESET_HDMI_TX>;
 351         reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
 352         clocks = <&clkc CLKID_HDMI_PCLK>,
 353                  <&clkc CLKID_CLK81>,
 354                  <&clkc CLKID_GCLK_VENCI_INT0>;
 355         clock-names = "isfr", "iahb", "venci";
 356 };
 357
 358 &sysctrl {
 359         clkc: clock-controller {
 360                 compatible = "amlogic,gxbb-clkc";
 361                 #clock-cells = <1>;
 362                 clocks = <&xtal>;
 363                 clock-names = "xtal";
 364         };
 365 };
 366
 367 &hwrng {
 368         clocks = <&clkc CLKID_RNG0>;
 369         clock-names = "core";
 370 };
 371
 372 &i2c_A {
 373         clocks = <&clkc CLKID_I2C>;
 374 };
 375
 376 &i2c_AO {
 377         clocks = <&clkc CLKID_AO_I2C>;
 378 };
 379
 380 &i2c_B {
 381         clocks = <&clkc CLKID_I2C>;
 382 };
 383
 384 &i2c_C {
 385         clocks = <&clkc CLKID_I2C>;
 386 };
 387
 388 &periphs {
 389         pinctrl_periphs: pinctrl@4b0 {
 390                 compatible = "amlogic,meson-gxbb-periphs-pinctrl";
 391                 #address-cells = <2>;
 392                 #size-cells = <2>;
 393                 ranges;
 394
 395                 gpio: bank@4b0 {
 396                         reg = <0x0 0x004b0 0x0 0x28>,
 397                               <0x0 0x004e8 0x0 0x14>,
 398                               <0x0 0x00520 0x0 0x14>,
 399                               <0x0 0x00430 0x0 0x40>;
 400                         reg-names = "mux", "pull", "pull-enable", "gpio";
 401                         gpio-controller;
 402                         #gpio-cells = <2>;
 403                         gpio-ranges = <&pinctrl_periphs 0 0 119>;
 404                 };
 405
 406                 emmc_pins: emmc {
 407                         mux-0 {
 408                                 groups = "emmc_nand_d07",
 409                                        "emmc_cmd";
 410                                 function = "emmc";
 411                                 bias-pull-up;
 412                         };
 413
 414                         mux-1 {
 415                                 groups = "emmc_clk";
 416                                 function = "emmc";
 417                                 bias-disable;
 418                         };
 419                 };
 420
 421                 emmc_ds_pins: emmc-ds {
 422                         mux {
 423                                 groups = "emmc_ds";
 424                                 function = "emmc";
 425                                 bias-pull-down;
 426                         };
 427                 };
 428
 429                 emmc_clk_gate_pins: emmc_clk_gate {
 430                         mux {
 431                                 groups = "BOOT_8";
 432                                 function = "gpio_periphs";
 433                                 bias-pull-down;
 434                         };
 435                 };
 436
 437                 nor_pins: nor {
 438                         mux {
 439                                 groups = "nor_d",
 440                                        "nor_q",
 441                                        "nor_c",
 442                                        "nor_cs";
 443                                 function = "nor";
 444                                 bias-disable;
 445                         };
 446                 };
 447
 448                 spi_pins: spi-pins {
 449                         mux {
 450                                 groups = "spi_miso",
 451                                         "spi_mosi",
 452                                         "spi_sclk";
 453                                 function = "spi";
 454                                 bias-disable;
 455                         };
 456                 };
 457
 458                 spi_ss0_pins: spi-ss0 {
 459                         mux {
 460                                 groups = "spi_ss0";
 461                                 function = "spi";
 462                                 bias-disable;
 463                         };
 464                 };
 465
 466                 sdcard_pins: sdcard {
 467                         mux-0 {
 468                                 groups = "sdcard_d0",
 469                                        "sdcard_d1",
 470                                        "sdcard_d2",
 471                                        "sdcard_d3",
 472                                        "sdcard_cmd";
 473                                 function = "sdcard";
 474                                 bias-pull-up;
 475                         };
 476
 477                         mux-1 {
 478                                 groups = "sdcard_clk";
 479                                 function = "sdcard";
 480                                 bias-disable;
 481                         };
 482                 };
 483
 484                 sdcard_clk_gate_pins: sdcard_clk_gate {
 485                         mux {
 486                                 groups = "CARD_2";
 487                                 function = "gpio_periphs";
 488                                 bias-pull-down;
 489                         };
 490                 };
 491
 492                 sdio_pins: sdio {
 493                         mux-0 {
 494                                 groups = "sdio_d0",
 495                                        "sdio_d1",
 496                                        "sdio_d2",
 497                                        "sdio_d3",
 498                                        "sdio_cmd";
 499                                 function = "sdio";
 500                                 bias-pull-up;
 501                         };
 502
 503                         mux-1 {
 504                                 groups = "sdio_clk";
 505                                 function = "sdio";
 506                                 bias-disable;
 507                         };
 508                 };
 509
 510                 sdio_clk_gate_pins: sdio_clk_gate {
 511                         mux {
 512                                 groups = "GPIOX_4";
 513                                 function = "gpio_periphs";
 514                                 bias-pull-down;
 515                         };
 516                 };
 517
 518                 sdio_irq_pins: sdio_irq {
 519                         mux {
 520                                 groups = "sdio_irq";
 521                                 function = "sdio";
 522                                 bias-disable;
 523                         };
 524                 };
 525
 526                 uart_a_pins: uart_a {
 527                         mux {
 528                                 groups = "uart_tx_a",
 529                                        "uart_rx_a";
 530                                 function = "uart_a";
 531                                 bias-disable;
 532                         };
 533                 };
 534
 535                 uart_a_cts_rts_pins: uart_a_cts_rts {
 536                         mux {
 537                                 groups = "uart_cts_a",
 538                                        "uart_rts_a";
 539                                 function = "uart_a";
 540                                 bias-disable;
 541                         };
 542                 };
 543
 544                 uart_b_pins: uart_b {
 545                         mux {
 546                                 groups = "uart_tx_b",
 547                                        "uart_rx_b";
 548                                 function = "uart_b";
 549                                 bias-disable;
 550                         };
 551                 };
 552
 553                 uart_b_cts_rts_pins: uart_b_cts_rts {
 554                         mux {
 555                                 groups = "uart_cts_b",
 556                                        "uart_rts_b";
 557                                 function = "uart_b";
 558                                 bias-disable;
 559                         };
 560                 };
 561
 562                 uart_c_pins: uart_c {
 563                         mux {
 564                                 groups = "uart_tx_c",
 565                                        "uart_rx_c";
 566                                 function = "uart_c";
 567                                 bias-disable;
 568                         };
 569                 };
 570
 571                 uart_c_cts_rts_pins: uart_c_cts_rts {
 572                         mux {
 573                                 groups = "uart_cts_c",
 574                                        "uart_rts_c";
 575                                 function = "uart_c";
 576                                 bias-disable;
 577                         };
 578                 };
 579
 580                 i2c_a_pins: i2c_a {
 581                         mux {
 582                                 groups = "i2c_sck_a",
 583                                        "i2c_sda_a";
 584                                 function = "i2c_a";
 585                                 bias-disable;
 586                         };
 587                 };
 588
 589                 i2c_b_pins: i2c_b {
 590                         mux {
 591                                 groups = "i2c_sck_b",
 592                                        "i2c_sda_b";
 593                                 function = "i2c_b";
 594                                 bias-disable;
 595                         };
 596                 };
 597
 598                 i2c_c_pins: i2c_c {
 599                         mux {
 600                                 groups = "i2c_sck_c",
 601                                        "i2c_sda_c";
 602                                 function = "i2c_c";
 603                                 bias-disable;
 604                         };
 605                 };
 606
 607                 eth_rgmii_pins: eth-rgmii {
 608                         mux {
 609                                 groups = "eth_mdio",
 610                                        "eth_mdc",
 611                                        "eth_clk_rx_clk",
 612                                        "eth_rx_dv",
 613                                        "eth_rxd0",
 614                                        "eth_rxd1",
 615                                        "eth_rxd2",
 616                                        "eth_rxd3",
 617                                        "eth_rgmii_tx_clk",
 618                                        "eth_tx_en",
 619                                        "eth_txd0",
 620                                        "eth_txd1",
 621                                        "eth_txd2",
 622                                        "eth_txd3";
 623                                 function = "eth";
 624                                 bias-disable;
 625                         };
 626                 };
 627
 628                 eth_rmii_pins: eth-rmii {
 629                         mux {
 630                                 groups = "eth_mdio",
 631                                        "eth_mdc",
 632                                        "eth_clk_rx_clk",
 633                                        "eth_rx_dv",
 634                                        "eth_rxd0",
 635                                        "eth_rxd1",
 636                                        "eth_tx_en",
 637                                        "eth_txd0",
 638                                        "eth_txd1";
 639                                 function = "eth";
 640                                 bias-disable;
 641                         };
 642                 };
 643
 644                 pwm_a_x_pins: pwm_a_x {
 645                         mux {
 646                                 groups = "pwm_a_x";
 647                                 function = "pwm_a_x";
 648                                 bias-disable;
 649                         };
 650                 };
 651
 652                 pwm_a_y_pins: pwm_a_y {
 653                         mux {
 654                                 groups = "pwm_a_y";
 655                                 function = "pwm_a_y";
 656                                 bias-disable;
 657                         };
 658                 };
 659
 660                 pwm_b_pins: pwm_b {
 661                         mux {
 662                                 groups = "pwm_b";
 663                                 function = "pwm_b";
 664                                 bias-disable;
 665                         };
 666                 };
 667
 668                 pwm_d_pins: pwm_d {
 669                         mux {
 670                                 groups = "pwm_d";
 671                                 function = "pwm_d";
 672                                 bias-disable;
 673                         };
 674                 };
 675
 676                 pwm_e_pins: pwm_e {
 677                         mux {
 678                                 groups = "pwm_e";
 679                                 function = "pwm_e";
 680                                 bias-disable;
 681                         };
 682                 };
 683
 684                 pwm_f_x_pins: pwm_f_x {
 685                         mux {
 686                                 groups = "pwm_f_x";
 687                                 function = "pwm_f_x";
 688                                 bias-disable;
 689                         };
 690                 };
 691
 692                 pwm_f_y_pins: pwm_f_y {
 693                         mux {
 694                                 groups = "pwm_f_y";
 695                                 function = "pwm_f_y";
 696                                 bias-disable;
 697                         };
 698                 };
 699
 700                 hdmi_hpd_pins: hdmi_hpd {
 701                         mux {
 702                                 groups = "hdmi_hpd";
 703                                 function = "hdmi_hpd";
 704                                 bias-disable;
 705                         };
 706                 };
 707
 708                 hdmi_i2c_pins: hdmi_i2c {
 709                         mux {
 710                                 groups = "hdmi_sda", "hdmi_scl";
 711                                 function = "hdmi_i2c";
 712                                 bias-disable;
 713                         };
 714                 };
 715
 716                 i2sout_ch23_y_pins: i2sout_ch23_y {
 717                         mux {
 718                                 groups = "i2sout_ch23_y";
 719                                 function = "i2s_out";
 720                                 bias-disable;
 721                         };
 722                 };
 723
 724                 i2sout_ch45_y_pins: i2sout_ch45_y {
 725                         mux {
 726                                 groups = "i2sout_ch45_y";
 727                                 function = "i2s_out";
 728                                 bias-disable;
 729                         };
 730                 };
 731
 732                 i2sout_ch67_y_pins: i2sout_ch67_y {
 733                         mux {
 734                                 groups = "i2sout_ch67_y";
 735                                 function = "i2s_out";
 736                                 bias-disable;
 737                         };
 738                 };
 739
 740                 spdif_out_y_pins: spdif_out_y {
 741                         mux {
 742                                 groups = "spdif_out_y";
 743                                 function = "spdif_out";
 744                                 bias-disable;
 745                         };
 746                 };
 747         };
 748 };
 749
 750 &pwrc_vpu {
 751         resets = <&reset RESET_VIU>,
 752                  <&reset RESET_VENC>,
 753                  <&reset RESET_VCBUS>,
 754                  <&reset RESET_BT656>,
 755                  <&reset RESET_DVIN_RESET>,
 756                  <&reset RESET_RDMA>,
 757                  <&reset RESET_VENCI>,
 758                  <&reset RESET_VENCP>,
 759                  <&reset RESET_VDAC>,
 760                  <&reset RESET_VDI6>,
 761                  <&reset RESET_VENCL>,
 762                  <&reset RESET_VID_LOCK>;
 763         clocks = <&clkc CLKID_VPU>,
 764                  <&clkc CLKID_VAPB>;
 765         clock-names = "vpu", "vapb";
 766         /*
 767          * VPU clocking is provided by two identical clock paths
 768          * VPU_0 and VPU_1 muxed to a single clock by a glitch
 769          * free mux to safely change frequency while running.
 770          * Same for VAPB but with a final gate after the glitch free mux.
 771          */
 772         assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
 773                           <&clkc CLKID_VPU_0>,
 774                           <&clkc CLKID_VPU>, /* Glitch free mux */
 775                           <&clkc CLKID_VAPB_0_SEL>,
 776                           <&clkc CLKID_VAPB_0>,
 777                           <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
 778         assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
 779                                  <0>, /* Do Nothing */
 780                                  <&clkc CLKID_VPU_0>,
 781                                  <&clkc CLKID_FCLK_DIV4>,
 782                                  <0>, /* Do Nothing */
 783                                  <&clkc CLKID_VAPB_0>;
 784         assigned-clock-rates = <0>, /* Do Nothing */
 785                                <666666666>,
 786                                <0>, /* Do Nothing */
 787                                <0>, /* Do Nothing */
 788                                <250000000>,
 789                                <0>; /* Do Nothing */
 790 };
 791
 792 &saradc {
 793         compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
 794         clocks = <&xtal>,
 795                  <&clkc CLKID_SAR_ADC>,
 796                  <&clkc CLKID_SAR_ADC_CLK>,
 797                  <&clkc CLKID_SAR_ADC_SEL>;
 798         clock-names = "clkin", "core", "adc_clk", "adc_sel";
 799 };
 800
 801 &sd_emmc_a {
 802         clocks = <&clkc CLKID_SD_EMMC_A>,
 803                  <&clkc CLKID_SD_EMMC_A_CLK0>,
 804                  <&clkc CLKID_FCLK_DIV2>;
 805         clock-names = "core", "clkin0", "clkin1";
 806         resets = <&reset RESET_SD_EMMC_A>;
 807 };
 808
 809 &sd_emmc_b {
 810         clocks = <&clkc CLKID_SD_EMMC_B>,
 811                  <&clkc CLKID_SD_EMMC_B_CLK0>,
 812                  <&clkc CLKID_FCLK_DIV2>;
 813         clock-names = "core", "clkin0", "clkin1";
 814         resets = <&reset RESET_SD_EMMC_B>;
 815 };
 816
 817 &sd_emmc_c {
 818         clocks = <&clkc CLKID_SD_EMMC_C>,
 819                  <&clkc CLKID_SD_EMMC_C_CLK0>,
 820                  <&clkc CLKID_FCLK_DIV2>;
 821         clock-names = "core", "clkin0", "clkin1";
 822         resets = <&reset RESET_SD_EMMC_C>;
 823 };
 824
 825 &simplefb_hdmi {
 826         clocks = <&clkc CLKID_HDMI_PCLK>,
 827                  <&clkc CLKID_CLK81>,
 828                  <&clkc CLKID_GCLK_VENCI_INT0>;
 829 };
 830
 831 &spicc {
 832         clocks = <&clkc CLKID_SPICC>;
 833         clock-names = "core";
 834         resets = <&reset RESET_PERIPHS_SPICC>;
 835         num-cs = <1>;
 836 };
 837
 838 &spifc {
 839         clocks = <&clkc CLKID_SPI>;
 840 };
 841
 842 &uart_A {
 843         clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
 844         clock-names = "xtal", "pclk", "baud";
 845 };
 846
 847 &uart_AO {
 848         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
 849         clock-names = "xtal", "pclk", "baud";
 850 };
 851
 852 &uart_AO_B {
 853         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
 854         clock-names = "xtal", "pclk", "baud";
 855 };
 856
 857 &uart_B {
 858         clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
 859         clock-names = "xtal", "pclk", "baud";
 860 };
 861
 862 &uart_C {
 863         clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
 864         clock-names = "xtal", "pclk", "baud";
 865 };
 866
 867 &vpu {
 868         compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
 869         power-domains = <&pwrc_vpu>;
 870 };
 871
 872 &vdec {
 873         compatible = "amlogic,gxbb-vdec", "amlogic,gx-vdec";
 874         clocks = <&clkc CLKID_DOS_PARSER>,
 875                  <&clkc CLKID_DOS>,
 876                  <&clkc CLKID_VDEC_1>,
 877                  <&clkc CLKID_VDEC_HEVC>;
 878         clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
 879         resets = <&reset RESET_PARSER>;
 880         reset-names = "esparser";
 881 };