1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016 Andreas Färber
6 #include "meson-gx.dtsi"
7 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
8 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
9 #include <dt-bindings/clock/gxbb-clkc.h>
10 #include <dt-bindings/clock/gxbb-aoclkc.h>
11 #include <dt-bindings/reset/gxbb-aoclkc.h>
14 compatible = "amlogic,meson-gxbb";
17 usb0_phy: phy@c0000000 {
18 compatible = "amlogic,meson-gxbb-usb2-phy";
20 reg = <0x0 0xc0000000 0x0 0x20>;
21 resets = <&reset RESET_USB_OTG>;
22 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
23 clock-names = "usb_general", "usb";
27 usb1_phy: phy@c0000020 {
28 compatible = "amlogic,meson-gxbb-usb2-phy";
30 reg = <0x0 0xc0000020 0x0 0x20>;
31 resets = <&reset RESET_USB_OTG>;
32 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
33 clock-names = "usb_general", "usb";
38 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
39 reg = <0x0 0xc9000000 0x0 0x40000>;
40 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
41 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
44 phy-names = "usb2-phy";
50 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
51 reg = <0x0 0xc9100000 0x0 0x40000>;
52 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
53 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
56 phy-names = "usb2-phy";
64 pinctrl_aobus: pinctrl@14 {
65 compatible = "amlogic,meson-gxbb-aobus-pinctrl";
71 reg = <0x0 0x00014 0x0 0x8>,
72 <0x0 0x0002c 0x0 0x4>,
73 <0x0 0x00024 0x0 0x8>;
74 reg-names = "mux", "pull", "gpio";
77 gpio-ranges = <&pinctrl_aobus 0 0 14>;
80 uart_ao_a_pins: uart_ao_a {
82 groups = "uart_tx_ao_a", "uart_rx_ao_a";
88 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
90 groups = "uart_cts_ao_a",
97 uart_ao_b_pins: uart_ao_b {
99 groups = "uart_tx_ao_b", "uart_rx_ao_b";
100 function = "uart_ao_b";
105 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
107 groups = "uart_cts_ao_b",
109 function = "uart_ao_b";
114 remote_input_ao_pins: remote_input_ao {
116 groups = "remote_input_ao";
117 function = "remote_input_ao";
122 i2c_ao_pins: i2c_ao {
124 groups = "i2c_sck_ao",
131 pwm_ao_a_3_pins: pwm_ao_a_3 {
133 groups = "pwm_ao_a_3";
134 function = "pwm_ao_a_3";
139 pwm_ao_a_6_pins: pwm_ao_a_6 {
141 groups = "pwm_ao_a_6";
142 function = "pwm_ao_a_6";
147 pwm_ao_a_12_pins: pwm_ao_a_12 {
149 groups = "pwm_ao_a_12";
150 function = "pwm_ao_a_12";
155 pwm_ao_b_pins: pwm_ao_b {
158 function = "pwm_ao_b";
163 i2s_am_clk_pins: i2s_am_clk {
165 groups = "i2s_am_clk";
166 function = "i2s_out_ao";
171 i2s_out_ao_clk_pins: i2s_out_ao_clk {
173 groups = "i2s_out_ao_clk";
174 function = "i2s_out_ao";
179 i2s_out_lr_clk_pins: i2s_out_lr_clk {
181 groups = "i2s_out_lr_clk";
182 function = "i2s_out_ao";
187 i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
189 groups = "i2s_out_ch01_ao";
190 function = "i2s_out_ao";
195 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
197 groups = "i2s_out_ch23_ao";
198 function = "i2s_out_ao";
203 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
205 groups = "i2s_out_ch45_ao";
206 function = "i2s_out_ao";
211 spdif_out_ao_6_pins: spdif_out_ao_6 {
213 groups = "spdif_out_ao_6";
214 function = "spdif_out_ao";
218 spdif_out_ao_13_pins: spdif_out_ao_13 {
220 groups = "spdif_out_ao_13";
221 function = "spdif_out_ao";
226 ao_cec_pins: ao_cec {
234 ee_cec_pins: ee_cec {
246 compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
247 reg = <0x0 0xc0000 0x0 0x40000>;
248 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
258 interrupt-names = "gp", "gpmmu", "pp", "pmu",
259 "pp0", "ppmmu0", "pp1", "ppmmu1",
261 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
262 clock-names = "bus", "core";
265 * Mali clocking is provided by two identical clock paths
266 * MALI_0 and MALI_1 muxed to a single clock by a glitch
267 * free mux to safely change frequency while running.
269 assigned-clocks = <&clkc CLKID_GP0_PLL>,
270 <&clkc CLKID_MALI_0_SEL>,
271 <&clkc CLKID_MALI_0>,
272 <&clkc CLKID_MALI>; /* Glitch free mux */
273 assigned-clock-parents = <0>, /* Do Nothing */
274 <&clkc CLKID_GP0_PLL>,
275 <0>, /* Do Nothing */
276 <&clkc CLKID_MALI_0>;
277 assigned-clock-rates = <744000000>,
278 <0>, /* Do Nothing */
280 <0>; /* Do Nothing */
286 compatible = "amlogic,meson-gxbb-spifc";
287 reg = <0x0 0x08c80 0x0 0x80>;
288 #address-cells = <1>;
290 clocks = <&clkc CLKID_SPI>;
296 clocks = <&clkc_AO CLKID_AO_CEC_32K>;
297 clock-names = "core";
301 compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
302 clocks = <&xtal>, <&clkc CLKID_CLK81>;
303 clock-names = "xtal", "mpeg-clk";
307 clocks = <&clkc CLKID_EFUSE>;
311 clocks = <&clkc CLKID_ETH>,
312 <&clkc CLKID_FCLK_DIV2>,
314 clock-names = "stmmaceth", "clkin0", "clkin1";
318 compatible = "amlogic,meson-gpio-intc",
319 "amlogic,meson-gxbb-gpio-intc";
324 compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
325 resets = <&reset RESET_HDMITX_CAPB3>,
326 <&reset RESET_HDMI_SYSTEM_RESET>,
327 <&reset RESET_HDMI_TX>;
328 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
329 clocks = <&clkc CLKID_HDMI_PCLK>,
331 <&clkc CLKID_GCLK_VENCI_INT0>;
332 clock-names = "isfr", "iahb", "venci";
336 clkc: clock-controller {
337 compatible = "amlogic,gxbb-clkc";
340 clock-names = "xtal";
345 clocks = <&clkc CLKID_RNG0>;
346 clock-names = "core";
350 clocks = <&clkc CLKID_I2C>;
354 clocks = <&clkc CLKID_AO_I2C>;
358 clocks = <&clkc CLKID_I2C>;
362 clocks = <&clkc CLKID_I2C>;
366 pinctrl_periphs: pinctrl@4b0 {
367 compatible = "amlogic,meson-gxbb-periphs-pinctrl";
368 #address-cells = <2>;
373 reg = <0x0 0x004b0 0x0 0x28>,
374 <0x0 0x004e8 0x0 0x14>,
375 <0x0 0x00520 0x0 0x14>,
376 <0x0 0x00430 0x0 0x40>;
377 reg-names = "mux", "pull", "pull-enable", "gpio";
380 gpio-ranges = <&pinctrl_periphs 0 0 119>;
385 groups = "emmc_nand_d07",
393 emmc_ds_pins: emmc-ds {
401 emmc_clk_gate_pins: emmc_clk_gate {
404 function = "gpio_periphs";
430 spi_ss0_pins: spi-ss0 {
438 sdcard_pins: sdcard {
440 groups = "sdcard_d0",
451 sdcard_clk_gate_pins: sdcard_clk_gate {
454 function = "gpio_periphs";
472 sdio_clk_gate_pins: sdio_clk_gate {
475 function = "gpio_periphs";
480 sdio_irq_pins: sdio_irq {
488 uart_a_pins: uart_a {
490 groups = "uart_tx_a",
497 uart_a_cts_rts_pins: uart_a_cts_rts {
499 groups = "uart_cts_a",
506 uart_b_pins: uart_b {
508 groups = "uart_tx_b",
515 uart_b_cts_rts_pins: uart_b_cts_rts {
517 groups = "uart_cts_b",
524 uart_c_pins: uart_c {
526 groups = "uart_tx_c",
533 uart_c_cts_rts_pins: uart_c_cts_rts {
535 groups = "uart_cts_c",
544 groups = "i2c_sck_a",
553 groups = "i2c_sck_b",
562 groups = "i2c_sck_c",
569 eth_rgmii_pins: eth-rgmii {
590 eth_rmii_pins: eth-rmii {
606 pwm_a_x_pins: pwm_a_x {
609 function = "pwm_a_x";
614 pwm_a_y_pins: pwm_a_y {
617 function = "pwm_a_y";
646 pwm_f_x_pins: pwm_f_x {
649 function = "pwm_f_x";
654 pwm_f_y_pins: pwm_f_y {
657 function = "pwm_f_y";
662 hdmi_hpd_pins: hdmi_hpd {
665 function = "hdmi_hpd";
670 hdmi_i2c_pins: hdmi_i2c {
672 groups = "hdmi_sda", "hdmi_scl";
673 function = "hdmi_i2c";
678 i2sout_ch23_y_pins: i2sout_ch23_y {
680 groups = "i2sout_ch23_y";
681 function = "i2s_out";
686 i2sout_ch45_y_pins: i2sout_ch45_y {
688 groups = "i2sout_ch45_y";
689 function = "i2s_out";
694 i2sout_ch67_y_pins: i2sout_ch67_y {
696 groups = "i2sout_ch67_y";
697 function = "i2s_out";
702 spdif_out_y_pins: spdif_out_y {
704 groups = "spdif_out_y";
705 function = "spdif_out";
713 resets = <&reset RESET_VIU>,
715 <&reset RESET_VCBUS>,
716 <&reset RESET_BT656>,
717 <&reset RESET_DVIN_RESET>,
719 <&reset RESET_VENCI>,
720 <&reset RESET_VENCP>,
723 <&reset RESET_VENCL>,
724 <&reset RESET_VID_LOCK>;
725 clocks = <&clkc CLKID_VPU>,
727 clock-names = "vpu", "vapb";
729 * VPU clocking is provided by two identical clock paths
730 * VPU_0 and VPU_1 muxed to a single clock by a glitch
731 * free mux to safely change frequency while running.
732 * Same for VAPB but with a final gate after the glitch free mux.
734 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
736 <&clkc CLKID_VPU>, /* Glitch free mux */
737 <&clkc CLKID_VAPB_0_SEL>,
738 <&clkc CLKID_VAPB_0>,
739 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
740 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
741 <0>, /* Do Nothing */
743 <&clkc CLKID_FCLK_DIV4>,
744 <0>, /* Do Nothing */
745 <&clkc CLKID_VAPB_0>;
746 assigned-clock-rates = <0>, /* Do Nothing */
748 <0>, /* Do Nothing */
749 <0>, /* Do Nothing */
751 <0>; /* Do Nothing */
755 compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
757 <&clkc CLKID_SAR_ADC>,
758 <&clkc CLKID_SAR_ADC_CLK>,
759 <&clkc CLKID_SAR_ADC_SEL>;
760 clock-names = "clkin", "core", "adc_clk", "adc_sel";
764 clocks = <&clkc CLKID_SD_EMMC_A>,
765 <&clkc CLKID_SD_EMMC_A_CLK0>,
766 <&clkc CLKID_FCLK_DIV2>;
767 clock-names = "core", "clkin0", "clkin1";
768 resets = <&reset RESET_SD_EMMC_A>;
772 clocks = <&clkc CLKID_SD_EMMC_B>,
773 <&clkc CLKID_SD_EMMC_B_CLK0>,
774 <&clkc CLKID_FCLK_DIV2>;
775 clock-names = "core", "clkin0", "clkin1";
776 resets = <&reset RESET_SD_EMMC_B>;
780 clocks = <&clkc CLKID_SD_EMMC_C>,
781 <&clkc CLKID_SD_EMMC_C_CLK0>,
782 <&clkc CLKID_FCLK_DIV2>;
783 clock-names = "core", "clkin0", "clkin1";
784 resets = <&reset RESET_SD_EMMC_C>;
788 clocks = <&clkc CLKID_HDMI_PCLK>,
790 <&clkc CLKID_GCLK_VENCI_INT0>;
794 clocks = <&clkc CLKID_SPICC>;
795 clock-names = "core";
796 resets = <&reset RESET_PERIPHS_SPICC>;
801 clocks = <&clkc CLKID_SPI>;
805 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
806 clock-names = "xtal", "pclk", "baud";
810 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
811 clock-names = "xtal", "pclk", "baud";
815 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
816 clock-names = "xtal", "pclk", "baud";
820 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
821 clock-names = "xtal", "pclk", "baud";
825 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
826 clock-names = "xtal", "pclk", "baud";
830 compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
831 power-domains = <&pwrc_vpu>;