src/arm64/amlogic/meson-gxl.dtsi

   1 /*
   2  * Copyright (c) 2016 Endless Computers, Inc.
   3  * Author: Carlo Caione <carlo@endlessm.com>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This library is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This library is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include "meson-gx.dtsi"
  45 #include <dt-bindings/clock/gxbb-clkc.h>
  46 #include <dt-bindings/gpio/meson-gxl-gpio.h>
  47 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
  48
  49 / {
  50         compatible = "amlogic,meson-gxl";
  51 };
  52
  53 &ethmac {
  54         reg = <0x0 0xc9410000 0x0 0x10000
  55                0x0 0xc8834540 0x0 0x4>;
  56
  57         clocks = <&clkc CLKID_ETH>,
  58                  <&clkc CLKID_FCLK_DIV2>,
  59                  <&clkc CLKID_MPLL2>;
  60         clock-names = "stmmaceth", "clkin0", "clkin1";
  61
  62         mdio0: mdio {
  63                 #address-cells = <1>;
  64                 #size-cells = <0>;
  65                 compatible = "snps,dwmac-mdio";
  66         };
  67 };
  68
  69 &aobus {
  70         pinctrl_aobus: pinctrl@14 {
  71                 compatible = "amlogic,meson-gxl-aobus-pinctrl";
  72                 #address-cells = <2>;
  73                 #size-cells = <2>;
  74                 ranges;
  75
  76                 gpio_ao: bank@14 {
  77                         reg = <0x0 0x00014 0x0 0x8>,
  78                               <0x0 0x0002c 0x0 0x4>,
  79                               <0x0 0x00024 0x0 0x8>;
  80                         reg-names = "mux", "pull", "gpio";
  81                         gpio-controller;
  82                         #gpio-cells = <2>;
  83                         gpio-ranges = <&pinctrl_aobus 0 0 14>;
  84                 };
  85
  86                 uart_ao_a_pins: uart_ao_a {
  87                         mux {
  88                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
  89                                 function = "uart_ao";
  90                         };
  91                 };
  92
  93                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
  94                         mux {
  95                                 groups = "uart_cts_ao_a",
  96                                        "uart_rts_ao_a";
  97                                 function = "uart_ao";
  98                         };
  99                 };
 100
 101                 uart_ao_b_pins: uart_ao_b {
 102                         mux {
 103                                 groups = "uart_tx_ao_b", "uart_rx_ao_b";
 104                                 function = "uart_ao_b";
 105                         };
 106                 };
 107
 108                 uart_ao_b_0_1_pins: uart_ao_b_0_1 {
 109                         mux {
 110                                 groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
 111                                 function = "uart_ao_b";
 112                         };
 113                 };
 114
 115                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
 116                         mux {
 117                                 groups = "uart_cts_ao_b",
 118                                        "uart_rts_ao_b";
 119                                 function = "uart_ao_b";
 120                         };
 121                 };
 122
 123                 remote_input_ao_pins: remote_input_ao {
 124                         mux {
 125                                 groups = "remote_input_ao";
 126                                 function = "remote_input_ao";
 127                         };
 128                 };
 129
 130                 i2c_ao_pins: i2c_ao {
 131                         mux {
 132                                 groups = "i2c_sck_ao",
 133                                        "i2c_sda_ao";
 134                                 function = "i2c_ao";
 135                         };
 136                 };
 137
 138                 pwm_ao_a_3_pins: pwm_ao_a_3 {
 139                         mux {
 140                                 groups = "pwm_ao_a_3";
 141                                 function = "pwm_ao_a";
 142                         };
 143                 };
 144
 145                 pwm_ao_a_8_pins: pwm_ao_a_8 {
 146                         mux {
 147                                 groups = "pwm_ao_a_8";
 148                                 function = "pwm_ao_a";
 149                         };
 150                 };
 151
 152                 pwm_ao_b_pins: pwm_ao_b {
 153                         mux {
 154                                 groups = "pwm_ao_b";
 155                                 function = "pwm_ao_b";
 156                         };
 157                 };
 158
 159                 pwm_ao_b_6_pins: pwm_ao_b_6 {
 160                         mux {
 161                                 groups = "pwm_ao_b_6";
 162                                 function = "pwm_ao_b";
 163                         };
 164                 };
 165
 166                 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
 167                         mux {
 168                                 groups = "i2s_out_ch23_ao";
 169                                 function = "i2s_out_ao";
 170                         };
 171                 };
 172
 173                 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
 174                         mux {
 175                                 groups = "i2s_out_ch45_ao";
 176                                 function = "i2s_out_ao";
 177                         };
 178                 };
 179
 180                 spdif_out_ao_6_pins: spdif_out_ao_6 {
 181                         mux {
 182                                 groups = "spdif_out_ao_6";
 183                                 function = "spdif_out_ao";
 184                         };
 185                 };
 186
 187                 spdif_out_ao_9_pins: spdif_out_ao_9 {
 188                         mux {
 189                                 groups = "spdif_out_ao_9";
 190                                 function = "spdif_out_ao";
 191                         };
 192                 };
 193         };
 194 };
 195
 196 &periphs {
 197         pinctrl_periphs: pinctrl@4b0 {
 198                 compatible = "amlogic,meson-gxl-periphs-pinctrl";
 199                 #address-cells = <2>;
 200                 #size-cells = <2>;
 201                 ranges;
 202
 203                 gpio: bank@4b0 {
 204                         reg = <0x0 0x004b0 0x0 0x28>,
 205                               <0x0 0x004e8 0x0 0x14>,
 206                               <0x0 0x00120 0x0 0x14>,
 207                               <0x0 0x00430 0x0 0x40>;
 208                         reg-names = "mux", "pull", "pull-enable", "gpio";
 209                         gpio-controller;
 210                         #gpio-cells = <2>;
 211                         gpio-ranges = <&pinctrl_periphs 0 14 101>;
 212                 };
 213
 214                 emmc_pins: emmc {
 215                         mux {
 216                                 groups = "emmc_nand_d07",
 217                                        "emmc_cmd",
 218                                        "emmc_clk",
 219                                        "emmc_ds";
 220                                 function = "emmc";
 221                         };
 222                 };
 223
 224                 nor_pins: nor {
 225                         mux {
 226                                 groups = "nor_d",
 227                                        "nor_q",
 228                                        "nor_c",
 229                                        "nor_cs";
 230                                 function = "nor";
 231                         };
 232                 };
 233
 234                 sdcard_pins: sdcard {
 235                         mux {
 236                                 groups = "sdcard_d0",
 237                                        "sdcard_d1",
 238                                        "sdcard_d2",
 239                                        "sdcard_d3",
 240                                        "sdcard_cmd",
 241                                        "sdcard_clk";
 242                                 function = "sdcard";
 243                         };
 244                 };
 245
 246                 sdio_pins: sdio {
 247                         mux {
 248                                 groups = "sdio_d0",
 249                                        "sdio_d1",
 250                                        "sdio_d2",
 251                                        "sdio_d3",
 252                                        "sdio_cmd",
 253                                        "sdio_clk";
 254                                 function = "sdio";
 255                         };
 256                 };
 257
 258                 sdio_irq_pins: sdio_irq {
 259                         mux {
 260                                 groups = "sdio_irq";
 261                                 function = "sdio";
 262                         };
 263                 };
 264
 265                 uart_a_pins: uart_a {
 266                         mux {
 267                                 groups = "uart_tx_a",
 268                                        "uart_rx_a";
 269                                 function = "uart_a";
 270                         };
 271                 };
 272
 273                 uart_a_cts_rts_pins: uart_a_cts_rts {
 274                         mux {
 275                                 groups = "uart_cts_a",
 276                                        "uart_rts_a";
 277                                 function = "uart_a";
 278                         };
 279                 };
 280
 281                 uart_b_pins: uart_b {
 282                         mux {
 283                                 groups = "uart_tx_b",
 284                                        "uart_rx_b";
 285                                 function = "uart_b";
 286                         };
 287                 };
 288
 289                 uart_b_cts_rts_pins: uart_b_cts_rts {
 290                         mux {
 291                                 groups = "uart_cts_b",
 292                                        "uart_rts_b";
 293                                 function = "uart_b";
 294                         };
 295                 };
 296
 297                 uart_c_pins: uart_c {
 298                         mux {
 299                                 groups = "uart_tx_c",
 300                                        "uart_rx_c";
 301                                 function = "uart_c";
 302                         };
 303                 };
 304
 305                 uart_c_cts_rts_pins: uart_c_cts_rts {
 306                         mux {
 307                                 groups = "uart_cts_c",
 308                                        "uart_rts_c";
 309                                 function = "uart_c";
 310                         };
 311                 };
 312
 313                 i2c_a_pins: i2c_a {
 314                         mux {
 315                                 groups = "i2c_sck_a",
 316                                      "i2c_sda_a";
 317                                 function = "i2c_a";
 318                         };
 319                 };
 320
 321                 i2c_b_pins: i2c_b {
 322                         mux {
 323                                 groups = "i2c_sck_b",
 324                                       "i2c_sda_b";
 325                                 function = "i2c_b";
 326                         };
 327                 };
 328
 329                 i2c_c_pins: i2c_c {
 330                         mux {
 331                                 groups = "i2c_sck_c",
 332                                       "i2c_sda_c";
 333                                 function = "i2c_c";
 334                         };
 335                 };
 336
 337                 eth_pins: eth_c {
 338                         mux {
 339                                 groups = "eth_mdio",
 340                                        "eth_mdc",
 341                                        "eth_clk_rx_clk",
 342                                        "eth_rx_dv",
 343                                        "eth_rxd0",
 344                                        "eth_rxd1",
 345                                        "eth_rxd2",
 346                                        "eth_rxd3",
 347                                        "eth_rgmii_tx_clk",
 348                                        "eth_tx_en",
 349                                        "eth_txd0",
 350                                        "eth_txd1",
 351                                        "eth_txd2",
 352                                        "eth_txd3";
 353                                 function = "eth";
 354                         };
 355                 };
 356
 357                 pwm_a_pins: pwm_a {
 358                         mux {
 359                                 groups = "pwm_a";
 360                                 function = "pwm_a";
 361                         };
 362                 };
 363
 364                 pwm_b_pins: pwm_b {
 365                         mux {
 366                                 groups = "pwm_b";
 367                                 function = "pwm_b";
 368                         };
 369                 };
 370
 371                 pwm_c_pins: pwm_c {
 372                         mux {
 373                                 groups = "pwm_c";
 374                                 function = "pwm_c";
 375                         };
 376                 };
 377
 378                 pwm_d_pins: pwm_d {
 379                         mux {
 380                                 groups = "pwm_d";
 381                                 function = "pwm_d";
 382                         };
 383                 };
 384
 385                 pwm_e_pins: pwm_e {
 386                         mux {
 387                                 groups = "pwm_e";
 388                                 function = "pwm_e";
 389                         };
 390                 };
 391
 392                 pwm_f_clk_pins: pwm_f_clk {
 393                         mux {
 394                                 groups = "pwm_f_clk";
 395                                 function = "pwm_f";
 396                         };
 397                 };
 398
 399                 pwm_f_x_pins: pwm_f_x {
 400                         mux {
 401                                 groups = "pwm_f_x";
 402                                 function = "pwm_f";
 403                         };
 404                 };
 405
 406                 hdmi_hpd_pins: hdmi_hpd {
 407                         mux {
 408                                 groups = "hdmi_hpd";
 409                                 function = "hdmi_hpd";
 410                         };
 411                 };
 412
 413                 hdmi_i2c_pins: hdmi_i2c {
 414                         mux {
 415                                 groups = "hdmi_sda", "hdmi_scl";
 416                                 function = "hdmi_i2c";
 417                         };
 418                 };
 419
 420                 i2s_am_clk_pins: i2s_am_clk {
 421                         mux {
 422                                 groups = "i2s_am_clk";
 423                                 function = "i2s_out";
 424                         };
 425                 };
 426
 427                 i2s_out_ao_clk_pins: i2s_out_ao_clk {
 428                         mux {
 429                                 groups = "i2s_out_ao_clk";
 430                                 function = "i2s_out";
 431                         };
 432                 };
 433
 434                 i2s_out_lr_clk_pins: i2s_out_lr_clk {
 435                         mux {
 436                                 groups = "i2s_out_lr_clk";
 437                                 function = "i2s_out";
 438                         };
 439                 };
 440
 441                 i2s_out_ch01_pins: i2s_out_ch01 {
 442                         mux {
 443                                 groups = "i2s_out_ch01";
 444                                 function = "i2s_out";
 445                         };
 446                 };
 447                 i2sout_ch23_z_pins: i2sout_ch23_z {
 448                         mux {
 449                                 groups = "i2sout_ch23_z";
 450                                 function = "i2s_out";
 451                         };
 452                 };
 453
 454                 i2sout_ch45_z_pins: i2sout_ch45_z {
 455                         mux {
 456                                 groups = "i2sout_ch45_z";
 457                                 function = "i2s_out";
 458                         };
 459                 };
 460
 461                 i2sout_ch67_z_pins: i2sout_ch67_z {
 462                         mux {
 463                                 groups = "i2sout_ch67_z";
 464                                 function = "i2s_out";
 465                         };
 466                 };
 467
 468                 spdif_out_h_pins: spdif_out_ao_h {
 469                         mux {
 470                                 groups = "spdif_out_h";
 471                                 function = "spdif_out";
 472                         };
 473                 };
 474         };
 475
 476         eth-phy-mux {
 477                 compatible = "mdio-mux-mmioreg", "mdio-mux";
 478                 #address-cells = <1>;
 479                 #size-cells = <0>;
 480                 reg = <0x0 0x55c 0x0 0x4>;
 481                 mux-mask = <0xffffffff>;
 482                 mdio-parent-bus = <&mdio0>;
 483
 484                 internal_mdio: mdio@e40908ff {
 485                         reg = <0xe40908ff>;
 486                         #address-cells = <1>;
 487                         #size-cells = <0>;
 488
 489                         internal_phy: ethernet-phy@8 {
 490                                 compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
 491                                 reg = <8>;
 492                                 max-speed = <100>;
 493                         };
 494                 };
 495
 496                 external_mdio: mdio@2009087f {
 497                         reg = <0x2009087f>;
 498                         #address-cells = <1>;
 499                         #size-cells = <0>;
 500                 };
 501         };
 502 };
 503
 504 &hiubus {
 505         clkc: clock-controller@0 {
 506                 compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
 507                 #clock-cells = <1>;
 508                 reg = <0x0 0x0 0x0 0x3db>;
 509         };
 510 };
 511
 512 &i2c_A {
 513         clocks = <&clkc CLKID_I2C>;
 514 };
 515
 516 &i2c_AO {
 517         clocks = <&clkc CLKID_AO_I2C>;
 518 };
 519
 520 &i2c_B {
 521         clocks = <&clkc CLKID_I2C>;
 522 };
 523
 524 &i2c_C {
 525         clocks = <&clkc CLKID_I2C>;
 526 };
 527
 528 &saradc {
 529         compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
 530         clocks = <&xtal>,
 531                  <&clkc CLKID_SAR_ADC>,
 532                  <&clkc CLKID_SANA>,
 533                  <&clkc CLKID_SAR_ADC_CLK>,
 534                  <&clkc CLKID_SAR_ADC_SEL>;
 535         clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
 536 };
 537
 538 &sd_emmc_a {
 539         clocks = <&clkc CLKID_SD_EMMC_A>,
 540                  <&xtal>,
 541                  <&clkc CLKID_FCLK_DIV2>;
 542         clock-names = "core", "clkin0", "clkin1";
 543 };
 544
 545 &sd_emmc_b {
 546         clocks = <&clkc CLKID_SD_EMMC_B>,
 547                  <&xtal>,
 548                  <&clkc CLKID_FCLK_DIV2>;
 549        clock-names = "core", "clkin0", "clkin1";
 550 };
 551
 552 &sd_emmc_c {
 553         clocks = <&clkc CLKID_SD_EMMC_C>,
 554                  <&xtal>,
 555                  <&clkc CLKID_FCLK_DIV2>;
 556         clock-names = "core", "clkin0", "clkin1";
 557 };
 558
 559 &spifc {
 560         clocks = <&clkc CLKID_SPI>;
 561 };
 562
 563 &vpu {
 564         compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
 565 };
 566
 567 &hdmi_tx {
 568         compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
 569         resets = <&reset RESET_HDMITX_CAPB3>,
 570                  <&reset RESET_HDMI_SYSTEM_RESET>,
 571                  <&reset RESET_HDMI_TX>;
 572         reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
 573         clocks = <&clkc CLKID_HDMI_PCLK>,
 574                  <&clkc CLKID_CLK81>,
 575                  <&clkc CLKID_GCLK_VENCI_INT0>;
 576         clock-names = "isfr", "iahb", "venci";
 577 };