src/arm64/amlogic/meson-s4.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/irq.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9
  10 / {
  11         cpus {
  12                 #address-cells = <2>;
  13                 #size-cells = <0>;
  14
  15                 cpu0: cpu@0 {
  16                         device_type = "cpu";
  17                         compatible = "arm,cortex-a35";
  18                         reg = <0x0 0x0>;
  19                         enable-method = "psci";
  20                 };
  21
  22                 cpu1: cpu@1 {
  23                         device_type = "cpu";
  24                         compatible = "arm,cortex-a35";
  25                         reg = <0x0 0x1>;
  26                         enable-method = "psci";
  27                 };
  28
  29                 cpu2: cpu@2 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a35";
  32                         reg = <0x0 0x2>;
  33                         enable-method = "psci";
  34                 };
  35
  36                 cpu3: cpu@3 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a35";
  39                         reg = <0x0 0x3>;
  40                         enable-method = "psci";
  41                 };
  42         };
  43
  44         timer {
  45                 compatible = "arm,armv8-timer";
  46                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  47                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  48                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  49                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  50         };
  51
  52         psci {
  53                 compatible = "arm,psci-1.0";
  54                 method = "smc";
  55         };
  56
  57         xtal: xtal-clk {
  58                 compatible = "fixed-clock";
  59                 clock-frequency = <24000000>;
  60                 clock-output-names = "xtal";
  61                 #clock-cells = <0>;
  62         };
  63
  64         pwrc: power-controller {
  65                 compatible = "amlogic,meson-s4-pwrc";
  66                 #power-domain-cells = <1>;
  67                 status = "okay";
  68         };
  69
  70         soc {
  71                 compatible = "simple-bus";
  72                 #address-cells = <2>;
  73                 #size-cells = <2>;
  74                 ranges;
  75
  76                 gic: interrupt-controller@fff01000 {
  77                         compatible = "arm,gic-400";
  78                         #interrupt-cells = <3>;
  79                         #address-cells = <0>;
  80                         interrupt-controller;
  81                         reg = <0x0 0xfff01000 0 0x1000>,
  82                               <0x0 0xfff02000 0 0x2000>,
  83                               <0x0 0xfff04000 0 0x2000>,
  84                               <0x0 0xfff06000 0 0x2000>;
  85                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  86                 };
  87
  88                 apb4: bus@fe000000 {
  89                         compatible = "simple-bus";
  90                         reg = <0x0 0xfe000000 0x0 0x480000>;
  91                         #address-cells = <2>;
  92                         #size-cells = <2>;
  93                         ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
  94
  95                         periphs_pinctrl: pinctrl@4000 {
  96                                 compatible = "amlogic,meson-s4-periphs-pinctrl";
  97                                 #address-cells = <2>;
  98                                 #size-cells = <2>;
  99                                 ranges;
 100
 101                                 gpio: bank@4000 {
 102                                         reg = <0x0 0x4000 0x0 0x004c>,
 103                                               <0x0 0x40c0 0x0 0x0220>;
 104                                         reg-names = "mux", "gpio";
 105                                         gpio-controller;
 106                                         #gpio-cells = <2>;
 107                                         gpio-ranges = <&periphs_pinctrl 0 0 82>;
 108                                 };
 109                         };
 110
 111                         gpio_intc: interrupt-controller@4080 {
 112                                 compatible = "amlogic,meson-s4-gpio-intc",
 113                                              "amlogic,meson-gpio-intc";
 114                                 reg = <0x0 0x4080 0x0 0x20>;
 115                                 interrupt-controller;
 116                                 #interrupt-cells = <2>;
 117                                 amlogic,channel-interrupts =
 118                                         <10 11 12 13 14 15 16 17 18 19 20 21>;
 119                         };
 120
 121                         uart_B: serial@7a000 {
 122                                 compatible = "amlogic,meson-s4-uart",
 123                                              "amlogic,meson-ao-uart";
 124                                 reg = <0x0 0x7a000 0x0 0x18>;
 125                                 interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
 126                                 status = "disabled";
 127                                 clocks = <&xtal>, <&xtal>, <&xtal>;
 128                                 clock-names = "xtal", "pclk", "baud";
 129                         };
 130
 131                         reset: reset-controller@2000 {
 132                                 compatible = "amlogic,meson-s4-reset";
 133                                 reg = <0x0 0x2000 0x0 0x98>;
 134                                 #reset-cells = <1>;
 135                         };
 136                 };
 137         };
 138 };