src/arm64/arm/juno-r2.dts

   1 /*
   2  * ARM Ltd. Juno Platform
   3  *
   4  * Copyright (c) 2015 ARM Ltd.
   5  *
   6  * This file is licensed under a dual GPLv2 or BSD license.
   7  */
   8
   9 /dts-v1/;
  10
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include "juno-base.dtsi"
  13 #include "juno-cs-r1r2.dtsi"
  14
  15 / {
  16         model = "ARM Juno development board (r2)";
  17         compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 serial0 = &soc_uart0;
  24         };
  25
  26         chosen {
  27                 stdout-path = "serial0:115200n8";
  28         };
  29
  30         psci {
  31                 compatible = "arm,psci-0.2";
  32                 method = "smc";
  33         };
  34
  35         cpus {
  36                 #address-cells = <2>;
  37                 #size-cells = <0>;
  38
  39                 cpu-map {
  40                         cluster0 {
  41                                 core0 {
  42                                         cpu = <&A72_0>;
  43                                 };
  44                                 core1 {
  45                                         cpu = <&A72_1>;
  46                                 };
  47                         };
  48
  49                         cluster1 {
  50                                 core0 {
  51                                         cpu = <&A53_0>;
  52                                 };
  53                                 core1 {
  54                                         cpu = <&A53_1>;
  55                                 };
  56                                 core2 {
  57                                         cpu = <&A53_2>;
  58                                 };
  59                                 core3 {
  60                                         cpu = <&A53_3>;
  61                                 };
  62                         };
  63                 };
  64
  65                 idle-states {
  66                         entry-method = "arm,psci";
  67
  68                         CPU_SLEEP_0: cpu-sleep-0 {
  69                                 compatible = "arm,idle-state";
  70                                 arm,psci-suspend-param = <0x0010000>;
  71                                 local-timer-stop;
  72                                 entry-latency-us = <300>;
  73                                 exit-latency-us = <1200>;
  74                                 min-residency-us = <2000>;
  75                         };
  76
  77                         CLUSTER_SLEEP_0: cluster-sleep-0 {
  78                                 compatible = "arm,idle-state";
  79                                 arm,psci-suspend-param = <0x1010000>;
  80                                 local-timer-stop;
  81                                 entry-latency-us = <400>;
  82                                 exit-latency-us = <1200>;
  83                                 min-residency-us = <2500>;
  84                         };
  85                 };
  86
  87                 A72_0: cpu@0 {
  88                         compatible = "arm,cortex-a72","arm,armv8";
  89                         reg = <0x0 0x0>;
  90                         device_type = "cpu";
  91                         enable-method = "psci";
  92                         next-level-cache = <&A72_L2>;
  93                         clocks = <&scpi_dvfs 0>;
  94                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  95                         capacity-dmips-mhz = <1024>;
  96                 };
  97
  98                 A72_1: cpu@1 {
  99                         compatible = "arm,cortex-a72","arm,armv8";
 100                         reg = <0x0 0x1>;
 101                         device_type = "cpu";
 102                         enable-method = "psci";
 103                         next-level-cache = <&A72_L2>;
 104                         clocks = <&scpi_dvfs 0>;
 105                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 106                         capacity-dmips-mhz = <1024>;
 107                 };
 108
 109                 A53_0: cpu@100 {
 110                         compatible = "arm,cortex-a53","arm,armv8";
 111                         reg = <0x0 0x100>;
 112                         device_type = "cpu";
 113                         enable-method = "psci";
 114                         next-level-cache = <&A53_L2>;
 115                         clocks = <&scpi_dvfs 1>;
 116                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 117                         capacity-dmips-mhz = <485>;
 118                 };
 119
 120                 A53_1: cpu@101 {
 121                         compatible = "arm,cortex-a53","arm,armv8";
 122                         reg = <0x0 0x101>;
 123                         device_type = "cpu";
 124                         enable-method = "psci";
 125                         next-level-cache = <&A53_L2>;
 126                         clocks = <&scpi_dvfs 1>;
 127                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 128                         capacity-dmips-mhz = <485>;
 129                 };
 130
 131                 A53_2: cpu@102 {
 132                         compatible = "arm,cortex-a53","arm,armv8";
 133                         reg = <0x0 0x102>;
 134                         device_type = "cpu";
 135                         enable-method = "psci";
 136                         next-level-cache = <&A53_L2>;
 137                         clocks = <&scpi_dvfs 1>;
 138                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 139                         capacity-dmips-mhz = <485>;
 140                 };
 141
 142                 A53_3: cpu@103 {
 143                         compatible = "arm,cortex-a53","arm,armv8";
 144                         reg = <0x0 0x103>;
 145                         device_type = "cpu";
 146                         enable-method = "psci";
 147                         next-level-cache = <&A53_L2>;
 148                         clocks = <&scpi_dvfs 1>;
 149                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 150                         capacity-dmips-mhz = <485>;
 151                 };
 152
 153                 A72_L2: l2-cache0 {
 154                         compatible = "cache";
 155                 };
 156
 157                 A53_L2: l2-cache1 {
 158                         compatible = "cache";
 159                 };
 160         };
 161
 162         pmu_a72 {
 163                 compatible = "arm,cortex-a72-pmu";
 164                 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
 165                              <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
 166                 interrupt-affinity = <&A72_0>,
 167                                      <&A72_1>;
 168         };
 169
 170         pmu_a53 {
 171                 compatible = "arm,cortex-a53-pmu";
 172                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 173                              <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 174                              <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 175                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 176                 interrupt-affinity = <&A53_0>,
 177                                      <&A53_1>,
 178                                      <&A53_2>,
 179                                      <&A53_3>;
 180         };
 181 };
 182
 183 &memtimer {
 184         status = "okay";
 185 };
 186
 187 &pcie_ctlr {
 188         status = "okay";
 189 };
 190
 191 &etm0 {
 192         cpu = <&A72_0>;
 193 };
 194
 195 &etm1 {
 196         cpu = <&A72_1>;
 197 };
 198
 199 &etm2 {
 200         cpu = <&A53_0>;
 201 };
 202
 203 &etm3 {
 204         cpu = <&A53_1>;
 205 };
 206
 207 &etm4 {
 208         cpu = <&A53_2>;
 209 };
 210
 211 &etm5 {
 212         cpu = <&A53_3>;
 213 };
 214
 215 &big_cluster_thermal_zone {
 216         status = "okay";
 217 };
 218
 219 &little_cluster_thermal_zone {
 220         status = "okay";
 221 };
 222
 223 &gpu0_thermal_zone {
 224         status = "okay";
 225 };
 226
 227 &gpu1_thermal_zone {
 228         status = "okay";
 229 };
 230
 231 &etf0_out_port {
 232         remote-endpoint = <&csys2_funnel_in_port0>;
 233 };
 234
 235 &replicator_in_port0 {
 236         remote-endpoint = <&csys2_funnel_out_port>;
 237 };
 238
 239 &stm_out_port {
 240         remote-endpoint = <&csys1_funnel_in_port0>;
 241 };