src/arm64/broadcom/bcmbca/bcm6858.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2022 Broadcom Ltd.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/irq.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8
   9 / {
  10         compatible = "brcm,bcm6858", "brcm,bcmbca";
  11         #address-cells = <2>;
  12         #size-cells = <2>;
  13
  14         interrupt-parent = <&gic>;
  15
  16         cpus {
  17                 #address-cells = <2>;
  18                 #size-cells = <0>;
  19
  20                 B53_0: cpu@0 {
  21                         compatible = "brcm,brahma-b53";
  22                         device_type = "cpu";
  23                         reg = <0x0 0x0>;
  24                         next-level-cache = <&L2_0>;
  25                         enable-method = "psci";
  26                 };
  27
  28                 B53_1: cpu@1 {
  29                         compatible = "brcm,brahma-b53";
  30                         device_type = "cpu";
  31                         reg = <0x0 0x1>;
  32                         next-level-cache = <&L2_0>;
  33                         enable-method = "psci";
  34                 };
  35
  36                 B53_2: cpu@2 {
  37                         compatible = "brcm,brahma-b53";
  38                         device_type = "cpu";
  39                         reg = <0x0 0x2>;
  40                         next-level-cache = <&L2_0>;
  41                         enable-method = "psci";
  42                 };
  43
  44                 B53_3: cpu@3 {
  45                         compatible = "brcm,brahma-b53";
  46                         device_type = "cpu";
  47                         reg = <0x0 0x3>;
  48                         next-level-cache = <&L2_0>;
  49                         enable-method = "psci";
  50                 };
  51                 L2_0: l2-cache0 {
  52                         compatible = "cache";
  53                         cache-level = <2>;
  54                 };
  55         };
  56
  57         timer {
  58                 compatible = "arm,armv8-timer";
  59                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  60                         <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  61                         <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  62                         <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  63         };
  64
  65         pmu: pmu {
  66                 compatible = "arm,armv8-pmuv3";
  67                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  68                         <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
  69                         <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
  70                         <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
  71                 interrupt-affinity = <&B53_0>, <&B53_1>,
  72                         <&B53_2>, <&B53_3>;
  73         };
  74
  75         clocks: clocks {
  76                 periph_clk:periph-clk {
  77                         compatible = "fixed-clock";
  78                         #clock-cells = <0>;
  79                         clock-frequency = <200000000>;
  80                 };
  81         };
  82
  83         psci {
  84                 compatible = "arm,psci-0.2";
  85                 method = "smc";
  86         };
  87
  88         axi@81000000 {
  89                 compatible = "simple-bus";
  90                 #address-cells = <1>;
  91                 #size-cells = <1>;
  92                 ranges = <0x0 0x0 0x81000000 0x8000>;
  93
  94                 gic: interrupt-controller@1000 {
  95                         compatible = "arm,gic-400";
  96                         #interrupt-cells = <3>;
  97                         interrupt-controller;
  98                         reg = <0x1000 0x1000>, /* GICD */
  99                                 <0x2000 0x2000>, /* GICC */
 100                                 <0x4000 0x2000>, /* GICH */
 101                                 <0x6000 0x2000>; /* GICV */
 102                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
 103                                         IRQ_TYPE_LEVEL_HIGH)>;
 104                 };
 105         };
 106
 107         bus@ff800000 {
 108                 compatible = "simple-bus";
 109                 #address-cells = <1>;
 110                 #size-cells = <1>;
 111                 ranges = <0x0 0x0 0xff800000 0x62000>;
 112
 113                 twd: timer-mfd@400 {
 114                         compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
 115                         reg = <0x400 0x4c>;
 116                         ranges = <0x0 0x400 0x4c>;
 117
 118                         #address-cells = <1>;
 119                         #size-cells = <1>;
 120
 121                         timer@0 {
 122                                 compatible = "brcm,bcm63138-timer";
 123                                 reg = <0x0 0x28>;
 124                         };
 125
 126                         watchdog@28 {
 127                                 compatible = "brcm,bcm6345-wdt";
 128                                 reg = <0x28 0x8>;
 129                         };
 130                 };
 131
 132                 uart0: serial@640 {
 133                         compatible = "brcm,bcm6345-uart";
 134                         reg = <0x640 0x18>;
 135                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 136                         clocks = <&periph_clk>;
 137                         clock-names = "refclk";
 138                         status = "disabled";
 139                 };
 140         };
 141 };