src/arm64/freescale/fsl-ls1043a.dtsi

   1 /*
   2  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
   3  *
   4  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   5  *
   6  * Mingkai Hu <Mingkai.hu@freescale.com>
   7  *
   8  * This file is dual-licensed: you can use it either under the terms
   9  * of the GPLv2 or the X11 license, at your option. Note that this dual
  10  * licensing only applies to this file, and not this project as a
  11  * whole.
  12  *
  13  *  a) This library is free software; you can redistribute it and/or
  14  *     modify it under the terms of the GNU General Public License as
  15  *     published by the Free Software Foundation; either version 2 of the
  16  *     License, or (at your option) any later version.
  17  *
  18  *     This library is distributed in the hope that it will be useful,
  19  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *     GNU General Public License for more details.
  22  *
  23  * Or, alternatively,
  24  *
  25  *  b) Permission is hereby granted, free of charge, to any person
  26  *     obtaining a copy of this software and associated documentation
  27  *     files (the "Software"), to deal in the Software without
  28  *     restriction, including without limitation the rights to use,
  29  *     copy, modify, merge, publish, distribute, sublicense, and/or
  30  *     sell copies of the Software, and to permit persons to whom the
  31  *     Software is furnished to do so, subject to the following
  32  *     conditions:
  33  *
  34  *     The above copyright notice and this permission notice shall be
  35  *     included in all copies or substantial portions of the Software.
  36  *
  37  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  38  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  39  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  40  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  41  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  42  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  43  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  44  *     OTHER DEALINGS IN THE SOFTWARE.
  45  */
  46
  47 #include <dt-bindings/thermal/thermal.h>
  48 #include <dt-bindings/interrupt-controller/arm-gic.h>
  49
  50 / {
  51         compatible = "fsl,ls1043a";
  52         interrupt-parent = <&gic>;
  53         #address-cells = <2>;
  54         #size-cells = <2>;
  55
  56         aliases {
  57                 fman0 = &fman0;
  58                 ethernet0 = &enet0;
  59                 ethernet1 = &enet1;
  60                 ethernet2 = &enet2;
  61                 ethernet3 = &enet3;
  62                 ethernet4 = &enet4;
  63                 ethernet5 = &enet5;
  64                 ethernet6 = &enet6;
  65         };
  66
  67         cpus {
  68                 #address-cells = <1>;
  69                 #size-cells = <0>;
  70
  71                 /*
  72                  * We expect the enable-method for cpu's to be "psci", but this
  73                  * is dependent on the SoC FW, which will fill this in.
  74                  *
  75                  * Currently supported enable-method is psci v0.2
  76                  */
  77                 cpu0: cpu@0 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a53";
  80                         reg = <0x0>;
  81                         clocks = <&clockgen 1 0>;
  82                         next-level-cache = <&l2>;
  83                         #cooling-cells = <2>;
  84                         cpu-idle-states = <&CPU_PH20>;
  85                 };
  86
  87                 cpu1: cpu@1 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a53";
  90                         reg = <0x1>;
  91                         clocks = <&clockgen 1 0>;
  92                         next-level-cache = <&l2>;
  93                         cpu-idle-states = <&CPU_PH20>;
  94                 };
  95
  96                 cpu2: cpu@2 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a53";
  99                         reg = <0x2>;
 100                         clocks = <&clockgen 1 0>;
 101                         next-level-cache = <&l2>;
 102                         cpu-idle-states = <&CPU_PH20>;
 103                 };
 104
 105                 cpu3: cpu@3 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a53";
 108                         reg = <0x3>;
 109                         clocks = <&clockgen 1 0>;
 110                         next-level-cache = <&l2>;
 111                         cpu-idle-states = <&CPU_PH20>;
 112                 };
 113
 114                 l2: l2-cache {
 115                         compatible = "cache";
 116                 };
 117         };
 118
 119         idle-states {
 120                 /*
 121                  * PSCI node is not added default, U-boot will add missing
 122                  * parts if it determines to use PSCI.
 123                  */
 124                 entry-method = "arm,psci";
 125
 126                 CPU_PH20: cpu-ph20 {
 127                         compatible = "arm,idle-state";
 128                         idle-state-name = "PH20";
 129                         arm,psci-suspend-param = <0x0>;
 130                         entry-latency-us = <1000>;
 131                         exit-latency-us = <1000>;
 132                         min-residency-us = <3000>;
 133                 };
 134         };
 135
 136         memory@80000000 {
 137                 device_type = "memory";
 138                 reg = <0x0 0x80000000 0 0x80000000>;
 139                       /* DRAM space 1, size: 2GiB DRAM */
 140         };
 141
 142         reserved-memory {
 143                 #address-cells = <2>;
 144                 #size-cells = <2>;
 145                 ranges;
 146
 147                 bman_fbpr: bman-fbpr {
 148                         compatible = "shared-dma-pool";
 149                         size = <0 0x1000000>;
 150                         alignment = <0 0x1000000>;
 151                         no-map;
 152                 };
 153
 154                 qman_fqd: qman-fqd {
 155                         compatible = "shared-dma-pool";
 156                         size = <0 0x400000>;
 157                         alignment = <0 0x400000>;
 158                         no-map;
 159                 };
 160
 161                 qman_pfdr: qman-pfdr {
 162                         compatible = "shared-dma-pool";
 163                         size = <0 0x2000000>;
 164                         alignment = <0 0x2000000>;
 165                         no-map;
 166                 };
 167         };
 168
 169         sysclk: sysclk {
 170                 compatible = "fixed-clock";
 171                 #clock-cells = <0>;
 172                 clock-frequency = <100000000>;
 173                 clock-output-names = "sysclk";
 174         };
 175
 176         reboot {
 177                 compatible ="syscon-reboot";
 178                 regmap = <&dcfg>;
 179                 offset = <0xb0>;
 180                 mask = <0x02>;
 181         };
 182
 183         thermal-zones {
 184                 cpu_thermal: cpu-thermal {
 185                         polling-delay-passive = <1000>;
 186                         polling-delay = <5000>;
 187
 188                         thermal-sensors = <&tmu 3>;
 189
 190                         trips {
 191                                 cpu_alert: cpu-alert {
 192                                         temperature = <85000>;
 193                                         hysteresis = <2000>;
 194                                         type = "passive";
 195                                 };
 196                                 cpu_crit: cpu-crit {
 197                                         temperature = <95000>;
 198                                         hysteresis = <2000>;
 199                                         type = "critical";
 200                                 };
 201                         };
 202
 203                         cooling-maps {
 204                                 map0 {
 205                                         trip = <&cpu_alert>;
 206                                         cooling-device =
 207                                                 <&cpu0 THERMAL_NO_LIMIT
 208                                                 THERMAL_NO_LIMIT>;
 209                                 };
 210                         };
 211                 };
 212         };
 213
 214         timer {
 215                 compatible = "arm,armv8-timer";
 216                 interrupts = <1 13 0xf08>, /* Physical Secure PPI */
 217                              <1 14 0xf08>, /* Physical Non-Secure PPI */
 218                              <1 11 0xf08>, /* Virtual PPI */
 219                              <1 10 0xf08>; /* Hypervisor PPI */
 220                 fsl,erratum-a008585;
 221         };
 222
 223         pmu {
 224                 compatible = "arm,armv8-pmuv3";
 225                 interrupts = <0 106 0x4>,
 226                              <0 107 0x4>,
 227                              <0 95 0x4>,
 228                              <0 97 0x4>;
 229                 interrupt-affinity = <&cpu0>,
 230                                      <&cpu1>,
 231                                      <&cpu2>,
 232                                      <&cpu3>;
 233         };
 234
 235         gic: interrupt-controller@1400000 {
 236                 compatible = "arm,gic-400";
 237                 #interrupt-cells = <3>;
 238                 interrupt-controller;
 239                 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
 240                       <0x0 0x1402000 0 0x2000>, /* GICC */
 241                       <0x0 0x1404000 0 0x2000>, /* GICH */
 242                       <0x0 0x1406000 0 0x2000>; /* GICV */
 243                 interrupts = <1 9 0xf08>;
 244         };
 245
 246         soc: soc {
 247                 compatible = "simple-bus";
 248                 #address-cells = <2>;
 249                 #size-cells = <2>;
 250                 ranges;
 251
 252                 clockgen: clocking@1ee1000 {
 253                         compatible = "fsl,ls1043a-clockgen";
 254                         reg = <0x0 0x1ee1000 0x0 0x1000>;
 255                         #clock-cells = <2>;
 256                         clocks = <&sysclk>;
 257                 };
 258
 259                 scfg: scfg@1570000 {
 260                         compatible = "fsl,ls1043a-scfg", "syscon";
 261                         reg = <0x0 0x1570000 0x0 0x10000>;
 262                         big-endian;
 263                 };
 264
 265                 crypto: crypto@1700000 {
 266                         compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
 267                                      "fsl,sec-v4.0";
 268                         fsl,sec-era = <3>;
 269                         #address-cells = <1>;
 270                         #size-cells = <1>;
 271                         ranges = <0x0 0x00 0x1700000 0x100000>;
 272                         reg = <0x00 0x1700000 0x0 0x100000>;
 273                         interrupts = <0 75 0x4>;
 274
 275                         sec_jr0: jr@10000 {
 276                                 compatible = "fsl,sec-v5.4-job-ring",
 277                                              "fsl,sec-v5.0-job-ring",
 278                                              "fsl,sec-v4.0-job-ring";
 279                                 reg        = <0x10000 0x10000>;
 280                                 interrupts = <0 71 0x4>;
 281                         };
 282
 283                         sec_jr1: jr@20000 {
 284                                 compatible = "fsl,sec-v5.4-job-ring",
 285                                              "fsl,sec-v5.0-job-ring",
 286                                              "fsl,sec-v4.0-job-ring";
 287                                 reg        = <0x20000 0x10000>;
 288                                 interrupts = <0 72 0x4>;
 289                         };
 290
 291                         sec_jr2: jr@30000 {
 292                                 compatible = "fsl,sec-v5.4-job-ring",
 293                                              "fsl,sec-v5.0-job-ring",
 294                                              "fsl,sec-v4.0-job-ring";
 295                                 reg        = <0x30000 0x10000>;
 296                                 interrupts = <0 73 0x4>;
 297                         };
 298
 299                         sec_jr3: jr@40000 {
 300                                 compatible = "fsl,sec-v5.4-job-ring",
 301                                              "fsl,sec-v5.0-job-ring",
 302                                              "fsl,sec-v4.0-job-ring";
 303                                 reg        = <0x40000 0x10000>;
 304                                 interrupts = <0 74 0x4>;
 305                         };
 306                 };
 307
 308                 dcfg: dcfg@1ee0000 {
 309                         compatible = "fsl,ls1043a-dcfg", "syscon";
 310                         reg = <0x0 0x1ee0000 0x0 0x10000>;
 311                         big-endian;
 312                 };
 313
 314                 ifc: ifc@1530000 {
 315                         compatible = "fsl,ifc", "simple-bus";
 316                         reg = <0x0 0x1530000 0x0 0x10000>;
 317                         big-endian;
 318                         interrupts = <0 43 0x4>;
 319                 };
 320
 321                 qspi: quadspi@1550000 {
 322                         compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
 323                         #address-cells = <1>;
 324                         #size-cells = <0>;
 325                         reg = <0x0 0x1550000 0x0 0x10000>,
 326                                 <0x0 0x40000000 0x0 0x4000000>;
 327                         reg-names = "QuadSPI", "QuadSPI-memory";
 328                         interrupts = <0 99 0x4>;
 329                         clock-names = "qspi_en", "qspi";
 330                         clocks = <&clockgen 4 0>, <&clockgen 4 0>;
 331                         big-endian;
 332                         status = "disabled";
 333                 };
 334
 335                 esdhc: esdhc@1560000 {
 336                         compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
 337                         reg = <0x0 0x1560000 0x0 0x10000>;
 338                         interrupts = <0 62 0x4>;
 339                         clock-frequency = <0>;
 340                         voltage-ranges = <1800 1800 3300 3300>;
 341                         sdhci,auto-cmd12;
 342                         big-endian;
 343                         bus-width = <4>;
 344                 };
 345
 346                 ddr: memory-controller@1080000 {
 347                         compatible = "fsl,qoriq-memory-controller";
 348                         reg = <0x0 0x1080000 0x0 0x1000>;
 349                         interrupts = <0 144 0x4>;
 350                         big-endian;
 351                 };
 352
 353                 tmu: tmu@1f00000 {
 354                         compatible = "fsl,qoriq-tmu";
 355                         reg = <0x0 0x1f00000 0x0 0x10000>;
 356                         interrupts = <0 33 0x4>;
 357                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
 358                         fsl,tmu-calibration = <0x00000000 0x00000026
 359                                                0x00000001 0x0000002d
 360                                                0x00000002 0x00000032
 361                                                0x00000003 0x00000039
 362                                                0x00000004 0x0000003f
 363                                                0x00000005 0x00000046
 364                                                0x00000006 0x0000004d
 365                                                0x00000007 0x00000054
 366                                                0x00000008 0x0000005a
 367                                                0x00000009 0x00000061
 368                                                0x0000000a 0x0000006a
 369                                                0x0000000b 0x00000071
 370
 371                                                0x00010000 0x00000025
 372                                                0x00010001 0x0000002c
 373                                                0x00010002 0x00000035
 374                                                0x00010003 0x0000003d
 375                                                0x00010004 0x00000045
 376                                                0x00010005 0x0000004e
 377                                                0x00010006 0x00000057
 378                                                0x00010007 0x00000061
 379                                                0x00010008 0x0000006b
 380                                                0x00010009 0x00000076
 381
 382                                                0x00020000 0x00000029
 383                                                0x00020001 0x00000033
 384                                                0x00020002 0x0000003d
 385                                                0x00020003 0x00000049
 386                                                0x00020004 0x00000056
 387                                                0x00020005 0x00000061
 388                                                0x00020006 0x0000006d
 389
 390                                                0x00030000 0x00000021
 391                                                0x00030001 0x0000002a
 392                                                0x00030002 0x0000003c
 393                                                0x00030003 0x0000004e>;
 394                         #thermal-sensor-cells = <1>;
 395                 };
 396
 397                 qman: qman@1880000 {
 398                         compatible = "fsl,qman";
 399                         reg = <0x0 0x1880000 0x0 0x10000>;
 400                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 401                         memory-region = <&qman_fqd &qman_pfdr>;
 402                 };
 403
 404                 bman: bman@1890000 {
 405                         compatible = "fsl,bman";
 406                         reg = <0x0 0x1890000 0x0 0x10000>;
 407                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 408                         memory-region = <&bman_fbpr>;
 409                 };
 410
 411                 bportals: bman-portals@508000000 {
 412                         ranges = <0x0 0x5 0x08000000 0x8000000>;
 413                 };
 414
 415                 qportals: qman-portals@500000000 {
 416                         ranges = <0x0 0x5 0x00000000 0x8000000>;
 417                 };
 418
 419                 dspi0: dspi@2100000 {
 420                         compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
 421                         #address-cells = <1>;
 422                         #size-cells = <0>;
 423                         reg = <0x0 0x2100000 0x0 0x10000>;
 424                         interrupts = <0 64 0x4>;
 425                         clock-names = "dspi";
 426                         clocks = <&clockgen 4 0>;
 427                         spi-num-chipselects = <5>;
 428                         big-endian;
 429                         status = "disabled";
 430                 };
 431
 432                 dspi1: dspi@2110000 {
 433                         compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
 434                         #address-cells = <1>;
 435                         #size-cells = <0>;
 436                         reg = <0x0 0x2110000 0x0 0x10000>;
 437                         interrupts = <0 65 0x4>;
 438                         clock-names = "dspi";
 439                         clocks = <&clockgen 4 0>;
 440                         spi-num-chipselects = <5>;
 441                         big-endian;
 442                         status = "disabled";
 443                 };
 444
 445                 i2c0: i2c@2180000 {
 446                         compatible = "fsl,vf610-i2c";
 447                         #address-cells = <1>;
 448                         #size-cells = <0>;
 449                         reg = <0x0 0x2180000 0x0 0x10000>;
 450                         interrupts = <0 56 0x4>;
 451                         clock-names = "i2c";
 452                         clocks = <&clockgen 4 0>;
 453                         dmas = <&edma0 1 39>,
 454                                <&edma0 1 38>;
 455                         dma-names = "tx", "rx";
 456                         status = "disabled";
 457                 };
 458
 459                 i2c1: i2c@2190000 {
 460                         compatible = "fsl,vf610-i2c";
 461                         #address-cells = <1>;
 462                         #size-cells = <0>;
 463                         reg = <0x0 0x2190000 0x0 0x10000>;
 464                         interrupts = <0 57 0x4>;
 465                         clock-names = "i2c";
 466                         clocks = <&clockgen 4 0>;
 467                         status = "disabled";
 468                 };
 469
 470                 i2c2: i2c@21a0000 {
 471                         compatible = "fsl,vf610-i2c";
 472                         #address-cells = <1>;
 473                         #size-cells = <0>;
 474                         reg = <0x0 0x21a0000 0x0 0x10000>;
 475                         interrupts = <0 58 0x4>;
 476                         clock-names = "i2c";
 477                         clocks = <&clockgen 4 0>;
 478                         status = "disabled";
 479                 };
 480
 481                 i2c3: i2c@21b0000 {
 482                         compatible = "fsl,vf610-i2c";
 483                         #address-cells = <1>;
 484                         #size-cells = <0>;
 485                         reg = <0x0 0x21b0000 0x0 0x10000>;
 486                         interrupts = <0 59 0x4>;
 487                         clock-names = "i2c";
 488                         clocks = <&clockgen 4 0>;
 489                         status = "disabled";
 490                 };
 491
 492                 duart0: serial@21c0500 {
 493                         compatible = "fsl,ns16550", "ns16550a";
 494                         reg = <0x00 0x21c0500 0x0 0x100>;
 495                         interrupts = <0 54 0x4>;
 496                         clocks = <&clockgen 4 0>;
 497                 };
 498
 499                 duart1: serial@21c0600 {
 500                         compatible = "fsl,ns16550", "ns16550a";
 501                         reg = <0x00 0x21c0600 0x0 0x100>;
 502                         interrupts = <0 54 0x4>;
 503                         clocks = <&clockgen 4 0>;
 504                 };
 505
 506                 duart2: serial@21d0500 {
 507                         compatible = "fsl,ns16550", "ns16550a";
 508                         reg = <0x0 0x21d0500 0x0 0x100>;
 509                         interrupts = <0 55 0x4>;
 510                         clocks = <&clockgen 4 0>;
 511                 };
 512
 513                 duart3: serial@21d0600 {
 514                         compatible = "fsl,ns16550", "ns16550a";
 515                         reg = <0x0 0x21d0600 0x0 0x100>;
 516                         interrupts = <0 55 0x4>;
 517                         clocks = <&clockgen 4 0>;
 518                 };
 519
 520                 gpio1: gpio@2300000 {
 521                         compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
 522                         reg = <0x0 0x2300000 0x0 0x10000>;
 523                         interrupts = <0 66 0x4>;
 524                         gpio-controller;
 525                         #gpio-cells = <2>;
 526                         interrupt-controller;
 527                         #interrupt-cells = <2>;
 528                 };
 529
 530                 gpio2: gpio@2310000 {
 531                         compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
 532                         reg = <0x0 0x2310000 0x0 0x10000>;
 533                         interrupts = <0 67 0x4>;
 534                         gpio-controller;
 535                         #gpio-cells = <2>;
 536                         interrupt-controller;
 537                         #interrupt-cells = <2>;
 538                 };
 539
 540                 gpio3: gpio@2320000 {
 541                         compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
 542                         reg = <0x0 0x2320000 0x0 0x10000>;
 543                         interrupts = <0 68 0x4>;
 544                         gpio-controller;
 545                         #gpio-cells = <2>;
 546                         interrupt-controller;
 547                         #interrupt-cells = <2>;
 548                 };
 549
 550                 gpio4: gpio@2330000 {
 551                         compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
 552                         reg = <0x0 0x2330000 0x0 0x10000>;
 553                         interrupts = <0 134 0x4>;
 554                         gpio-controller;
 555                         #gpio-cells = <2>;
 556                         interrupt-controller;
 557                         #interrupt-cells = <2>;
 558                 };
 559
 560                 lpuart0: serial@2950000 {
 561                         compatible = "fsl,ls1021a-lpuart";
 562                         reg = <0x0 0x2950000 0x0 0x1000>;
 563                         interrupts = <0 48 0x4>;
 564                         clocks = <&clockgen 0 0>;
 565                         clock-names = "ipg";
 566                         status = "disabled";
 567                 };
 568
 569                 lpuart1: serial@2960000 {
 570                         compatible = "fsl,ls1021a-lpuart";
 571                         reg = <0x0 0x2960000 0x0 0x1000>;
 572                         interrupts = <0 49 0x4>;
 573                         clocks = <&clockgen 4 0>;
 574                         clock-names = "ipg";
 575                         status = "disabled";
 576                 };
 577
 578                 lpuart2: serial@2970000 {
 579                         compatible = "fsl,ls1021a-lpuart";
 580                         reg = <0x0 0x2970000 0x0 0x1000>;
 581                         interrupts = <0 50 0x4>;
 582                         clocks = <&clockgen 4 0>;
 583                         clock-names = "ipg";
 584                         status = "disabled";
 585                 };
 586
 587                 lpuart3: serial@2980000 {
 588                         compatible = "fsl,ls1021a-lpuart";
 589                         reg = <0x0 0x2980000 0x0 0x1000>;
 590                         interrupts = <0 51 0x4>;
 591                         clocks = <&clockgen 4 0>;
 592                         clock-names = "ipg";
 593                         status = "disabled";
 594                 };
 595
 596                 lpuart4: serial@2990000 {
 597                         compatible = "fsl,ls1021a-lpuart";
 598                         reg = <0x0 0x2990000 0x0 0x1000>;
 599                         interrupts = <0 52 0x4>;
 600                         clocks = <&clockgen 4 0>;
 601                         clock-names = "ipg";
 602                         status = "disabled";
 603                 };
 604
 605                 lpuart5: serial@29a0000 {
 606                         compatible = "fsl,ls1021a-lpuart";
 607                         reg = <0x0 0x29a0000 0x0 0x1000>;
 608                         interrupts = <0 53 0x4>;
 609                         clocks = <&clockgen 4 0>;
 610                         clock-names = "ipg";
 611                         status = "disabled";
 612                 };
 613
 614                 wdog0: wdog@2ad0000 {
 615                         compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
 616                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 617                         interrupts = <0 83 0x4>;
 618                         clocks = <&clockgen 4 0>;
 619                         clock-names = "wdog";
 620                         big-endian;
 621                 };
 622
 623                 edma0: edma@2c00000 {
 624                         #dma-cells = <2>;
 625                         compatible = "fsl,vf610-edma";
 626                         reg = <0x0 0x2c00000 0x0 0x10000>,
 627                               <0x0 0x2c10000 0x0 0x10000>,
 628                               <0x0 0x2c20000 0x0 0x10000>;
 629                         interrupts = <0 103 0x4>,
 630                                      <0 103 0x4>;
 631                         interrupt-names = "edma-tx", "edma-err";
 632                         dma-channels = <32>;
 633                         big-endian;
 634                         clock-names = "dmamux0", "dmamux1";
 635                         clocks = <&clockgen 4 0>,
 636                                  <&clockgen 4 0>;
 637                 };
 638
 639                 usb0: usb3@2f00000 {
 640                         compatible = "snps,dwc3";
 641                         reg = <0x0 0x2f00000 0x0 0x10000>;
 642                         interrupts = <0 60 0x4>;
 643                         dr_mode = "host";
 644                         snps,quirk-frame-length-adjustment = <0x20>;
 645                         snps,dis_rxdet_inp3_quirk;
 646                 };
 647
 648                 usb1: usb3@3000000 {
 649                         compatible = "snps,dwc3";
 650                         reg = <0x0 0x3000000 0x0 0x10000>;
 651                         interrupts = <0 61 0x4>;
 652                         dr_mode = "host";
 653                         snps,quirk-frame-length-adjustment = <0x20>;
 654                         snps,dis_rxdet_inp3_quirk;
 655                 };
 656
 657                 usb2: usb3@3100000 {
 658                         compatible = "snps,dwc3";
 659                         reg = <0x0 0x3100000 0x0 0x10000>;
 660                         interrupts = <0 63 0x4>;
 661                         dr_mode = "host";
 662                         snps,quirk-frame-length-adjustment = <0x20>;
 663                         snps,dis_rxdet_inp3_quirk;
 664                 };
 665
 666                 sata: sata@3200000 {
 667                         compatible = "fsl,ls1043a-ahci";
 668                         reg = <0x0 0x3200000 0x0 0x10000>,
 669                                 <0x0 0x20140520 0x0 0x4>;
 670                         reg-names = "ahci", "sata-ecc";
 671                         interrupts = <0 69 0x4>;
 672                         clocks = <&clockgen 4 0>;
 673                         dma-coherent;
 674                 };
 675
 676                 msi1: msi-controller1@1571000 {
 677                         compatible = "fsl,ls1043a-msi";
 678                         reg = <0x0 0x1571000 0x0 0x8>;
 679                         msi-controller;
 680                         interrupts = <0 116 0x4>;
 681                 };
 682
 683                 msi2: msi-controller2@1572000 {
 684                         compatible = "fsl,ls1043a-msi";
 685                         reg = <0x0 0x1572000 0x0 0x8>;
 686                         msi-controller;
 687                         interrupts = <0 126 0x4>;
 688                 };
 689
 690                 msi3: msi-controller3@1573000 {
 691                         compatible = "fsl,ls1043a-msi";
 692                         reg = <0x0 0x1573000 0x0 0x8>;
 693                         msi-controller;
 694                         interrupts = <0 160 0x4>;
 695                 };
 696
 697                 pcie@3400000 {
 698                         compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
 699                         reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 700                                0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 701                         reg-names = "regs", "config";
 702                         interrupts = <0 118 0x4>, /* controller interrupt */
 703                                      <0 117 0x4>; /* PME interrupt */
 704                         interrupt-names = "intr", "pme";
 705                         #address-cells = <3>;
 706                         #size-cells = <2>;
 707                         device_type = "pci";
 708                         dma-coherent;
 709                         num-lanes = <4>;
 710                         bus-range = <0x0 0xff>;
 711                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
 712                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 713                         msi-parent = <&msi1>, <&msi2>, <&msi3>;
 714                         #interrupt-cells = <1>;
 715                         interrupt-map-mask = <0 0 0 7>;
 716                         interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
 717                                         <0000 0 0 2 &gic 0 111 0x4>,
 718                                         <0000 0 0 3 &gic 0 112 0x4>,
 719                                         <0000 0 0 4 &gic 0 113 0x4>;
 720                 };
 721
 722                 pcie@3500000 {
 723                         compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
 724                         reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 725                                0x48 0x00000000 0x0 0x00002000>; /* configuration space */
 726                         reg-names = "regs", "config";
 727                         interrupts = <0 128 0x4>,
 728                                      <0 127 0x4>;
 729                         interrupt-names = "intr", "pme";
 730                         #address-cells = <3>;
 731                         #size-cells = <2>;
 732                         device_type = "pci";
 733                         dma-coherent;
 734                         num-lanes = <2>;
 735                         bus-range = <0x0 0xff>;
 736                         ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
 737                                   0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 738                         msi-parent = <&msi1>, <&msi2>, <&msi3>;
 739                         #interrupt-cells = <1>;
 740                         interrupt-map-mask = <0 0 0 7>;
 741                         interrupt-map = <0000 0 0 1 &gic 0 120  0x4>,
 742                                         <0000 0 0 2 &gic 0 121 0x4>,
 743                                         <0000 0 0 3 &gic 0 122 0x4>,
 744                                         <0000 0 0 4 &gic 0 123 0x4>;
 745                 };
 746
 747                 pcie@3600000 {
 748                         compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
 749                         reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 750                                0x50 0x00000000 0x0 0x00002000>; /* configuration space */
 751                         reg-names = "regs", "config";
 752                         interrupts = <0 162 0x4>,
 753                                      <0 161 0x4>;
 754                         interrupt-names = "intr", "pme";
 755                         #address-cells = <3>;
 756                         #size-cells = <2>;
 757                         device_type = "pci";
 758                         dma-coherent;
 759                         num-lanes = <2>;
 760                         bus-range = <0x0 0xff>;
 761                         ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
 762                                   0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 763                         msi-parent = <&msi1>, <&msi2>, <&msi3>;
 764                         #interrupt-cells = <1>;
 765                         interrupt-map-mask = <0 0 0 7>;
 766                         interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
 767                                         <0000 0 0 2 &gic 0 155 0x4>,
 768                                         <0000 0 0 3 &gic 0 156 0x4>,
 769                                         <0000 0 0 4 &gic 0 157 0x4>;
 770                 };
 771         };
 772
 773         firmware {
 774                 optee {
 775                         compatible = "linaro,optee-tz";
 776                         method = "smc";
 777                 };
 778         };
 779
 780 };
 781
 782 #include "qoriq-qman-portals.dtsi"
 783 #include "qoriq-bman-portals.dtsi"