src/arm64/freescale/fsl-lx2160a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 //
   3 // Device Tree Include file for Layerscape-LX2160A family SoC.
   4 //
   5 // Copyright 2018 NXP
   6
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/thermal/thermal.h>
  10
  11 /memreserve/ 0x80000000 0x00010000;
  12
  13 / {
  14         compatible = "fsl,lx2160a";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 // 8 clusters having 2 Cortex-A72 cores each
  24                 cpu0: cpu@0 {
  25                         device_type = "cpu";
  26                         compatible = "arm,cortex-a72";
  27                         enable-method = "psci";
  28                         reg = <0x0>;
  29                         clocks = <&clockgen 1 0>;
  30                         d-cache-size = <0x8000>;
  31                         d-cache-line-size = <64>;
  32                         d-cache-sets = <128>;
  33                         i-cache-size = <0xC000>;
  34                         i-cache-line-size = <64>;
  35                         i-cache-sets = <192>;
  36                         next-level-cache = <&cluster0_l2>;
  37                         cpu-idle-states = <&cpu_pw15>;
  38                         #cooling-cells = <2>;
  39                 };
  40
  41                 cpu1: cpu@1 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a72";
  44                         enable-method = "psci";
  45                         reg = <0x1>;
  46                         clocks = <&clockgen 1 0>;
  47                         d-cache-size = <0x8000>;
  48                         d-cache-line-size = <64>;
  49                         d-cache-sets = <128>;
  50                         i-cache-size = <0xC000>;
  51                         i-cache-line-size = <64>;
  52                         i-cache-sets = <192>;
  53                         next-level-cache = <&cluster0_l2>;
  54                         cpu-idle-states = <&cpu_pw15>;
  55                         #cooling-cells = <2>;
  56                 };
  57
  58                 cpu100: cpu@100 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a72";
  61                         enable-method = "psci";
  62                         reg = <0x100>;
  63                         clocks = <&clockgen 1 1>;
  64                         d-cache-size = <0x8000>;
  65                         d-cache-line-size = <64>;
  66                         d-cache-sets = <128>;
  67                         i-cache-size = <0xC000>;
  68                         i-cache-line-size = <64>;
  69                         i-cache-sets = <192>;
  70                         next-level-cache = <&cluster1_l2>;
  71                         cpu-idle-states = <&cpu_pw15>;
  72                         #cooling-cells = <2>;
  73                 };
  74
  75                 cpu101: cpu@101 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a72";
  78                         enable-method = "psci";
  79                         reg = <0x101>;
  80                         clocks = <&clockgen 1 1>;
  81                         d-cache-size = <0x8000>;
  82                         d-cache-line-size = <64>;
  83                         d-cache-sets = <128>;
  84                         i-cache-size = <0xC000>;
  85                         i-cache-line-size = <64>;
  86                         i-cache-sets = <192>;
  87                         next-level-cache = <&cluster1_l2>;
  88                         cpu-idle-states = <&cpu_pw15>;
  89                         #cooling-cells = <2>;
  90                 };
  91
  92                 cpu200: cpu@200 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a72";
  95                         enable-method = "psci";
  96                         reg = <0x200>;
  97                         clocks = <&clockgen 1 2>;
  98                         d-cache-size = <0x8000>;
  99                         d-cache-line-size = <64>;
 100                         d-cache-sets = <128>;
 101                         i-cache-size = <0xC000>;
 102                         i-cache-line-size = <64>;
 103                         i-cache-sets = <192>;
 104                         next-level-cache = <&cluster2_l2>;
 105                         cpu-idle-states = <&cpu_pw15>;
 106                         #cooling-cells = <2>;
 107                 };
 108
 109                 cpu201: cpu@201 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a72";
 112                         enable-method = "psci";
 113                         reg = <0x201>;
 114                         clocks = <&clockgen 1 2>;
 115                         d-cache-size = <0x8000>;
 116                         d-cache-line-size = <64>;
 117                         d-cache-sets = <128>;
 118                         i-cache-size = <0xC000>;
 119                         i-cache-line-size = <64>;
 120                         i-cache-sets = <192>;
 121                         next-level-cache = <&cluster2_l2>;
 122                         cpu-idle-states = <&cpu_pw15>;
 123                         #cooling-cells = <2>;
 124                 };
 125
 126                 cpu300: cpu@300 {
 127                         device_type = "cpu";
 128                         compatible = "arm,cortex-a72";
 129                         enable-method = "psci";
 130                         reg = <0x300>;
 131                         clocks = <&clockgen 1 3>;
 132                         d-cache-size = <0x8000>;
 133                         d-cache-line-size = <64>;
 134                         d-cache-sets = <128>;
 135                         i-cache-size = <0xC000>;
 136                         i-cache-line-size = <64>;
 137                         i-cache-sets = <192>;
 138                         next-level-cache = <&cluster3_l2>;
 139                         cpu-idle-states = <&cpu_pw15>;
 140                         #cooling-cells = <2>;
 141                 };
 142
 143                 cpu301: cpu@301 {
 144                         device_type = "cpu";
 145                         compatible = "arm,cortex-a72";
 146                         enable-method = "psci";
 147                         reg = <0x301>;
 148                         clocks = <&clockgen 1 3>;
 149                         d-cache-size = <0x8000>;
 150                         d-cache-line-size = <64>;
 151                         d-cache-sets = <128>;
 152                         i-cache-size = <0xC000>;
 153                         i-cache-line-size = <64>;
 154                         i-cache-sets = <192>;
 155                         next-level-cache = <&cluster3_l2>;
 156                         cpu-idle-states = <&cpu_pw15>;
 157                         #cooling-cells = <2>;
 158                 };
 159
 160                 cpu400: cpu@400 {
 161                         device_type = "cpu";
 162                         compatible = "arm,cortex-a72";
 163                         enable-method = "psci";
 164                         reg = <0x400>;
 165                         clocks = <&clockgen 1 4>;
 166                         d-cache-size = <0x8000>;
 167                         d-cache-line-size = <64>;
 168                         d-cache-sets = <128>;
 169                         i-cache-size = <0xC000>;
 170                         i-cache-line-size = <64>;
 171                         i-cache-sets = <192>;
 172                         next-level-cache = <&cluster4_l2>;
 173                         cpu-idle-states = <&cpu_pw15>;
 174                         #cooling-cells = <2>;
 175                 };
 176
 177                 cpu401: cpu@401 {
 178                         device_type = "cpu";
 179                         compatible = "arm,cortex-a72";
 180                         enable-method = "psci";
 181                         reg = <0x401>;
 182                         clocks = <&clockgen 1 4>;
 183                         d-cache-size = <0x8000>;
 184                         d-cache-line-size = <64>;
 185                         d-cache-sets = <128>;
 186                         i-cache-size = <0xC000>;
 187                         i-cache-line-size = <64>;
 188                         i-cache-sets = <192>;
 189                         next-level-cache = <&cluster4_l2>;
 190                         cpu-idle-states = <&cpu_pw15>;
 191                         #cooling-cells = <2>;
 192                 };
 193
 194                 cpu500: cpu@500 {
 195                         device_type = "cpu";
 196                         compatible = "arm,cortex-a72";
 197                         enable-method = "psci";
 198                         reg = <0x500>;
 199                         clocks = <&clockgen 1 5>;
 200                         d-cache-size = <0x8000>;
 201                         d-cache-line-size = <64>;
 202                         d-cache-sets = <128>;
 203                         i-cache-size = <0xC000>;
 204                         i-cache-line-size = <64>;
 205                         i-cache-sets = <192>;
 206                         next-level-cache = <&cluster5_l2>;
 207                         cpu-idle-states = <&cpu_pw15>;
 208                         #cooling-cells = <2>;
 209                 };
 210
 211                 cpu501: cpu@501 {
 212                         device_type = "cpu";
 213                         compatible = "arm,cortex-a72";
 214                         enable-method = "psci";
 215                         reg = <0x501>;
 216                         clocks = <&clockgen 1 5>;
 217                         d-cache-size = <0x8000>;
 218                         d-cache-line-size = <64>;
 219                         d-cache-sets = <128>;
 220                         i-cache-size = <0xC000>;
 221                         i-cache-line-size = <64>;
 222                         i-cache-sets = <192>;
 223                         next-level-cache = <&cluster5_l2>;
 224                         cpu-idle-states = <&cpu_pw15>;
 225                         #cooling-cells = <2>;
 226                 };
 227
 228                 cpu600: cpu@600 {
 229                         device_type = "cpu";
 230                         compatible = "arm,cortex-a72";
 231                         enable-method = "psci";
 232                         reg = <0x600>;
 233                         clocks = <&clockgen 1 6>;
 234                         d-cache-size = <0x8000>;
 235                         d-cache-line-size = <64>;
 236                         d-cache-sets = <128>;
 237                         i-cache-size = <0xC000>;
 238                         i-cache-line-size = <64>;
 239                         i-cache-sets = <192>;
 240                         next-level-cache = <&cluster6_l2>;
 241                         cpu-idle-states = <&cpu_pw15>;
 242                         #cooling-cells = <2>;
 243                 };
 244
 245                 cpu601: cpu@601 {
 246                         device_type = "cpu";
 247                         compatible = "arm,cortex-a72";
 248                         enable-method = "psci";
 249                         reg = <0x601>;
 250                         clocks = <&clockgen 1 6>;
 251                         d-cache-size = <0x8000>;
 252                         d-cache-line-size = <64>;
 253                         d-cache-sets = <128>;
 254                         i-cache-size = <0xC000>;
 255                         i-cache-line-size = <64>;
 256                         i-cache-sets = <192>;
 257                         next-level-cache = <&cluster6_l2>;
 258                         cpu-idle-states = <&cpu_pw15>;
 259                         #cooling-cells = <2>;
 260                 };
 261
 262                 cpu700: cpu@700 {
 263                         device_type = "cpu";
 264                         compatible = "arm,cortex-a72";
 265                         enable-method = "psci";
 266                         reg = <0x700>;
 267                         clocks = <&clockgen 1 7>;
 268                         d-cache-size = <0x8000>;
 269                         d-cache-line-size = <64>;
 270                         d-cache-sets = <128>;
 271                         i-cache-size = <0xC000>;
 272                         i-cache-line-size = <64>;
 273                         i-cache-sets = <192>;
 274                         next-level-cache = <&cluster7_l2>;
 275                         cpu-idle-states = <&cpu_pw15>;
 276                         #cooling-cells = <2>;
 277                 };
 278
 279                 cpu701: cpu@701 {
 280                         device_type = "cpu";
 281                         compatible = "arm,cortex-a72";
 282                         enable-method = "psci";
 283                         reg = <0x701>;
 284                         clocks = <&clockgen 1 7>;
 285                         d-cache-size = <0x8000>;
 286                         d-cache-line-size = <64>;
 287                         d-cache-sets = <128>;
 288                         i-cache-size = <0xC000>;
 289                         i-cache-line-size = <64>;
 290                         i-cache-sets = <192>;
 291                         next-level-cache = <&cluster7_l2>;
 292                         cpu-idle-states = <&cpu_pw15>;
 293                         #cooling-cells = <2>;
 294                 };
 295
 296                 cluster0_l2: l2-cache0 {
 297                         compatible = "cache";
 298                         cache-size = <0x100000>;
 299                         cache-line-size = <64>;
 300                         cache-sets = <1024>;
 301                         cache-level = <2>;
 302                 };
 303
 304                 cluster1_l2: l2-cache1 {
 305                         compatible = "cache";
 306                         cache-size = <0x100000>;
 307                         cache-line-size = <64>;
 308                         cache-sets = <1024>;
 309                         cache-level = <2>;
 310                 };
 311
 312                 cluster2_l2: l2-cache2 {
 313                         compatible = "cache";
 314                         cache-size = <0x100000>;
 315                         cache-line-size = <64>;
 316                         cache-sets = <1024>;
 317                         cache-level = <2>;
 318                 };
 319
 320                 cluster3_l2: l2-cache3 {
 321                         compatible = "cache";
 322                         cache-size = <0x100000>;
 323                         cache-line-size = <64>;
 324                         cache-sets = <1024>;
 325                         cache-level = <2>;
 326                 };
 327
 328                 cluster4_l2: l2-cache4 {
 329                         compatible = "cache";
 330                         cache-size = <0x100000>;
 331                         cache-line-size = <64>;
 332                         cache-sets = <1024>;
 333                         cache-level = <2>;
 334                 };
 335
 336                 cluster5_l2: l2-cache5 {
 337                         compatible = "cache";
 338                         cache-size = <0x100000>;
 339                         cache-line-size = <64>;
 340                         cache-sets = <1024>;
 341                         cache-level = <2>;
 342                 };
 343
 344                 cluster6_l2: l2-cache6 {
 345                         compatible = "cache";
 346                         cache-size = <0x100000>;
 347                         cache-line-size = <64>;
 348                         cache-sets = <1024>;
 349                         cache-level = <2>;
 350                 };
 351
 352                 cluster7_l2: l2-cache7 {
 353                         compatible = "cache";
 354                         cache-size = <0x100000>;
 355                         cache-line-size = <64>;
 356                         cache-sets = <1024>;
 357                         cache-level = <2>;
 358                 };
 359
 360                 cpu_pw15: cpu-pw15 {
 361                         compatible = "arm,idle-state";
 362                         idle-state-name = "PW15";
 363                         arm,psci-suspend-param = <0x0>;
 364                         entry-latency-us = <2000>;
 365                         exit-latency-us = <2000>;
 366                         min-residency-us = <6000>;
 367                   };
 368         };
 369
 370         gic: interrupt-controller@6000000 {
 371                 compatible = "arm,gic-v3";
 372                 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
 373                         <0x0 0x06200000 0 0x200000>, // GICR (RD_base +
 374                                                      // SGI_base)
 375                         <0x0 0x0c0c0000 0 0x2000>, // GICC
 376                         <0x0 0x0c0d0000 0 0x1000>, // GICH
 377                         <0x0 0x0c0e0000 0 0x20000>; // GICV
 378                 #interrupt-cells = <3>;
 379                 #address-cells = <2>;
 380                 #size-cells = <2>;
 381                 ranges;
 382                 interrupt-controller;
 383                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 384
 385                 its: gic-its@6020000 {
 386                         compatible = "arm,gic-v3-its";
 387                         msi-controller;
 388                         reg = <0x0 0x6020000 0 0x20000>;
 389                 };
 390         };
 391
 392         timer {
 393                 compatible = "arm,armv8-timer";
 394                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
 395                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
 396                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
 397                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
 398         };
 399
 400         pmu {
 401                 compatible = "arm,cortex-a72-pmu";
 402                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 403         };
 404
 405         psci {
 406                 compatible = "arm,psci-0.2";
 407                 method = "smc";
 408         };
 409
 410         memory@80000000 {
 411                 // DRAM space - 1, size : 2 GB DRAM
 412                 device_type = "memory";
 413                 reg = <0x00000000 0x80000000 0 0x80000000>;
 414         };
 415
 416         ddr1: memory-controller@1080000 {
 417                 compatible = "fsl,qoriq-memory-controller";
 418                 reg = <0x0 0x1080000 0x0 0x1000>;
 419                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 420                 little-endian;
 421         };
 422
 423         ddr2: memory-controller@1090000 {
 424                 compatible = "fsl,qoriq-memory-controller";
 425                 reg = <0x0 0x1090000 0x0 0x1000>;
 426                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 427                 little-endian;
 428         };
 429
 430         // One clock unit-sysclk node which bootloader require during DT fix-up
 431         sysclk: sysclk {
 432                 compatible = "fixed-clock";
 433                 #clock-cells = <0>;
 434                 clock-frequency = <100000000>; // fixed up by bootloader
 435                 clock-output-names = "sysclk";
 436         };
 437
 438         thermal-zones {
 439                 cluster6-7 {
 440                         polling-delay-passive = <1000>;
 441                         polling-delay = <5000>;
 442                         thermal-sensors = <&tmu 0>;
 443
 444                         trips {
 445                                 cluster6_7_alert: cluster6-7-alert {
 446                                         temperature = <85000>;
 447                                         hysteresis = <2000>;
 448                                         type = "passive";
 449                                 };
 450
 451                                 cluster6_7_crit: cluster6-7-crit {
 452                                         temperature = <95000>;
 453                                         hysteresis = <2000>;
 454                                         type = "critical";
 455                                 };
 456                         };
 457
 458                         cooling-maps {
 459                                 map0 {
 460                                         trip = <&cluster6_7_alert>;
 461                                         cooling-device =
 462                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 463                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 464                                                 <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 465                                                 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 466                                                 <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 467                                                 <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 468                                                 <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 469                                                 <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 470                                                 <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 471                                                 <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 472                                                 <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 473                                                 <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 474                                                 <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 475                                                 <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 476                                                 <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 477                                                 <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 478                                 };
 479                         };
 480                 };
 481
 482                 ddr-cluster5 {
 483                         polling-delay-passive = <1000>;
 484                         polling-delay = <5000>;
 485                         thermal-sensors = <&tmu 1>;
 486
 487                         trips {
 488                                 ddr-cluster5-alert {
 489                                         temperature = <85000>;
 490                                         hysteresis = <2000>;
 491                                         type = "passive";
 492                                 };
 493
 494                                 ddr-cluster5-crit {
 495                                         temperature = <95000>;
 496                                         hysteresis = <2000>;
 497                                         type = "critical";
 498                                 };
 499                         };
 500                 };
 501
 502                 wriop {
 503                         polling-delay-passive = <1000>;
 504                         polling-delay = <5000>;
 505                         thermal-sensors = <&tmu 2>;
 506
 507                         trips {
 508                                 wriop-alert {
 509                                         temperature = <85000>;
 510                                         hysteresis = <2000>;
 511                                         type = "passive";
 512                                 };
 513
 514                                 wriop-crit {
 515                                         temperature = <95000>;
 516                                         hysteresis = <2000>;
 517                                         type = "critical";
 518                                 };
 519                         };
 520                 };
 521
 522                 dce-qbman-hsio2 {
 523                         polling-delay-passive = <1000>;
 524                         polling-delay = <5000>;
 525                         thermal-sensors = <&tmu 3>;
 526
 527                         trips {
 528                                 dce-qbman-alert {
 529                                         temperature = <85000>;
 530                                         hysteresis = <2000>;
 531                                         type = "passive";
 532                                 };
 533
 534                                 dce-qbman-crit {
 535                                         temperature = <95000>;
 536                                         hysteresis = <2000>;
 537                                         type = "critical";
 538                                 };
 539                         };
 540                 };
 541
 542                 ccn-dpaa-tbu {
 543                         polling-delay-passive = <1000>;
 544                         polling-delay = <5000>;
 545                         thermal-sensors = <&tmu 4>;
 546
 547                         trips {
 548                                 ccn-dpaa-alert {
 549                                         temperature = <85000>;
 550                                         hysteresis = <2000>;
 551                                         type = "passive";
 552                                 };
 553
 554                                 ccn-dpaa-crit {
 555                                         temperature = <95000>;
 556                                         hysteresis = <2000>;
 557                                         type = "critical";
 558                                 };
 559                         };
 560                 };
 561
 562                 cluster4-hsio3 {
 563                         polling-delay-passive = <1000>;
 564                         polling-delay = <5000>;
 565                         thermal-sensors = <&tmu 5>;
 566
 567                         trips {
 568                                 clust4-hsio3-alert {
 569                                         temperature = <85000>;
 570                                         hysteresis = <2000>;
 571                                         type = "passive";
 572                                 };
 573
 574                                 clust4-hsio3-crit {
 575                                         temperature = <95000>;
 576                                         hysteresis = <2000>;
 577                                         type = "critical";
 578                                 };
 579                         };
 580                 };
 581
 582                 cluster2-3 {
 583                         polling-delay-passive = <1000>;
 584                         polling-delay = <5000>;
 585                         thermal-sensors = <&tmu 6>;
 586
 587                         trips {
 588                                 cluster2-3-alert {
 589                                         temperature = <85000>;
 590                                         hysteresis = <2000>;
 591                                         type = "passive";
 592                                 };
 593
 594                                 cluster2-3-crit {
 595                                         temperature = <95000>;
 596                                         hysteresis = <2000>;
 597                                         type = "critical";
 598                                 };
 599                         };
 600                 };
 601         };
 602
 603         soc {
 604                 compatible = "simple-bus";
 605                 #address-cells = <2>;
 606                 #size-cells = <2>;
 607                 ranges;
 608                 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
 609
 610                 crypto: crypto@8000000 {
 611                         compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
 612                         fsl,sec-era = <10>;
 613                         #address-cells = <1>;
 614                         #size-cells = <1>;
 615                         ranges = <0x0 0x00 0x8000000 0x100000>;
 616                         reg = <0x00 0x8000000 0x0 0x100000>;
 617                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 618                         dma-coherent;
 619                         status = "disabled";
 620
 621                         sec_jr0: jr@10000 {
 622                                 compatible = "fsl,sec-v5.0-job-ring",
 623                                              "fsl,sec-v4.0-job-ring";
 624                                 reg        = <0x10000 0x10000>;
 625                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 626                         };
 627
 628                         sec_jr1: jr@20000 {
 629                                 compatible = "fsl,sec-v5.0-job-ring",
 630                                              "fsl,sec-v4.0-job-ring";
 631                                 reg        = <0x20000 0x10000>;
 632                                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 633                         };
 634
 635                         sec_jr2: jr@30000 {
 636                                 compatible = "fsl,sec-v5.0-job-ring",
 637                                              "fsl,sec-v4.0-job-ring";
 638                                 reg        = <0x30000 0x10000>;
 639                                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 640                         };
 641
 642                         sec_jr3: jr@40000 {
 643                                 compatible = "fsl,sec-v5.0-job-ring",
 644                                              "fsl,sec-v4.0-job-ring";
 645                                 reg        = <0x40000 0x10000>;
 646                                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 647                         };
 648                 };
 649
 650                 clockgen: clock-controller@1300000 {
 651                         compatible = "fsl,lx2160a-clockgen";
 652                         reg = <0 0x1300000 0 0xa0000>;
 653                         #clock-cells = <2>;
 654                         clocks = <&sysclk>;
 655                 };
 656
 657                 dcfg: syscon@1e00000 {
 658                         compatible = "fsl,lx2160a-dcfg", "syscon";
 659                         reg = <0x0 0x1e00000 0x0 0x10000>;
 660                         little-endian;
 661                 };
 662
 663                 tmu: tmu@1f80000 {
 664                         compatible = "fsl,qoriq-tmu";
 665                         reg = <0x0 0x1f80000 0x0 0x10000>;
 666                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 667                         fsl,tmu-range = <0x800000e6 0x8001017d>;
 668                         fsl,tmu-calibration =
 669                                 /* Calibration data group 1 */
 670                                 <0x00000000 0x00000035
 671                                 /* Calibration data group 2 */
 672                                 0x00000001 0x00000154>;
 673                         little-endian;
 674                         #thermal-sensor-cells = <1>;
 675                 };
 676
 677                 i2c0: i2c@2000000 {
 678                         compatible = "fsl,vf610-i2c";
 679                         #address-cells = <1>;
 680                         #size-cells = <0>;
 681                         reg = <0x0 0x2000000 0x0 0x10000>;
 682                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 683                         clock-names = "i2c";
 684                         clocks = <&clockgen 4 15>;
 685                         scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
 686                         status = "disabled";
 687                 };
 688
 689                 i2c1: i2c@2010000 {
 690                         compatible = "fsl,vf610-i2c";
 691                         #address-cells = <1>;
 692                         #size-cells = <0>;
 693                         reg = <0x0 0x2010000 0x0 0x10000>;
 694                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 695                         clock-names = "i2c";
 696                         clocks = <&clockgen 4 15>;
 697                         status = "disabled";
 698                 };
 699
 700                 i2c2: i2c@2020000 {
 701                         compatible = "fsl,vf610-i2c";
 702                         #address-cells = <1>;
 703                         #size-cells = <0>;
 704                         reg = <0x0 0x2020000 0x0 0x10000>;
 705                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 706                         clock-names = "i2c";
 707                         clocks = <&clockgen 4 15>;
 708                         status = "disabled";
 709                 };
 710
 711                 i2c3: i2c@2030000 {
 712                         compatible = "fsl,vf610-i2c";
 713                         #address-cells = <1>;
 714                         #size-cells = <0>;
 715                         reg = <0x0 0x2030000 0x0 0x10000>;
 716                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 717                         clock-names = "i2c";
 718                         clocks = <&clockgen 4 15>;
 719                         status = "disabled";
 720                 };
 721
 722                 i2c4: i2c@2040000 {
 723                         compatible = "fsl,vf610-i2c";
 724                         #address-cells = <1>;
 725                         #size-cells = <0>;
 726                         reg = <0x0 0x2040000 0x0 0x10000>;
 727                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 728                         clock-names = "i2c";
 729                         clocks = <&clockgen 4 15>;
 730                         scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
 731                         status = "disabled";
 732                 };
 733
 734                 i2c5: i2c@2050000 {
 735                         compatible = "fsl,vf610-i2c";
 736                         #address-cells = <1>;
 737                         #size-cells = <0>;
 738                         reg = <0x0 0x2050000 0x0 0x10000>;
 739                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 740                         clock-names = "i2c";
 741                         clocks = <&clockgen 4 15>;
 742                         status = "disabled";
 743                 };
 744
 745                 i2c6: i2c@2060000 {
 746                         compatible = "fsl,vf610-i2c";
 747                         #address-cells = <1>;
 748                         #size-cells = <0>;
 749                         reg = <0x0 0x2060000 0x0 0x10000>;
 750                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 751                         clock-names = "i2c";
 752                         clocks = <&clockgen 4 15>;
 753                         status = "disabled";
 754                 };
 755
 756                 i2c7: i2c@2070000 {
 757                         compatible = "fsl,vf610-i2c";
 758                         #address-cells = <1>;
 759                         #size-cells = <0>;
 760                         reg = <0x0 0x2070000 0x0 0x10000>;
 761                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 762                         clock-names = "i2c";
 763                         clocks = <&clockgen 4 15>;
 764                         status = "disabled";
 765                 };
 766
 767                 fspi: spi@20c0000 {
 768                         compatible = "nxp,lx2160a-fspi";
 769                         #address-cells = <1>;
 770                         #size-cells = <0>;
 771                         reg = <0x0 0x20c0000 0x0 0x10000>,
 772                               <0x0 0x20000000 0x0 0x10000000>;
 773                         reg-names = "fspi_base", "fspi_mmap";
 774                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 775                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 776                         clock-names = "fspi_en", "fspi";
 777                         status = "disabled";
 778                 };
 779
 780                 esdhc0: esdhc@2140000 {
 781                         compatible = "fsl,esdhc";
 782                         reg = <0x0 0x2140000 0x0 0x10000>;
 783                         interrupts = <0 28 0x4>; /* Level high type */
 784                         clocks = <&clockgen 4 1>;
 785                         dma-coherent;
 786                         voltage-ranges = <1800 1800 3300 3300>;
 787                         sdhci,auto-cmd12;
 788                         little-endian;
 789                         bus-width = <4>;
 790                         status = "disabled";
 791                 };
 792
 793                 esdhc1: esdhc@2150000 {
 794                         compatible = "fsl,esdhc";
 795                         reg = <0x0 0x2150000 0x0 0x10000>;
 796                         interrupts = <0 63 0x4>; /* Level high type */
 797                         clocks = <&clockgen 4 1>;
 798                         dma-coherent;
 799                         voltage-ranges = <1800 1800 3300 3300>;
 800                         sdhci,auto-cmd12;
 801                         broken-cd;
 802                         little-endian;
 803                         bus-width = <4>;
 804                         status = "disabled";
 805                 };
 806
 807                 uart0: serial@21c0000 {
 808                         compatible = "arm,sbsa-uart","arm,pl011";
 809                         reg = <0x0 0x21c0000 0x0 0x1000>;
 810                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 811                         current-speed = <115200>;
 812                         status = "disabled";
 813                 };
 814
 815                 uart1: serial@21d0000 {
 816                         compatible = "arm,sbsa-uart","arm,pl011";
 817                         reg = <0x0 0x21d0000 0x0 0x1000>;
 818                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 819                         current-speed = <115200>;
 820                         status = "disabled";
 821                 };
 822
 823                 uart2: serial@21e0000 {
 824                         compatible = "arm,sbsa-uart","arm,pl011";
 825                         reg = <0x0 0x21e0000 0x0 0x1000>;
 826                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 827                         current-speed = <115200>;
 828                         status = "disabled";
 829                 };
 830
 831                 uart3: serial@21f0000 {
 832                         compatible = "arm,sbsa-uart","arm,pl011";
 833                         reg = <0x0 0x21f0000 0x0 0x1000>;
 834                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 835                         current-speed = <115200>;
 836                         status = "disabled";
 837                 };
 838
 839                 gpio0: gpio@2300000 {
 840                         compatible = "fsl,qoriq-gpio";
 841                         reg = <0x0 0x2300000 0x0 0x10000>;
 842                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 843                         gpio-controller;
 844                         little-endian;
 845                         #gpio-cells = <2>;
 846                         interrupt-controller;
 847                         #interrupt-cells = <2>;
 848                 };
 849
 850                 gpio1: gpio@2310000 {
 851                         compatible = "fsl,qoriq-gpio";
 852                         reg = <0x0 0x2310000 0x0 0x10000>;
 853                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 854                         gpio-controller;
 855                         little-endian;
 856                         #gpio-cells = <2>;
 857                         interrupt-controller;
 858                         #interrupt-cells = <2>;
 859                 };
 860
 861                 gpio2: gpio@2320000 {
 862                         compatible = "fsl,qoriq-gpio";
 863                         reg = <0x0 0x2320000 0x0 0x10000>;
 864                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 865                         gpio-controller;
 866                         little-endian;
 867                         #gpio-cells = <2>;
 868                         interrupt-controller;
 869                         #interrupt-cells = <2>;
 870                 };
 871
 872                 gpio3: gpio@2330000 {
 873                         compatible = "fsl,qoriq-gpio";
 874                         reg = <0x0 0x2330000 0x0 0x10000>;
 875                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 876                         gpio-controller;
 877                         little-endian;
 878                         #gpio-cells = <2>;
 879                         interrupt-controller;
 880                         #interrupt-cells = <2>;
 881                 };
 882
 883                 watchdog@23a0000 {
 884                         compatible = "arm,sbsa-gwdt";
 885                         reg = <0x0 0x23a0000 0 0x1000>,
 886                               <0x0 0x2390000 0 0x1000>;
 887                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 888                         timeout-sec = <30>;
 889                 };
 890
 891                 usb0: usb@3100000 {
 892                         compatible = "snps,dwc3";
 893                         reg = <0x0 0x3100000 0x0 0x10000>;
 894                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 895                         dr_mode = "host";
 896                         snps,quirk-frame-length-adjustment = <0x20>;
 897                         snps,dis_rxdet_inp3_quirk;
 898                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 899                         status = "disabled";
 900                 };
 901
 902                 usb1: usb@3110000 {
 903                         compatible = "snps,dwc3";
 904                         reg = <0x0 0x3110000 0x0 0x10000>;
 905                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 906                         dr_mode = "host";
 907                         snps,quirk-frame-length-adjustment = <0x20>;
 908                         snps,dis_rxdet_inp3_quirk;
 909                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 910                         status = "disabled";
 911                 };
 912
 913                 sata0: sata@3200000 {
 914                         compatible = "fsl,lx2160a-ahci";
 915                         reg = <0x0 0x3200000 0x0 0x10000>,
 916                               <0x7 0x100520 0x0 0x4>;
 917                         reg-names = "ahci", "sata-ecc";
 918                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 919                         clocks = <&clockgen 4 3>;
 920                         dma-coherent;
 921                         status = "disabled";
 922                 };
 923
 924                 sata1: sata@3210000 {
 925                         compatible = "fsl,lx2160a-ahci";
 926                         reg = <0x0 0x3210000 0x0 0x10000>,
 927                               <0x7 0x100520 0x0 0x4>;
 928                         reg-names = "ahci", "sata-ecc";
 929                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 930                         clocks = <&clockgen 4 3>;
 931                         dma-coherent;
 932                         status = "disabled";
 933                 };
 934
 935                 sata2: sata@3220000 {
 936                         compatible = "fsl,lx2160a-ahci";
 937                         reg = <0x0 0x3220000 0x0 0x10000>,
 938                               <0x7 0x100520 0x0 0x4>;
 939                         reg-names = "ahci", "sata-ecc";
 940                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 941                         clocks = <&clockgen 4 3>;
 942                         dma-coherent;
 943                         status = "disabled";
 944                 };
 945
 946                 sata3: sata@3230000 {
 947                         compatible = "fsl,lx2160a-ahci";
 948                         reg = <0x0 0x3230000 0x0 0x10000>,
 949                               <0x7 0x100520 0x0 0x4>;
 950                         reg-names = "ahci", "sata-ecc";
 951                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 952                         clocks = <&clockgen 4 3>;
 953                         dma-coherent;
 954                         status = "disabled";
 955                 };
 956
 957                 pcie@3400000 {
 958                         compatible = "fsl,lx2160a-pcie";
 959                         reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 960                                0x80 0x00000000 0x0 0x00001000>; /* configuration space */
 961                         reg-names = "csr_axi_slave", "config_axi_slave";
 962                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
 963                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
 964                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
 965                         interrupt-names = "aer", "pme", "intr";
 966                         #address-cells = <3>;
 967                         #size-cells = <2>;
 968                         device_type = "pci";
 969                         dma-coherent;
 970                         apio-wins = <8>;
 971                         ppio-wins = <8>;
 972                         bus-range = <0x0 0xff>;
 973                         ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 974                         msi-parent = <&its>;
 975                         #interrupt-cells = <1>;
 976                         interrupt-map-mask = <0 0 0 7>;
 977                         interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 978                                         <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 979                                         <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 980                                         <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 981                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 982                         status = "disabled";
 983                 };
 984
 985                 pcie@3500000 {
 986                         compatible = "fsl,lx2160a-pcie";
 987                         reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 988                                0x88 0x00000000 0x0 0x00001000>; /* configuration space */
 989                         reg-names = "csr_axi_slave", "config_axi_slave";
 990                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
 991                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
 992                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
 993                         interrupt-names = "aer", "pme", "intr";
 994                         #address-cells = <3>;
 995                         #size-cells = <2>;
 996                         device_type = "pci";
 997                         dma-coherent;
 998                         apio-wins = <8>;
 999                         ppio-wins = <8>;
1000                         bus-range = <0x0 0xff>;
1001                         ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1002                         msi-parent = <&its>;
1003                         #interrupt-cells = <1>;
1004                         interrupt-map-mask = <0 0 0 7>;
1005                         interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1006                                         <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1007                                         <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1008                                         <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1009                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1010                         status = "disabled";
1011                 };
1012
1013                 pcie@3600000 {
1014                         compatible = "fsl,lx2160a-pcie";
1015                         reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
1016                                0x90 0x00000000 0x0 0x00001000>; /* configuration space */
1017                         reg-names = "csr_axi_slave", "config_axi_slave";
1018                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1019                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1020                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1021                         interrupt-names = "aer", "pme", "intr";
1022                         #address-cells = <3>;
1023                         #size-cells = <2>;
1024                         device_type = "pci";
1025                         dma-coherent;
1026                         apio-wins = <256>;
1027                         ppio-wins = <24>;
1028                         bus-range = <0x0 0xff>;
1029                         ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1030                         msi-parent = <&its>;
1031                         #interrupt-cells = <1>;
1032                         interrupt-map-mask = <0 0 0 7>;
1033                         interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1034                                         <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1035                                         <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1036                                         <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1037                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1038                         status = "disabled";
1039                 };
1040
1041                 pcie@3700000 {
1042                         compatible = "fsl,lx2160a-pcie";
1043                         reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
1044                                0x98 0x00000000 0x0 0x00001000>; /* configuration space */
1045                         reg-names = "csr_axi_slave", "config_axi_slave";
1046                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1047                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1048                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1049                         interrupt-names = "aer", "pme", "intr";
1050                         #address-cells = <3>;
1051                         #size-cells = <2>;
1052                         device_type = "pci";
1053                         dma-coherent;
1054                         apio-wins = <8>;
1055                         ppio-wins = <8>;
1056                         bus-range = <0x0 0xff>;
1057                         ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1058                         msi-parent = <&its>;
1059                         #interrupt-cells = <1>;
1060                         interrupt-map-mask = <0 0 0 7>;
1061                         interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1062                                         <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1063                                         <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1064                                         <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1065                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1066                         status = "disabled";
1067                 };
1068
1069                 pcie@3800000 {
1070                         compatible = "fsl,lx2160a-pcie";
1071                         reg = <0x00 0x03800000 0x0 0x00100000   /* controller registers */
1072                                0xa0 0x00000000 0x0 0x00001000>; /* configuration space */
1073                         reg-names = "csr_axi_slave", "config_axi_slave";
1074                         interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1075                                      <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1076                                      <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1077                         interrupt-names = "aer", "pme", "intr";
1078                         #address-cells = <3>;
1079                         #size-cells = <2>;
1080                         device_type = "pci";
1081                         dma-coherent;
1082                         apio-wins = <256>;
1083                         ppio-wins = <24>;
1084                         bus-range = <0x0 0xff>;
1085                         ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1086                         msi-parent = <&its>;
1087                         #interrupt-cells = <1>;
1088                         interrupt-map-mask = <0 0 0 7>;
1089                         interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1090                                         <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1091                                         <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1092                                         <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
1093                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1094                         status = "disabled";
1095                 };
1096
1097                 pcie@3900000 {
1098                         compatible = "fsl,lx2160a-pcie";
1099                         reg = <0x00 0x03900000 0x0 0x00100000   /* controller registers */
1100                                0xa8 0x00000000 0x0 0x00001000>; /* configuration space */
1101                         reg-names = "csr_axi_slave", "config_axi_slave";
1102                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1103                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1104                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1105                         interrupt-names = "aer", "pme", "intr";
1106                         #address-cells = <3>;
1107                         #size-cells = <2>;
1108                         device_type = "pci";
1109                         dma-coherent;
1110                         apio-wins = <8>;
1111                         ppio-wins = <8>;
1112                         bus-range = <0x0 0xff>;
1113                         ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1114                         msi-parent = <&its>;
1115                         #interrupt-cells = <1>;
1116                         interrupt-map-mask = <0 0 0 7>;
1117                         interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1118                                         <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1119                                         <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1120                                         <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1121                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1122                         status = "disabled";
1123                 };
1124
1125                 smmu: iommu@5000000 {
1126                         compatible = "arm,mmu-500";
1127                         reg = <0 0x5000000 0 0x800000>;
1128                         #iommu-cells = <1>;
1129                         #global-interrupts = <14>;
1130                                      // global secure fault
1131                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1132                                      // combined secure
1133                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1134                                      // global non-secure fault
1135                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
1136                                      // combined non-secure
1137                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1138                                      // performance counter interrupts 0-9
1139                                      <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
1140                                      <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
1141                                      <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
1142                                      <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1143                                      <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1144                                      <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1145                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1146                                      <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
1147                                      <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
1148                                      <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
1149                                      // per context interrupt, 64 interrupts
1150                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1151                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1152                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1153                                      <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1154                                      <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1155                                      <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1156                                      <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
1157                                      <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1158                                      <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
1159                                      <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1160                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
1161                                      <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1162                                      <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
1163                                      <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1164                                      <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
1165                                      <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1166                                      <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
1167                                      <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1168                                      <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
1169                                      <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
1170                                      <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
1171                                      <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
1172                                      <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1173                                      <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
1174                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1175                                      <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
1176                                      <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
1177                                      <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
1178                                      <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
1179                                      <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
1180                                      <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1181                                      <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
1182                                      <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
1183                                      <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
1184                                      <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
1185                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1186                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1187                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1188                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1189                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1190                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1191                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1192                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1193                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1194                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1195                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1196                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1197                                      <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
1198                                      <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
1199                                      <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
1200                                      <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1201                                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1202                                      <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1203                                      <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
1204                                      <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
1205                                      <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
1206                                      <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
1207                                      <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1208                                      <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1209                                      <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
1210                                      <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
1211                                      <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
1212                                      <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
1213                                      <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1214                         dma-coherent;
1215                 };
1216
1217                 console@8340020 {
1218                         compatible = "fsl,dpaa2-console";
1219                         reg = <0x00000000 0x08340020 0 0x2>;
1220                 };
1221
1222                 ptp-timer@8b95000 {
1223                         compatible = "fsl,dpaa2-ptp";
1224                         reg = <0x0 0x8b95000 0x0 0x100>;
1225                         clocks = <&clockgen 4 1>;
1226                         little-endian;
1227                         fsl,extts-fifo;
1228                 };
1229
1230                 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
1231                 emdio1: mdio@8b96000 {
1232                         compatible = "fsl,fman-memac-mdio";
1233                         reg = <0x0 0x8b96000 0x0 0x1000>;
1234                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1235                         #address-cells = <1>;
1236                         #size-cells = <0>;
1237                         little-endian;
1238                         status = "disabled";
1239                 };
1240
1241                 emdio2: mdio@8b97000 {
1242                         compatible = "fsl,fman-memac-mdio";
1243                         reg = <0x0 0x8b97000 0x0 0x1000>;
1244                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1245                         little-endian;
1246                         #address-cells = <1>;
1247                         #size-cells = <0>;
1248                         status = "disabled";
1249                 };
1250
1251                 fsl_mc: fsl-mc@80c000000 {
1252                         compatible = "fsl,qoriq-mc";
1253                         reg = <0x00000008 0x0c000000 0 0x40>,
1254                               <0x00000000 0x08340000 0 0x40000>;
1255                         msi-parent = <&its>;
1256                         /* iommu-map property is fixed up by u-boot */
1257                         iommu-map = <0 &smmu 0 0>;
1258                         dma-coherent;
1259                         #address-cells = <3>;
1260                         #size-cells = <1>;
1261
1262                         /*
1263                          * Region type 0x0 - MC portals
1264                          * Region type 0x1 - QBMAN portals
1265                          */
1266                         ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
1267                                   0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
1268
1269                         /*
1270                          * Define the maximum number of MACs present on the SoC.
1271                          */
1272                         dpmacs {
1273                                 #address-cells = <1>;
1274                                 #size-cells = <0>;
1275
1276                                 dpmac1: dpmac@1 {
1277                                         compatible = "fsl,qoriq-mc-dpmac";
1278                                         reg = <0x1>;
1279                                 };
1280
1281                                 dpmac2: dpmac@2 {
1282                                         compatible = "fsl,qoriq-mc-dpmac";
1283                                         reg = <0x2>;
1284                                 };
1285
1286                                 dpmac3: dpmac@3 {
1287                                         compatible = "fsl,qoriq-mc-dpmac";
1288                                         reg = <0x3>;
1289                                 };
1290
1291                                 dpmac4: dpmac@4 {
1292                                         compatible = "fsl,qoriq-mc-dpmac";
1293                                         reg = <0x4>;
1294                                 };
1295
1296                                 dpmac5: dpmac@5 {
1297                                         compatible = "fsl,qoriq-mc-dpmac";
1298                                         reg = <0x5>;
1299                                 };
1300
1301                                 dpmac6: dpmac@6 {
1302                                         compatible = "fsl,qoriq-mc-dpmac";
1303                                         reg = <0x6>;
1304                                 };
1305
1306                                 dpmac7: dpmac@7 {
1307                                         compatible = "fsl,qoriq-mc-dpmac";
1308                                         reg = <0x7>;
1309                                 };
1310
1311                                 dpmac8: dpmac@8 {
1312                                         compatible = "fsl,qoriq-mc-dpmac";
1313                                         reg = <0x8>;
1314                                 };
1315
1316                                 dpmac9: dpmac@9 {
1317                                         compatible = "fsl,qoriq-mc-dpmac";
1318                                         reg = <0x9>;
1319                                 };
1320
1321                                 dpmac10: dpmac@a {
1322                                         compatible = "fsl,qoriq-mc-dpmac";
1323                                         reg = <0xa>;
1324                                 };
1325
1326                                 dpmac11: dpmac@b {
1327                                         compatible = "fsl,qoriq-mc-dpmac";
1328                                         reg = <0xb>;
1329                                 };
1330
1331                                 dpmac12: dpmac@c {
1332                                         compatible = "fsl,qoriq-mc-dpmac";
1333                                         reg = <0xc>;
1334                                 };
1335
1336                                 dpmac13: dpmac@d {
1337                                         compatible = "fsl,qoriq-mc-dpmac";
1338                                         reg = <0xd>;
1339                                 };
1340
1341                                 dpmac14: dpmac@e {
1342                                         compatible = "fsl,qoriq-mc-dpmac";
1343                                         reg = <0xe>;
1344                                 };
1345
1346                                 dpmac15: dpmac@f {
1347                                         compatible = "fsl,qoriq-mc-dpmac";
1348                                         reg = <0xf>;
1349                                 };
1350
1351                                 dpmac16: dpmac@10 {
1352                                         compatible = "fsl,qoriq-mc-dpmac";
1353                                         reg = <0x10>;
1354                                 };
1355
1356                                 dpmac17: dpmac@11 {
1357                                         compatible = "fsl,qoriq-mc-dpmac";
1358                                         reg = <0x11>;
1359                                 };
1360
1361                                 dpmac18: dpmac@12 {
1362                                         compatible = "fsl,qoriq-mc-dpmac";
1363                                         reg = <0x12>;
1364                                 };
1365                         };
1366                 };
1367         };
1368 };