src/arm64/freescale/imx8mq-zii-ultra.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2019 Zodiac Inflight Innovations
   4  */
   5
   6 #include "imx8mq.dtsi"
   7
   8 / {
   9         aliases {
  10                 mdio-gpio0 = &mdio0;
  11                 rtc0 = &ds1341;
  12         };
  13
  14         chosen {
  15                 stdout-path = &uart1;
  16         };
  17
  18         mdio0: bitbang-mdio {
  19                 compatible = "virtual,mdio-gpio";
  20                 pinctrl-names = "default";
  21                 pinctrl-0 = <&pinctrl_mdio_bitbang>, <&pinctrl_fec1_phy_reset>;
  22                 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>, /* MDC */
  23                         <&gpio1 14 GPIO_ACTIVE_HIGH>; /* MDIO */
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 phy0: ethernet-phy@0 {
  28                         reg = <0>;
  29                         reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
  30                 };
  31         };
  32
  33         pcie0_refclk: clock-pcie0-refclk {
  34                 compatible = "fixed-clock";
  35                 #clock-cells = <0>;
  36                 clock-frequency = <100000000>;
  37         };
  38
  39         pcie1_refclk: clock-pcie1-refclk {
  40                 compatible = "fixed-clock";
  41                 #clock-cells = <0>;
  42                 clock-frequency = <100000000>;
  43         };
  44
  45         reg_12p0_main: regulator-12p0-main {
  46                 compatible = "regulator-fixed";
  47                 regulator-name = "12V_MAIN";
  48                 regulator-min-microvolt = <5000000>;
  49                 regulator-max-microvolt = <5000000>;
  50                 regulator-always-on;
  51         };
  52
  53         reg_5p0_main: regulator-5p0-main {
  54                 compatible = "regulator-fixed";
  55                 vin-supply = <&reg_12p0_main>;
  56                 regulator-name = "5V_MAIN";
  57                 regulator-min-microvolt = <5000000>;
  58                 regulator-max-microvolt = <5000000>;
  59                 regulator-always-on;
  60         };
  61
  62         reg_3p3_main: regulator-3p3-main {
  63                 compatible = "regulator-fixed";
  64                 vin-supply = <&reg_12p0_main>;
  65                 regulator-name = "3V3V_MAIN";
  66                 regulator-min-microvolt = <3300000>;
  67                 regulator-max-microvolt = <3300000>;
  68                 regulator-always-on;
  69         };
  70
  71         reg_usdhc2_vmmc: regulator-vsd-3v3 {
  72                 pinctrl-names = "default";
  73                 pinctrl-0 = <&pinctrl_reg_usdhc2>;
  74                 compatible = "regulator-fixed";
  75                 vin-supply = <&reg_3p3_main>;
  76                 regulator-name = "3V3_SD";
  77                 regulator-min-microvolt = <3300000>;
  78                 regulator-max-microvolt = <3300000>;
  79                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  80                 enable-active-high;
  81         };
  82
  83         reg_arm: regulator-arm {
  84                 pinctrl-names = "default";
  85                 pinctrl-0 = <&pinctrl_reg_arm>;
  86                 compatible = "regulator-gpio";
  87                 vin-supply = <&reg_12p0_main>;
  88                 regulator-name = "0V9_ARM";
  89                 regulator-min-microvolt = <900000>;
  90                 regulator-max-microvolt = <1000000>;
  91                 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
  92                 states = <1000000 0x1
  93                            900000 0x0>;
  94                 regulator-always-on;
  95         };
  96 };
  97
  98 &A53_0 {
  99         cpu-supply = <&reg_arm>;
 100 };
 101
 102 &A53_1 {
 103         cpu-supply = <&reg_arm>;
 104 };
 105
 106 &A53_2 {
 107         cpu-supply = <&reg_arm>;
 108 };
 109
 110 &A53_3 {
 111         cpu-supply = <&reg_arm>;
 112 };
 113
 114 &fec1 {
 115         pinctrl-names = "default";
 116         pinctrl-0 = <&pinctrl_fec1>;
 117
 118         phy-handle = <&phy0>;
 119         phy-mode = "rmii";
 120         status = "okay";
 121
 122         mdio {
 123                 #address-cells = <1>;
 124                 #size-cells = <0>;
 125                 status = "okay";
 126
 127                 switch: switch@0 {
 128                         compatible = "marvell,mv88e6085";
 129                         pinctrl-0 = <&pinctrl_switch_irq>;
 130                         pinctrl-names = "default";
 131                         reg = <0>;
 132                         dsa,member = <0 0>;
 133                         eeprom-length = <512>;
 134                         interrupt-parent = <&gpio1>;
 135                         interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
 136                         interrupt-controller;
 137                         #interrupt-cells = <2>;
 138
 139                         ports {
 140                                 #address-cells = <1>;
 141                                 #size-cells = <0>;
 142
 143                                 port@0 {
 144                                         reg = <0>;
 145                                         label = "gigabit_proc";
 146                                         phy-handle = <&switchphy0>;
 147                                 };
 148
 149                                 port@1 {
 150                                         reg = <1>;
 151                                         label = "netaux";
 152                                         phy-handle = <&switchphy1>;
 153                                 };
 154
 155                                 port@2 {
 156                                         reg = <2>;
 157                                         label = "cpu";
 158                                         ethernet = <&fec1>;
 159
 160                                         fixed-link {
 161                                                 speed = <100>;
 162                                                 full-duplex;
 163                                         };
 164                                 };
 165
 166                                 port@3 {
 167                                         reg = <3>;
 168                                         label = "netright";
 169                                         phy-handle = <&switchphy3>;
 170                                 };
 171
 172                                 port@4 {
 173                                         reg = <4>;
 174                                         label = "netleft";
 175                                         phy-handle = <&switchphy4>;
 176                                 };
 177                         };
 178
 179                         mdio {
 180                                 #address-cells = <1>;
 181                                 #size-cells = <0>;
 182
 183                                 switchphy0: switchphy@0 {
 184                                         reg = <0>;
 185                                         interrupt-parent = <&switch>;
 186                                         interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 187                                 };
 188
 189                                 switchphy1: switchphy@1 {
 190                                         reg = <1>;
 191                                         interrupt-parent = <&switch>;
 192                                         interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 193                                 };
 194
 195                                 switchphy2: switchphy@2 {
 196                                         reg = <2>;
 197                                         interrupt-parent = <&switch>;
 198                                         interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 199                                 };
 200
 201                                 switchphy3: switchphy@3 {
 202                                         reg = <3>;
 203                                         interrupt-parent = <&switch>;
 204                                         interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
 205                                 };
 206
 207                                 switchphy4: switchphy@4 {
 208                                         reg = <4>;
 209                                         interrupt-parent = <&switch>;
 210                                         interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 211                                 };
 212                         };
 213                 };
 214         };
 215 };
 216
 217 &gpio3 {
 218         pinctrl-names = "default";
 219         pinctrl-0 = <&pinctrl_gpio3_hog>;
 220
 221         usb-emulation {
 222                 gpio-hog;
 223                 gpios = <10 GPIO_ACTIVE_HIGH>;
 224                 output-low;
 225                 line-name = "usb-emulation";
 226         };
 227
 228         usb-mode1 {
 229                 gpio-hog;
 230                 gpios = <11 GPIO_ACTIVE_HIGH>;
 231                 output-high;
 232                 line-name = "usb-mode1";
 233         };
 234
 235         usb-pwr {
 236                 gpio-hog;
 237                 gpios = <12 GPIO_ACTIVE_LOW>;
 238                 output-high;
 239                 line-name = "usb-pwr-ctrl-en-n";
 240         };
 241
 242         usb-mode2 {
 243                 gpio-hog;
 244                 gpios = <13 GPIO_ACTIVE_HIGH>;
 245                 output-high;
 246                 line-name = "usb-mode2";
 247         };
 248 };
 249
 250 &i2c1 {
 251         clock-frequency = <400000>;
 252         pinctrl-names = "default";
 253         pinctrl-0 = <&pinctrl_i2c1>;
 254         status = "okay";
 255
 256         ucs1002: charger@32 {
 257                 compatible = "microchip,ucs1002";
 258                 pinctrl-names = "default";
 259                 pinctrl-0 = <&pinctrl_ucs1002>;
 260                 reg = <0x32>;
 261                 interrupt-parent = <&gpio3>;
 262                 interrupts = <17 IRQ_TYPE_EDGE_BOTH>,
 263                              <18 IRQ_TYPE_EDGE_BOTH>;
 264                 interrupt-names = "a_det", "alert";
 265         };
 266 };
 267
 268 &i2c2 {
 269         clock-frequency = <400000>;
 270         pinctrl-names = "default";
 271         pinctrl-0 = <&pinctrl_i2c2>;
 272         status = "okay";
 273
 274         pmic@8 {
 275                 compatible = "fsl,pfuze100";
 276                 reg = <0x8>;
 277
 278                 regulators {
 279                         sw1a_reg: sw1ab {
 280                                 regulator-min-microvolt = <825000>;
 281                                 regulator-max-microvolt = <1100000>;
 282                         };
 283
 284                         sw1c_reg: sw1c {
 285                                 regulator-min-microvolt = <825000>;
 286                                 regulator-max-microvolt = <1100000>;
 287                         };
 288
 289                         sw2_reg: sw2 {
 290                                 regulator-min-microvolt = <1100000>;
 291                                 regulator-max-microvolt = <1100000>;
 292                                 regulator-always-on;
 293                         };
 294
 295                         sw3a_reg: sw3ab {
 296                                 regulator-min-microvolt = <825000>;
 297                                 regulator-max-microvolt = <1100000>;
 298                                 regulator-always-on;
 299                         };
 300
 301                         sw4_reg: sw4 {
 302                                 regulator-min-microvolt = <1800000>;
 303                                 regulator-max-microvolt = <1800000>;
 304                                 regulator-always-on;
 305                         };
 306
 307                         swbst_reg: swbst {
 308                                 regulator-min-microvolt = <5000000>;
 309                                 regulator-max-microvolt = <5150000>;
 310                         };
 311
 312                         snvs_reg: vsnvs {
 313                                 regulator-min-microvolt = <1000000>;
 314                                 regulator-max-microvolt = <3000000>;
 315                                 regulator-always-on;
 316                         };
 317
 318                         vref_reg: vrefddr {
 319                                 regulator-always-on;
 320                         };
 321
 322                         vgen1_reg: vgen1 {
 323                                 regulator-min-microvolt = <800000>;
 324                                 regulator-max-microvolt = <1550000>;
 325                         };
 326
 327                         vgen2_reg: vgen2 {
 328                                 regulator-min-microvolt = <850000>;
 329                                 regulator-max-microvolt = <975000>;
 330                                 regulator-always-on;
 331                         };
 332
 333                         vgen3_reg: vgen3 {
 334                                 regulator-min-microvolt = <1675000>;
 335                                 regulator-max-microvolt = <1975000>;
 336                                 regulator-always-on;
 337                         };
 338
 339                         vgen4_reg: vgen4 {
 340                                 regulator-min-microvolt = <1625000>;
 341                                 regulator-max-microvolt = <1875000>;
 342                                 regulator-always-on;
 343                         };
 344
 345                         vgen5_reg: vgen5 {
 346                                 regulator-min-microvolt = <3075000>;
 347                                 regulator-max-microvolt = <3625000>;
 348                                 regulator-always-on;
 349                         };
 350
 351                         vgen6_reg: vgen6 {
 352                                 regulator-min-microvolt = <1800000>;
 353                                 regulator-max-microvolt = <3300000>;
 354                         };
 355                 };
 356         };
 357
 358         eeprom@54 {
 359                 compatible = "atmel,24c128";
 360                 reg = <0x54>;
 361         };
 362
 363         ds1341: rtc@68 {
 364                 compatible = "dallas,ds1341";
 365                 reg = <0x68>;
 366         };
 367 };
 368
 369 &i2c3 {
 370         clock-frequency = <100000>;
 371         pinctrl-names = "default";
 372         pinctrl-0 = <&pinctrl_i2c3>;
 373         status = "okay";
 374
 375         usbhub: usbhub@2c {
 376                 compatible ="microchip,usb2513b";
 377                 pinctrl-names = "default";
 378                 pinctrl-0 = <&pinctrl_usbhub>;
 379                 reg = <0x2c>;
 380                 reset-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
 381         };
 382 };
 383
 384 &i2c4 {
 385         clock-frequency = <400000>;
 386         pinctrl-names = "default";
 387         pinctrl-0 = <&pinctrl_i2c4>;
 388         status = "okay";
 389 };
 390
 391 &uart1 {
 392         pinctrl-names = "default";
 393         pinctrl-0 = <&pinctrl_uart1>;
 394         status = "okay";
 395 };
 396
 397 &uart2 {
 398         pinctrl-names = "default";
 399         pinctrl-0 = <&pinctrl_uart2>;
 400         status = "okay";
 401
 402         rave-sp {
 403                 compatible = "zii,rave-sp-rdu2";
 404                 current-speed = <1000000>;
 405                 #address-cells = <1>;
 406                 #size-cells = <1>;
 407
 408                 watchdog {
 409                         compatible = "zii,rave-sp-watchdog";
 410                 };
 411
 412                 backlight {
 413                         compatible = "zii,rave-sp-backlight";
 414                 };
 415
 416                 pwrbutton {
 417                         compatible = "zii,rave-sp-pwrbutton";
 418                 };
 419
 420                 eeprom@a3 {
 421                         compatible = "zii,rave-sp-eeprom";
 422                         reg = <0xa3 0x4000>;
 423                         zii,eeprom-name = "dds-eeprom";
 424                 };
 425
 426                 eeprom@a4 {
 427                         compatible = "zii,rave-sp-eeprom";
 428                         reg = <0xa4 0x4000>;
 429                         #address-cells = <1>;
 430                         #size-cells = <1>;
 431                         zii,eeprom-name = "main-eeprom";
 432                 };
 433         };
 434 };
 435
 436 &usb3_phy0 {
 437         vbus-supply = <&ucs1002>;
 438         status = "okay";
 439 };
 440
 441 &usb_dwc3_0 {
 442         dr_mode = "host";
 443         status = "okay";
 444 };
 445
 446 &usb3_phy1 {
 447         vbus-supply = <&reg_5p0_main>;
 448         status = "okay";
 449 };
 450
 451 &usb_dwc3_1 {
 452         dr_mode = "host";
 453         status = "okay";
 454 };
 455
 456 &pcie0 {
 457         pinctrl-names = "default";
 458         pinctrl-0 = <&pinctrl_pcie0>;
 459         reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
 460         clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
 461                  <&clk IMX8MQ_CLK_PCIE1_AUX>,
 462                  <&clk IMX8MQ_CLK_PCIE1_PHY>,
 463                  <&pcie0_refclk>;
 464         clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
 465         status = "okay";
 466 };
 467
 468 &pcie1 {
 469         pinctrl-names = "default";
 470         pinctrl-0 = <&pinctrl_pcie1>;
 471         reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
 472         clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
 473                  <&clk IMX8MQ_CLK_PCIE2_AUX>,
 474                  <&clk IMX8MQ_CLK_PCIE2_PHY>,
 475                  <&pcie1_refclk>;
 476         clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
 477         status = "okay";
 478 };
 479
 480 &pgc_gpu {
 481         power-supply = <&sw1a_reg>;
 482 };
 483
 484 &pgc_vpu {
 485         power-supply = <&sw1c_reg>;
 486 };
 487
 488 &usdhc1 {
 489         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 490         pinctrl-0 = <&pinctrl_usdhc1>;
 491         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 492         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 493         vqmmc-supply = <&sw4_reg>;
 494         bus-width = <8>;
 495         non-removable;
 496         no-sd;
 497         no-sdio;
 498         status = "okay";
 499 };
 500
 501 &usdhc2 {
 502         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 503         pinctrl-0 = <&pinctrl_usdhc2>;
 504         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 505         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 506         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 507         vmmc-supply = <&reg_usdhc2_vmmc>;
 508         status = "okay";
 509 };
 510
 511 &snvs_rtc {
 512         status = "disabled";
 513 };
 514
 515 &iomuxc {
 516         pinctrl_fec1: fec1grp {
 517                 fsl,pins = <
 518                         MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 519                         MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO               0x23
 520                         MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
 521                         MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
 522                         MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 523                         MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 524                         MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK              0x1f
 525                         MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER               0x91
 526                         MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 527                         MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 528                 >;
 529         };
 530
 531         pinctrl_fec1_phy_reset: fec1phyresetgrp {
 532                 fsl,pins = <
 533                         MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29                0x11
 534                 >;
 535         };
 536
 537         pinctrl_gpio3_hog: gpio3hoggrp {
 538                 fsl,pins = <
 539                         MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10             0x6
 540                         MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11             0x6
 541                         MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12             0x6
 542                         MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13             0x6
 543                 >;
 544         };
 545
 546         pinctrl_i2c1: i2c1grp {
 547                 fsl,pins = <
 548                         MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL                  0x4000007f
 549                         MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA                  0x4000007f
 550                 >;
 551         };
 552
 553         pinctrl_i2c2: i2c2grp {
 554                 fsl,pins = <
 555                         MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL                  0x4000007f
 556                         MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA                  0x4000007f
 557                 >;
 558         };
 559
 560         pinctrl_i2c3: i2c3grp {
 561                 fsl,pins = <
 562                         MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL                  0x4000007f
 563                         MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA                  0x4000007f
 564                 >;
 565         };
 566
 567         pinctrl_i2c4: i2c4grp {
 568                 fsl,pins = <
 569                         MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL                  0x4000007f
 570                         MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA                  0x4000007f
 571                 >;
 572         };
 573
 574         pinctrl_mdio_bitbang: bitbangmdiogrp {
 575                 fsl,pins = <
 576                         MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x44
 577                         MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14              0x64
 578                 >;
 579         };
 580
 581         pinctrl_pcie0: pcie0grp {
 582                 fsl,pins = <
 583                         MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B           0x66
 584                         MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3               0x6
 585                 >;
 586         };
 587
 588         pinctrl_pcie1: pcie1grp {
 589                 fsl,pins = <
 590                         MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B           0x66
 591                         MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6               0x6
 592                 >;
 593         };
 594
 595         pinctrl_reg_arm: regarmgrp {
 596                 fsl,pins = <
 597                         MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16            0x19
 598                 >;
 599         };
 600
 601         pinctrl_reg_usdhc2: regusdhc2grp {
 602                 fsl,pins = <
 603                         MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19             0x41
 604                 >;
 605         };
 606
 607         pinctrl_switch_irq: switchgrp {
 608                 fsl,pins = <
 609                         MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15              0x41
 610                 >;
 611         };
 612
 613         pinctrl_ts: tsgrp {
 614                 fsl,pins = <
 615                         MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11              0x96
 616                         MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12              0x96
 617                 >;
 618         };
 619
 620         pinctrl_uart1: uart1grp {
 621                 fsl,pins = <
 622                         MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX             0x49
 623                         MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX             0x49
 624                 >;
 625         };
 626
 627         pinctrl_uart2: uart2grp {
 628                 fsl,pins = <
 629                         MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX             0x49
 630                         MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX             0x49
 631                 >;
 632         };
 633
 634         pinctrl_ucs1002: ucs1002grp {
 635                 fsl,pins = <
 636                         MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17               0x41
 637                         MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18               0x41
 638                 >;
 639         };
 640
 641         pinctrl_usbhub: usbhubgrp {
 642                 fsl,pins = <
 643                         MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25               0x41
 644                 >;
 645         };
 646
 647         pinctrl_usdhc1: usdhc1grp {
 648                 fsl,pins = <
 649                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x83
 650                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xc3
 651                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xc3
 652                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xc3
 653                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xc3
 654                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xc3
 655                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xc3
 656                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xc3
 657                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xc3
 658                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xc3
 659                         MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x83
 660                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
 661                 >;
 662         };
 663
 664         pinctrl_usdhc1_100mhz: usdhc1-100grp {
 665                 fsl,pins = <
 666                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x8d
 667                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xcd
 668                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xcd
 669                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xcd
 670                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xcd
 671                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xcd
 672                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xcd
 673                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xcd
 674                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xcd
 675                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xcd
 676                         MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x8d
 677                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
 678                 >;
 679         };
 680
 681         pinctrl_usdhc1_200mhz: usdhc1-200grp {
 682                 fsl,pins = <
 683                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x9f
 684                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xdf
 685                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xdf
 686                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xdf
 687                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xdf
 688                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xdf
 689                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xdf
 690                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xdf
 691                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xdf
 692                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xdf
 693                         MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x9f
 694                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
 695                 >;
 696         };
 697
 698         pinctrl_usdhc2: usdhc2grp {
 699                 fsl,pins = <
 700                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x83
 701                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc3
 702                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc3
 703                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc3
 704                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc3
 705                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc3
 706                         MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
 707                 >;
 708         };
 709
 710         pinctrl_usdhc2_100mhz: usdhc2-100grp {
 711                 fsl,pins = <
 712                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x85
 713                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc5
 714                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc5
 715                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc5
 716                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc5
 717                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc5
 718                         MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
 719                 >;
 720         };
 721
 722         pinctrl_usdhc2_200mhz: usdhc2-200grp {
 723                 fsl,pins = <
 724                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x87
 725                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc7
 726                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc7
 727                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc7
 728                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc7
 729                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc7
 730                         MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
 731                 >;
 732         };
 733 };