src/arm64/freescale/imx8mq-zii-ultra.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2019 Zodiac Inflight Innovations
   4  */
   5
   6 #include "imx8mq.dtsi"
   7
   8 / {
   9         aliases {
  10                 mdio-gpio0 = &mdio0;
  11                 rtc0 = &ds1341;
  12         };
  13
  14         chosen {
  15                 stdout-path = &uart1;
  16         };
  17
  18         mdio0: bitbang-mdio {
  19                 compatible = "virtual,mdio-gpio";
  20                 pinctrl-names = "default";
  21                 pinctrl-0 = <&pinctrl_mdio_bitbang>, <&pinctrl_fec1_phy_reset>;
  22                 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>, /* MDC */
  23                         <&gpio1 14 GPIO_ACTIVE_HIGH>; /* MDIO */
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 phy0: ethernet-phy@0 {
  28                         reg = <0>;
  29                         reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
  30                 };
  31         };
  32
  33         pcie0_refclk: clock-pcie0-refclk {
  34                 compatible = "fixed-clock";
  35                 #clock-cells = <0>;
  36                 clock-frequency = <100000000>;
  37         };
  38
  39         pcie1_refclk: clock-pcie1-refclk {
  40                 compatible = "fixed-clock";
  41                 #clock-cells = <0>;
  42                 clock-frequency = <100000000>;
  43         };
  44
  45         reg_12p0_main: regulator-12p0-main {
  46                 compatible = "regulator-fixed";
  47                 regulator-name = "12V_MAIN";
  48                 regulator-min-microvolt = <5000000>;
  49                 regulator-max-microvolt = <5000000>;
  50                 regulator-always-on;
  51         };
  52
  53         reg_5p0_main: regulator-5p0-main {
  54                 compatible = "regulator-fixed";
  55                 vin-supply = <&reg_12p0_main>;
  56                 regulator-name = "5V_MAIN";
  57                 regulator-min-microvolt = <5000000>;
  58                 regulator-max-microvolt = <5000000>;
  59                 regulator-always-on;
  60         };
  61
  62         reg_3p3_main: regulator-3p3-main {
  63                 compatible = "regulator-fixed";
  64                 vin-supply = <&reg_12p0_main>;
  65                 regulator-name = "3V3_MAIN";
  66                 regulator-min-microvolt = <3300000>;
  67                 regulator-max-microvolt = <3300000>;
  68                 regulator-always-on;
  69         };
  70
  71         reg_gen_3p3: regulator-gen-3p3 {
  72                 compatible = "regulator-fixed";
  73                 vin-supply = <&reg_3p3_main>;
  74                 regulator-name = "GEN_3V3";
  75                 regulator-min-microvolt = <3300000>;
  76                 regulator-max-microvolt = <3300000>;
  77                 regulator-always-on;
  78         };
  79
  80         reg_usdhc2_vmmc: regulator-vsd-3v3 {
  81                 pinctrl-names = "default";
  82                 pinctrl-0 = <&pinctrl_reg_usdhc2>;
  83                 compatible = "regulator-fixed";
  84                 vin-supply = <&reg_gen_3p3>;
  85                 regulator-name = "3V3_SD";
  86                 regulator-min-microvolt = <3300000>;
  87                 regulator-max-microvolt = <3300000>;
  88                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  89                 enable-active-high;
  90         };
  91
  92         reg_arm: regulator-arm {
  93                 pinctrl-names = "default";
  94                 pinctrl-0 = <&pinctrl_reg_arm>;
  95                 compatible = "regulator-gpio";
  96                 vin-supply = <&reg_12p0_main>;
  97                 regulator-name = "0V9_ARM";
  98                 regulator-min-microvolt = <900000>;
  99                 regulator-max-microvolt = <1000000>;
 100                 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
 101                 states = <1000000 0x1
 102                            900000 0x0>;
 103                 regulator-always-on;
 104         };
 105 };
 106
 107 &A53_0 {
 108         cpu-supply = <&reg_arm>;
 109 };
 110
 111 &A53_1 {
 112         cpu-supply = <&reg_arm>;
 113 };
 114
 115 &A53_2 {
 116         cpu-supply = <&reg_arm>;
 117 };
 118
 119 &A53_3 {
 120         cpu-supply = <&reg_arm>;
 121 };
 122
 123 &fec1 {
 124         pinctrl-names = "default";
 125         pinctrl-0 = <&pinctrl_fec1>;
 126
 127         phy-handle = <&phy0>;
 128         phy-mode = "rmii";
 129         status = "okay";
 130
 131         mdio {
 132                 #address-cells = <1>;
 133                 #size-cells = <0>;
 134                 status = "okay";
 135
 136                 switch: switch@0 {
 137                         compatible = "marvell,mv88e6085";
 138                         pinctrl-0 = <&pinctrl_switch_irq>;
 139                         pinctrl-names = "default";
 140                         reg = <0>;
 141                         dsa,member = <0 0>;
 142                         eeprom-length = <512>;
 143                         interrupt-parent = <&gpio1>;
 144                         interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
 145                         interrupt-controller;
 146                         #interrupt-cells = <2>;
 147
 148                         ports {
 149                                 #address-cells = <1>;
 150                                 #size-cells = <0>;
 151
 152                                 port@0 {
 153                                         reg = <0>;
 154                                         label = "gigabit_proc";
 155                                         phy-handle = <&switchphy0>;
 156                                 };
 157
 158                                 port@1 {
 159                                         reg = <1>;
 160                                         label = "netaux";
 161                                         phy-handle = <&switchphy1>;
 162                                 };
 163
 164                                 port@2 {
 165                                         reg = <2>;
 166                                         label = "cpu";
 167                                         ethernet = <&fec1>;
 168
 169                                         fixed-link {
 170                                                 speed = <100>;
 171                                                 full-duplex;
 172                                         };
 173                                 };
 174
 175                                 port@3 {
 176                                         reg = <3>;
 177                                         label = "netright";
 178                                         phy-handle = <&switchphy3>;
 179                                 };
 180
 181                                 port@4 {
 182                                         reg = <4>;
 183                                         label = "netleft";
 184                                         phy-handle = <&switchphy4>;
 185                                 };
 186                         };
 187
 188                         mdio {
 189                                 #address-cells = <1>;
 190                                 #size-cells = <0>;
 191
 192                                 switchphy0: switchphy@0 {
 193                                         reg = <0>;
 194                                         interrupt-parent = <&switch>;
 195                                         interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 196                                 };
 197
 198                                 switchphy1: switchphy@1 {
 199                                         reg = <1>;
 200                                         interrupt-parent = <&switch>;
 201                                         interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 202                                 };
 203
 204                                 switchphy2: switchphy@2 {
 205                                         reg = <2>;
 206                                         interrupt-parent = <&switch>;
 207                                         interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 208                                 };
 209
 210                                 switchphy3: switchphy@3 {
 211                                         reg = <3>;
 212                                         interrupt-parent = <&switch>;
 213                                         interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
 214                                 };
 215
 216                                 switchphy4: switchphy@4 {
 217                                         reg = <4>;
 218                                         interrupt-parent = <&switch>;
 219                                         interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 220                                 };
 221                         };
 222                 };
 223         };
 224 };
 225
 226 &gpio3 {
 227         pinctrl-names = "default";
 228         pinctrl-0 = <&pinctrl_gpio3_hog>;
 229
 230         usb-emulation {
 231                 gpio-hog;
 232                 gpios = <10 GPIO_ACTIVE_HIGH>;
 233                 output-low;
 234                 line-name = "usb-emulation";
 235         };
 236
 237         usb-mode1 {
 238                 gpio-hog;
 239                 gpios = <11 GPIO_ACTIVE_HIGH>;
 240                 output-high;
 241                 line-name = "usb-mode1";
 242         };
 243
 244         usb-pwr {
 245                 gpio-hog;
 246                 gpios = <12 GPIO_ACTIVE_LOW>;
 247                 output-high;
 248                 line-name = "usb-pwr-ctrl-en-n";
 249         };
 250
 251         usb-mode2 {
 252                 gpio-hog;
 253                 gpios = <13 GPIO_ACTIVE_HIGH>;
 254                 output-high;
 255                 line-name = "usb-mode2";
 256         };
 257 };
 258
 259 &i2c1 {
 260         clock-frequency = <400000>;
 261         pinctrl-names = "default";
 262         pinctrl-0 = <&pinctrl_i2c1>;
 263         status = "okay";
 264
 265         accelerometer@1c {
 266                 compatible = "fsl,mma8451";
 267                 pinctrl-names = "default";
 268                 pinctrl-0 = <&pinctrl_accel>;
 269                 reg = <0x1c>;
 270                 interrupt-parent = <&gpio3>;
 271                 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
 272                 interrupt-names = "INT2";
 273                 vdd-supply = <&reg_gen_3p3>;
 274                 vddio-supply = <&reg_gen_3p3>;
 275         };
 276
 277         ucs1002: charger@32 {
 278                 compatible = "microchip,ucs1002";
 279                 pinctrl-names = "default";
 280                 pinctrl-0 = <&pinctrl_ucs1002>;
 281                 reg = <0x32>;
 282                 interrupt-parent = <&gpio3>;
 283                 interrupts = <17 IRQ_TYPE_EDGE_BOTH>,
 284                              <18 IRQ_TYPE_EDGE_BOTH>;
 285                 interrupt-names = "a_det", "alert";
 286         };
 287 };
 288
 289 &i2c2 {
 290         clock-frequency = <400000>;
 291         pinctrl-names = "default";
 292         pinctrl-0 = <&pinctrl_i2c2>;
 293         status = "okay";
 294
 295         pmic@8 {
 296                 compatible = "fsl,pfuze100";
 297                 reg = <0x8>;
 298
 299                 regulators {
 300                         sw1a_reg: sw1ab {
 301                                 regulator-min-microvolt = <825000>;
 302                                 regulator-max-microvolt = <1100000>;
 303                         };
 304
 305                         sw1c_reg: sw1c {
 306                                 regulator-min-microvolt = <825000>;
 307                                 regulator-max-microvolt = <1100000>;
 308                         };
 309
 310                         sw2_reg: sw2 {
 311                                 regulator-min-microvolt = <1100000>;
 312                                 regulator-max-microvolt = <1100000>;
 313                                 regulator-always-on;
 314                         };
 315
 316                         sw3a_reg: sw3ab {
 317                                 regulator-min-microvolt = <825000>;
 318                                 regulator-max-microvolt = <1100000>;
 319                                 regulator-always-on;
 320                         };
 321
 322                         sw4_reg: sw4 {
 323                                 regulator-min-microvolt = <1800000>;
 324                                 regulator-max-microvolt = <1800000>;
 325                                 regulator-always-on;
 326                         };
 327
 328                         swbst_reg: swbst {
 329                                 regulator-min-microvolt = <5000000>;
 330                                 regulator-max-microvolt = <5150000>;
 331                         };
 332
 333                         snvs_reg: vsnvs {
 334                                 regulator-min-microvolt = <1000000>;
 335                                 regulator-max-microvolt = <3000000>;
 336                                 regulator-always-on;
 337                         };
 338
 339                         vref_reg: vrefddr {
 340                                 regulator-always-on;
 341                         };
 342
 343                         vgen1_reg: vgen1 {
 344                                 regulator-min-microvolt = <800000>;
 345                                 regulator-max-microvolt = <1550000>;
 346                         };
 347
 348                         vgen2_reg: vgen2 {
 349                                 regulator-min-microvolt = <850000>;
 350                                 regulator-max-microvolt = <975000>;
 351                                 regulator-always-on;
 352                         };
 353
 354                         vgen3_reg: vgen3 {
 355                                 regulator-min-microvolt = <1675000>;
 356                                 regulator-max-microvolt = <1975000>;
 357                                 regulator-always-on;
 358                         };
 359
 360                         vgen4_reg: vgen4 {
 361                                 regulator-min-microvolt = <1625000>;
 362                                 regulator-max-microvolt = <1875000>;
 363                                 regulator-always-on;
 364                         };
 365
 366                         vgen5_reg: vgen5 {
 367                                 regulator-min-microvolt = <3075000>;
 368                                 regulator-max-microvolt = <3625000>;
 369                                 regulator-always-on;
 370                         };
 371
 372                         vgen6_reg: vgen6 {
 373                                 regulator-min-microvolt = <1800000>;
 374                                 regulator-max-microvolt = <3300000>;
 375                         };
 376                 };
 377         };
 378
 379         eeprom@54 {
 380                 compatible = "atmel,24c128";
 381                 reg = <0x54>;
 382         };
 383
 384         ds1341: rtc@68 {
 385                 compatible = "dallas,ds1341";
 386                 reg = <0x68>;
 387         };
 388 };
 389
 390 &i2c3 {
 391         clock-frequency = <100000>;
 392         pinctrl-names = "default";
 393         pinctrl-0 = <&pinctrl_i2c3>;
 394         status = "okay";
 395
 396         usbhub: usbhub@2c {
 397                 compatible ="microchip,usb2513b";
 398                 pinctrl-names = "default";
 399                 pinctrl-0 = <&pinctrl_usbhub>;
 400                 reg = <0x2c>;
 401                 reset-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
 402         };
 403
 404         watchdog@38 {
 405                 compatible = "zii,rave-wdt";
 406                 reg = <0x38>;
 407         };
 408 };
 409
 410 &i2c4 {
 411         clock-frequency = <400000>;
 412         pinctrl-names = "default";
 413         pinctrl-0 = <&pinctrl_i2c4>;
 414         status = "okay";
 415 };
 416
 417 &uart1 {
 418         pinctrl-names = "default";
 419         pinctrl-0 = <&pinctrl_uart1>;
 420         status = "okay";
 421 };
 422
 423 &uart2 {
 424         pinctrl-names = "default";
 425         pinctrl-0 = <&pinctrl_uart2>;
 426         status = "okay";
 427
 428         rave-sp {
 429                 compatible = "zii,rave-sp-rdu2";
 430                 current-speed = <1000000>;
 431                 #address-cells = <1>;
 432                 #size-cells = <1>;
 433
 434                 watchdog {
 435                         compatible = "zii,rave-sp-watchdog";
 436                 };
 437
 438                 backlight {
 439                         compatible = "zii,rave-sp-backlight";
 440                 };
 441
 442                 pwrbutton {
 443                         compatible = "zii,rave-sp-pwrbutton";
 444                 };
 445
 446                 eeprom@a3 {
 447                         compatible = "zii,rave-sp-eeprom";
 448                         reg = <0xa3 0x4000>;
 449                         zii,eeprom-name = "dds-eeprom";
 450                 };
 451
 452                 eeprom@a4 {
 453                         compatible = "zii,rave-sp-eeprom";
 454                         reg = <0xa4 0x4000>;
 455                         #address-cells = <1>;
 456                         #size-cells = <1>;
 457                         zii,eeprom-name = "main-eeprom";
 458                 };
 459         };
 460 };
 461
 462 &usb3_phy0 {
 463         vbus-supply = <&ucs1002>;
 464         status = "okay";
 465 };
 466
 467 &usb_dwc3_0 {
 468         dr_mode = "host";
 469         status = "okay";
 470 };
 471
 472 &usb3_phy1 {
 473         vbus-supply = <&reg_5p0_main>;
 474         status = "okay";
 475 };
 476
 477 &usb_dwc3_1 {
 478         dr_mode = "host";
 479         status = "okay";
 480 };
 481
 482 &pcie0 {
 483         pinctrl-names = "default";
 484         pinctrl-0 = <&pinctrl_pcie0>;
 485         reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
 486         clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
 487                  <&clk IMX8MQ_CLK_PCIE1_AUX>,
 488                  <&clk IMX8MQ_CLK_PCIE1_PHY>,
 489                  <&pcie0_refclk>;
 490         clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
 491         status = "okay";
 492 };
 493
 494 &pcie1 {
 495         pinctrl-names = "default";
 496         pinctrl-0 = <&pinctrl_pcie1>;
 497         reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
 498         clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
 499                  <&clk IMX8MQ_CLK_PCIE2_AUX>,
 500                  <&clk IMX8MQ_CLK_PCIE2_PHY>,
 501                  <&pcie1_refclk>;
 502         clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
 503         status = "okay";
 504 };
 505
 506 &pgc_gpu {
 507         power-supply = <&sw1a_reg>;
 508 };
 509
 510 &pgc_vpu {
 511         power-supply = <&sw1c_reg>;
 512 };
 513
 514 &usdhc1 {
 515         assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
 516         assigned-clock-rates = <400000000>;
 517         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 518         pinctrl-0 = <&pinctrl_usdhc1>;
 519         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 520         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 521         vqmmc-supply = <&sw4_reg>;
 522         bus-width = <8>;
 523         non-removable;
 524         no-sd;
 525         no-sdio;
 526         status = "okay";
 527 };
 528
 529 &usdhc2 {
 530         assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
 531         assigned-clock-rates = <200000000>;
 532         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 533         pinctrl-0 = <&pinctrl_usdhc2>;
 534         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 535         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 536         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 537         vmmc-supply = <&reg_usdhc2_vmmc>;
 538         status = "okay";
 539 };
 540
 541 &snvs_rtc {
 542         status = "disabled";
 543 };
 544
 545 &iomuxc {
 546         pinctrl_accel: accelgrp {
 547                 fsl,pins = <
 548                         MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20                0x41
 549                 >;
 550         };
 551
 552         pinctrl_fec1: fec1grp {
 553                 fsl,pins = <
 554                         MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 555                         MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO               0x23
 556                         MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
 557                         MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
 558                         MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 559                         MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 560                         MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK              0x1f
 561                         MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER               0x91
 562                         MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 563                         MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 564                 >;
 565         };
 566
 567         pinctrl_fec1_phy_reset: fec1phyresetgrp {
 568                 fsl,pins = <
 569                         MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29                0x11
 570                 >;
 571         };
 572
 573         pinctrl_gpio3_hog: gpio3hoggrp {
 574                 fsl,pins = <
 575                         MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10             0x6
 576                         MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11             0x6
 577                         MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12             0x6
 578                         MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13             0x6
 579                 >;
 580         };
 581
 582         pinctrl_i2c1: i2c1grp {
 583                 fsl,pins = <
 584                         MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL                  0x4000007f
 585                         MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA                  0x4000007f
 586                 >;
 587         };
 588
 589         pinctrl_i2c2: i2c2grp {
 590                 fsl,pins = <
 591                         MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL                  0x4000007f
 592                         MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA                  0x4000007f
 593                 >;
 594         };
 595
 596         pinctrl_i2c3: i2c3grp {
 597                 fsl,pins = <
 598                         MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL                  0x4000007f
 599                         MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA                  0x4000007f
 600                 >;
 601         };
 602
 603         pinctrl_i2c4: i2c4grp {
 604                 fsl,pins = <
 605                         MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL                  0x4000007f
 606                         MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA                  0x4000007f
 607                 >;
 608         };
 609
 610         pinctrl_mdio_bitbang: bitbangmdiogrp {
 611                 fsl,pins = <
 612                         MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x44
 613                         MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14              0x64
 614                 >;
 615         };
 616
 617         pinctrl_pcie0: pcie0grp {
 618                 fsl,pins = <
 619                         MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B           0x66
 620                         MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3               0x6
 621                 >;
 622         };
 623
 624         pinctrl_pcie1: pcie1grp {
 625                 fsl,pins = <
 626                         MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B           0x66
 627                         MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6               0x6
 628                 >;
 629         };
 630
 631         pinctrl_reg_arm: regarmgrp {
 632                 fsl,pins = <
 633                         MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16            0x19
 634                 >;
 635         };
 636
 637         pinctrl_reg_usdhc2: regusdhc2grp {
 638                 fsl,pins = <
 639                         MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19             0x41
 640                 >;
 641         };
 642
 643         pinctrl_switch_irq: switchgrp {
 644                 fsl,pins = <
 645                         MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15              0x41
 646                 >;
 647         };
 648
 649         pinctrl_ts: tsgrp {
 650                 fsl,pins = <
 651                         MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11              0x96
 652                         MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12              0x96
 653                 >;
 654         };
 655
 656         pinctrl_uart1: uart1grp {
 657                 fsl,pins = <
 658                         MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX             0x49
 659                         MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX             0x49
 660                 >;
 661         };
 662
 663         pinctrl_uart2: uart2grp {
 664                 fsl,pins = <
 665                         MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX             0x49
 666                         MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX             0x49
 667                 >;
 668         };
 669
 670         pinctrl_ucs1002: ucs1002grp {
 671                 fsl,pins = <
 672                         MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17               0x41
 673                         MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18               0x41
 674                 >;
 675         };
 676
 677         pinctrl_usbhub: usbhubgrp {
 678                 fsl,pins = <
 679                         MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25               0x41
 680                 >;
 681         };
 682
 683         pinctrl_usdhc1: usdhc1grp {
 684                 fsl,pins = <
 685                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x83
 686                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xc3
 687                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xc3
 688                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xc3
 689                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xc3
 690                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xc3
 691                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xc3
 692                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xc3
 693                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xc3
 694                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xc3
 695                         MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x83
 696                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
 697                 >;
 698         };
 699
 700         pinctrl_usdhc1_100mhz: usdhc1-100grp {
 701                 fsl,pins = <
 702                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x8d
 703                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xcd
 704                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xcd
 705                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xcd
 706                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xcd
 707                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xcd
 708                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xcd
 709                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xcd
 710                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xcd
 711                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xcd
 712                         MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x8d
 713                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
 714                 >;
 715         };
 716
 717         pinctrl_usdhc1_200mhz: usdhc1-200grp {
 718                 fsl,pins = <
 719                         MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                 0x9f
 720                         MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                 0xdf
 721                         MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0             0xdf
 722                         MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1             0xdf
 723                         MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2             0xdf
 724                         MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3             0xdf
 725                         MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4             0xdf
 726                         MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5             0xdf
 727                         MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6             0xdf
 728                         MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7             0xdf
 729                         MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x9f
 730                         MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0xc1
 731                 >;
 732         };
 733
 734         pinctrl_usdhc2: usdhc2grp {
 735                 fsl,pins = <
 736                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x83
 737                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc3
 738                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc3
 739                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc3
 740                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc3
 741                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc3
 742                         MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
 743                 >;
 744         };
 745
 746         pinctrl_usdhc2_100mhz: usdhc2-100grp {
 747                 fsl,pins = <
 748                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x85
 749                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc5
 750                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc5
 751                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc5
 752                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc5
 753                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc5
 754                         MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
 755                 >;
 756         };
 757
 758         pinctrl_usdhc2_200mhz: usdhc2-200grp {
 759                 fsl,pins = <
 760                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x87
 761                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc7
 762                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc7
 763                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc7
 764                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc7
 765                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc7
 766                         MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xc1
 767                 >;
 768         };
 769 };