src/arm64/marvell/armada-3720-uDPU.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device tree for the uDPU board.
   4  * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)
   5  * Copyright (C) 2016 Marvell
   6  * Copyright (C) 2019 Methode Electronics
   7  * Copyright (C) 2019 Telus
   8  *
   9  * Vladimir Vid <vladimir.vid@sartura.hr>
  10  */
  11
  12 /dts-v1/;
  13
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include "armada-372x.dtsi"
  16
  17 / {
  18         model = "Methode uDPU Board";
  19         compatible = "methode,udpu", "marvell,armada3720";
  20
  21         chosen {
  22                 stdout-path = "serial0:115200n8";
  23         };
  24
  25         memory@0 {
  26                 device_type = "memory";
  27                 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
  28         };
  29
  30         leds {
  31                 pinctrl-names = "default";
  32                 compatible = "gpio-leds";
  33
  34                 power1 {
  35                         label = "udpu:green:power";
  36                         gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
  37                 };
  38
  39                 power2 {
  40                         label = "udpu:red:power";
  41                         gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
  42                 };
  43
  44                 network1 {
  45                         label = "udpu:green:network";
  46                         gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
  47                 };
  48
  49                 network2 {
  50                         label = "udpu:red:network";
  51                         gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
  52                 };
  53
  54                 alarm1 {
  55                         label = "udpu:green:alarm";
  56                         gpios = <&gpionb 15 GPIO_ACTIVE_LOW>;
  57                 };
  58
  59                 alarm2 {
  60                         label = "udpu:red:alarm";
  61                         gpios = <&gpionb 16 GPIO_ACTIVE_LOW>;
  62                 };
  63         };
  64
  65         sfp_eth0: sfp-eth0 {
  66                 compatible = "sff,sfp";
  67                 i2c-bus = <&i2c0>;
  68                 los-gpio = <&gpiosb 2 GPIO_ACTIVE_HIGH>;
  69                 mod-def0-gpio = <&gpiosb 3 GPIO_ACTIVE_LOW>;
  70                 tx-disable-gpio = <&gpiosb 4 GPIO_ACTIVE_HIGH>;
  71                 tx-fault-gpio = <&gpiosb 5 GPIO_ACTIVE_HIGH>;
  72                 maximum-power-milliwatt = <3000>;
  73         };
  74
  75         sfp_eth1: sfp-eth1 {
  76                 compatible = "sff,sfp";
  77                 i2c-bus = <&i2c1>;
  78                 los-gpio = <&gpiosb 7 GPIO_ACTIVE_HIGH>;
  79                 mod-def0-gpio = <&gpiosb 8 GPIO_ACTIVE_LOW>;
  80                 tx-disable-gpio = <&gpiosb 9 GPIO_ACTIVE_HIGH>;
  81                 tx-fault-gpio = <&gpiosb 10 GPIO_ACTIVE_HIGH>;
  82                 maximum-power-milliwatt = <3000>;
  83         };
  84 };
  85
  86 &sdhci0 {
  87         status = "okay";
  88         bus-width = <8>;
  89         mmc-ddr-1_8v;
  90         mmc-hs400-1_8v;
  91         marvell,pad-type = "fixed-1-8v";
  92         non-removable;
  93         no-sd;
  94         no-sdio;
  95 };
  96
  97 &spi0 {
  98         status = "okay";
  99         pinctrl-names = "default";
 100         pinctrl-0 = <&spi_quad_pins>;
 101
 102         m25p80@0 {
 103                 compatible = "jedec,spi-nor";
 104                 reg = <0>;
 105                 spi-max-frequency = <54000000>;
 106
 107                 partitions {
 108                         compatible = "fixed-partitions";
 109                         #address-cells = <1>;
 110                         #size-cells = <1>;
 111                         /* only bootloader is located on the SPI */
 112                         partition@0 {
 113                                 label = "uboot";
 114                                 reg = <0 0x400000>;
 115                         };
 116                 };
 117         };
 118 };
 119
 120 &pinctrl_nb {
 121         i2c1_recovery_pins: i2c1-recovery-pins {
 122                 groups = "i2c1";
 123                 function = "gpio";
 124         };
 125
 126         i2c2_recovery_pins: i2c2-recovery-pins {
 127                 groups = "i2c2";
 128                 function = "gpio";
 129         };
 130 };
 131
 132 &i2c0 {
 133         status = "okay";
 134         pinctrl-names = "default", "recovery";
 135         pinctrl-0 = <&i2c1_pins>;
 136         pinctrl-1 = <&i2c1_recovery_pins>;
 137         /delete-property/mrvl,i2c-fast-mode;
 138         scl-gpios = <&gpionb 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 139         sda-gpios = <&gpionb 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 140 };
 141
 142 &i2c1 {
 143         status = "okay";
 144         pinctrl-names = "default", "recovery";
 145         pinctrl-0 = <&i2c2_pins>;
 146         pinctrl-1 = <&i2c2_recovery_pins>;
 147         /delete-property/mrvl,i2c-fast-mode;
 148         scl-gpios = <&gpionb 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 149         sda-gpios = <&gpionb 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 150
 151         lm75@48 {
 152                 status = "okay";
 153                 compatible = "lm75";
 154                 reg = <0x48>;
 155         };
 156
 157         lm75@49 {
 158                 status = "okay";
 159                 compatible = "lm75";
 160                 reg = <0x49>;
 161         };
 162 };
 163
 164 &eth0 {
 165         phy-mode = "sgmii";
 166         status = "okay";
 167         managed = "in-band-status";
 168         phys = <&comphy1 0>;
 169         sfp = <&sfp_eth0>;
 170 };
 171
 172 &eth1 {
 173         phy-mode = "sgmii";
 174         status = "okay";
 175         managed = "in-band-status";
 176         phys = <&comphy0 1>;
 177         sfp = <&sfp_eth1>;
 178 };
 179
 180 &usb3 {
 181         status = "okay";
 182         phys = <&usb2_utmi_otg_phy>;
 183         phy-names = "usb2-utmi-otg-phy";
 184 };
 185
 186 &uart0 {
 187         status = "okay";
 188 };