2 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPLv2 or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
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44 * Device Tree file for Marvell Armada 7040 Development board platform
47 #include <dt-bindings/gpio/gpio.h>
48 #include "armada-7040.dtsi"
51 model = "Marvell Armada 7040 DB board";
52 compatible = "marvell,armada7040-db", "marvell,armada7040",
53 "marvell,armada-ap806-quad", "marvell,armada-ap806";
56 stdout-path = "serial0:115200n8";
60 device_type = "memory";
61 reg = <0x0 0x0 0x0 0x80000000>;
64 cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus {
65 compatible = "regulator-fixed";
66 regulator-name = "usb3h0-vbus";
67 regulator-min-microvolt = <5000000>;
68 regulator-max-microvolt = <5000000>;
70 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
73 cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus {
74 compatible = "regulator-fixed";
75 regulator-name = "usb3h1-vbus";
76 regulator-min-microvolt = <5000000>;
77 regulator-max-microvolt = <5000000>;
79 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
82 cpm_usb3_0_phy: cpm-usb3-0-phy {
83 compatible = "usb-nop-xceiv";
84 vcc-supply = <&cpm_reg_usb3_0_vbus>;
87 cpm_usb3_1_phy: cpm-usb3-1-phy {
88 compatible = "usb-nop-xceiv";
89 vcc-supply = <&cpm_reg_usb3_1_vbus>;
95 clock-frequency = <100000>;
102 #address-cells = <1>;
104 compatible = "jedec,spi-nor";
106 spi-max-frequency = <10000000>;
109 compatible = "fixed-partitions";
110 #address-cells = <1>;
118 label = "Filesystem";
119 reg = <0x200000 0xce0000>;
127 pinctrl-0 = <&uart0_pins>;
128 pinctrl-names = "default";
138 clock-frequency = <100000>;
140 expander0: pca9555@21 {
141 compatible = "nxp,pca9555";
142 pinctrl-names = "default";
147 * IO0_0: USB3_PWR_EN0 IO1_0: USB_3_1_Dev_Detect
148 * IO0_1: USB3_PWR_EN1 IO1_1: USB2_1_current_limit
149 * IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN
150 * IO0_3: USB2_DEVICE_DETECT
151 * IO0_4: GPIO_0 IO1_4: SD_Status
152 * IO0_5: GPIO_1 IO1_5: LDO_5V_Enable
153 * IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC
154 * IO0_7: IO1_7: SDIO_Vcntrl
161 * SPI on CPM and NAND have common pins on this board. We can
162 * use only one at a time. To enable the NAND (whihch will
163 * disable the SPI), the "status = "okay";" line have to be
167 pinctrl-0 = <&nand_pins>, <&nand_rb>;
168 pinctrl-names = "default";
169 nand-ecc-strength = <4>;
170 nand-ecc-step-size = <512>;
171 marvell,nand-enable-arbiter;
180 reg = <0x200000 0xe00000>;
183 label = "Filesystem";
184 reg = <0x1000000 0x3f000000>;
193 #address-cells = <0x1>;
195 compatible = "jedec,spi-nor";
197 spi-max-frequency = <20000000>;
200 compatible = "fixed-partitions";
201 #address-cells = <1>;
206 reg = <0x0 0x200000>;
210 label = "Filesystem";
211 reg = <0x200000 0xe00000>;
222 usb-phy = <&cpm_usb3_0_phy>;
227 usb-phy = <&cpm_usb3_1_phy>;
242 cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
248 phy0: ethernet-phy@0 {
251 phy1: ethernet-phy@1 {
263 phy-mode = "10gbase-kr";
264 /* Generic PHY, providing serdes lanes */
265 phys = <&cpm_comphy2 0>;
273 /* Generic PHY, providing serdes lanes */
274 phys = <&cpm_comphy0 1>;
280 phy-mode = "rgmii-id";