src/arm64/mediatek/mt8186.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 /*
   3  * Copyright (C) 2022 MediaTek Inc.
   4  * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
   5  */
   6 /dts-v1/;
   7 #include <dt-bindings/clock/mt8186-clk.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/memory/mt8186-memory-port.h>
  11 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
  12 #include <dt-bindings/power/mt8186-power.h>
  13 #include <dt-bindings/phy/phy.h>
  14 #include <dt-bindings/reset/mt8186-resets.h>
  15
  16 / {
  17         compatible = "mediatek,mt8186";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25
  26                 cpu-map {
  27                         cluster0 {
  28                                 core0 {
  29                                         cpu = <&cpu0>;
  30                                 };
  31
  32                                 core1 {
  33                                         cpu = <&cpu1>;
  34                                 };
  35
  36                                 core2 {
  37                                         cpu = <&cpu2>;
  38                                 };
  39
  40                                 core3 {
  41                                         cpu = <&cpu3>;
  42                                 };
  43
  44                                 core4 {
  45                                         cpu = <&cpu4>;
  46                                 };
  47
  48                                 core5 {
  49                                         cpu = <&cpu5>;
  50                                 };
  51
  52                                 core6 {
  53                                         cpu = <&cpu6>;
  54                                 };
  55
  56                                 core7 {
  57                                         cpu = <&cpu7>;
  58                                 };
  59                         };
  60                 };
  61
  62                 cpu0: cpu@0 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a55";
  65                         reg = <0x000>;
  66                         enable-method = "psci";
  67                         clock-frequency = <2000000000>;
  68                         capacity-dmips-mhz = <382>;
  69                         cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
  70                         i-cache-size = <32768>;
  71                         i-cache-line-size = <64>;
  72                         i-cache-sets = <128>;
  73                         d-cache-size = <32768>;
  74                         d-cache-line-size = <64>;
  75                         d-cache-sets = <128>;
  76                         next-level-cache = <&l2_0>;
  77                         #cooling-cells = <2>;
  78                 };
  79
  80                 cpu1: cpu@100 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a55";
  83                         reg = <0x100>;
  84                         enable-method = "psci";
  85                         clock-frequency = <2000000000>;
  86                         capacity-dmips-mhz = <382>;
  87                         cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
  88                         i-cache-size = <32768>;
  89                         i-cache-line-size = <64>;
  90                         i-cache-sets = <128>;
  91                         d-cache-size = <32768>;
  92                         d-cache-line-size = <64>;
  93                         d-cache-sets = <128>;
  94                         next-level-cache = <&l2_0>;
  95                         #cooling-cells = <2>;
  96                 };
  97
  98                 cpu2: cpu@200 {
  99                         device_type = "cpu";
 100                         compatible = "arm,cortex-a55";
 101                         reg = <0x200>;
 102                         enable-method = "psci";
 103                         clock-frequency = <2000000000>;
 104                         capacity-dmips-mhz = <382>;
 105                         cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
 106                         i-cache-size = <32768>;
 107                         i-cache-line-size = <64>;
 108                         i-cache-sets = <128>;
 109                         d-cache-size = <32768>;
 110                         d-cache-line-size = <64>;
 111                         d-cache-sets = <128>;
 112                         next-level-cache = <&l2_0>;
 113                         #cooling-cells = <2>;
 114                 };
 115
 116                 cpu3: cpu@300 {
 117                         device_type = "cpu";
 118                         compatible = "arm,cortex-a55";
 119                         reg = <0x300>;
 120                         enable-method = "psci";
 121                         clock-frequency = <2000000000>;
 122                         capacity-dmips-mhz = <382>;
 123                         cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
 124                         i-cache-size = <32768>;
 125                         i-cache-line-size = <64>;
 126                         i-cache-sets = <128>;
 127                         d-cache-size = <32768>;
 128                         d-cache-line-size = <64>;
 129                         d-cache-sets = <128>;
 130                         next-level-cache = <&l2_0>;
 131                         #cooling-cells = <2>;
 132                 };
 133
 134                 cpu4: cpu@400 {
 135                         device_type = "cpu";
 136                         compatible = "arm,cortex-a55";
 137                         reg = <0x400>;
 138                         enable-method = "psci";
 139                         clock-frequency = <2000000000>;
 140                         capacity-dmips-mhz = <382>;
 141                         cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
 142                         i-cache-size = <32768>;
 143                         i-cache-line-size = <64>;
 144                         i-cache-sets = <128>;
 145                         d-cache-size = <32768>;
 146                         d-cache-line-size = <64>;
 147                         d-cache-sets = <128>;
 148                         next-level-cache = <&l2_0>;
 149                         #cooling-cells = <2>;
 150                 };
 151
 152                 cpu5: cpu@500 {
 153                         device_type = "cpu";
 154                         compatible = "arm,cortex-a55";
 155                         reg = <0x500>;
 156                         enable-method = "psci";
 157                         clock-frequency = <2000000000>;
 158                         capacity-dmips-mhz = <382>;
 159                         cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
 160                         i-cache-size = <32768>;
 161                         i-cache-line-size = <64>;
 162                         i-cache-sets = <128>;
 163                         d-cache-size = <32768>;
 164                         d-cache-line-size = <64>;
 165                         d-cache-sets = <128>;
 166                         next-level-cache = <&l2_0>;
 167                         #cooling-cells = <2>;
 168                 };
 169
 170                 cpu6: cpu@600 {
 171                         device_type = "cpu";
 172                         compatible = "arm,cortex-a76";
 173                         reg = <0x600>;
 174                         enable-method = "psci";
 175                         clock-frequency = <2050000000>;
 176                         capacity-dmips-mhz = <1024>;
 177                         cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
 178                         i-cache-size = <65536>;
 179                         i-cache-line-size = <64>;
 180                         i-cache-sets = <256>;
 181                         d-cache-size = <65536>;
 182                         d-cache-line-size = <64>;
 183                         d-cache-sets = <256>;
 184                         next-level-cache = <&l2_1>;
 185                         #cooling-cells = <2>;
 186                 };
 187
 188                 cpu7: cpu@700 {
 189                         device_type = "cpu";
 190                         compatible = "arm,cortex-a76";
 191                         reg = <0x700>;
 192                         enable-method = "psci";
 193                         clock-frequency = <2050000000>;
 194                         capacity-dmips-mhz = <1024>;
 195                         cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
 196                         i-cache-size = <65536>;
 197                         i-cache-line-size = <64>;
 198                         i-cache-sets = <256>;
 199                         d-cache-size = <65536>;
 200                         d-cache-line-size = <64>;
 201                         d-cache-sets = <256>;
 202                         next-level-cache = <&l2_1>;
 203                         #cooling-cells = <2>;
 204                 };
 205
 206                 idle-states {
 207                         entry-method = "psci";
 208
 209                         cpu_ret_l: cpu-retention-l {
 210                                 compatible = "arm,idle-state";
 211                                 arm,psci-suspend-param = <0x00010001>;
 212                                 local-timer-stop;
 213                                 entry-latency-us = <50>;
 214                                 exit-latency-us = <100>;
 215                                 min-residency-us = <1600>;
 216                         };
 217
 218                         cpu_ret_b: cpu-retention-b {
 219                                 compatible = "arm,idle-state";
 220                                 arm,psci-suspend-param = <0x00010001>;
 221                                 local-timer-stop;
 222                                 entry-latency-us = <50>;
 223                                 exit-latency-us = <100>;
 224                                 min-residency-us = <1400>;
 225                         };
 226
 227                         cpu_off_l: cpu-off-l {
 228                                 compatible = "arm,idle-state";
 229                                 arm,psci-suspend-param = <0x01010001>;
 230                                 local-timer-stop;
 231                                 entry-latency-us = <100>;
 232                                 exit-latency-us = <250>;
 233                                 min-residency-us = <2100>;
 234                         };
 235
 236                         cpu_off_b: cpu-off-b {
 237                                 compatible = "arm,idle-state";
 238                                 arm,psci-suspend-param = <0x01010001>;
 239                                 local-timer-stop;
 240                                 entry-latency-us = <100>;
 241                                 exit-latency-us = <250>;
 242                                 min-residency-us = <1900>;
 243                         };
 244                 };
 245
 246                 l2_0: l2-cache0 {
 247                         compatible = "cache";
 248                         cache-level = <2>;
 249                         cache-size = <131072>;
 250                         cache-line-size = <64>;
 251                         cache-sets = <512>;
 252                         next-level-cache = <&l3_0>;
 253                 };
 254
 255                 l2_1: l2-cache1 {
 256                         compatible = "cache";
 257                         cache-level = <2>;
 258                         cache-size = <262144>;
 259                         cache-line-size = <64>;
 260                         cache-sets = <512>;
 261                         next-level-cache = <&l3_0>;
 262                 };
 263
 264                 l3_0: l3-cache {
 265                         compatible = "cache";
 266                         cache-level = <3>;
 267                         cache-size = <1048576>;
 268                         cache-line-size = <64>;
 269                         cache-sets = <1024>;
 270                         cache-unified;
 271                 };
 272         };
 273
 274         clk13m: fixed-factor-clock-13m {
 275                 compatible = "fixed-factor-clock";
 276                 #clock-cells = <0>;
 277                 clocks = <&clk26m>;
 278                 clock-div = <2>;
 279                 clock-mult = <1>;
 280                 clock-output-names = "clk13m";
 281         };
 282
 283         clk26m: oscillator-26m {
 284                 compatible = "fixed-clock";
 285                 #clock-cells = <0>;
 286                 clock-frequency = <26000000>;
 287                 clock-output-names = "clk26m";
 288         };
 289
 290         clk32k: oscillator-32k {
 291                 compatible = "fixed-clock";
 292                 #clock-cells = <0>;
 293                 clock-frequency = <32768>;
 294                 clock-output-names = "clk32k";
 295         };
 296
 297         pmu-a55 {
 298                 compatible = "arm,cortex-a55-pmu";
 299                 interrupt-parent = <&gic>;
 300                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
 301         };
 302
 303         pmu-a76 {
 304                 compatible = "arm,cortex-a76-pmu";
 305                 interrupt-parent = <&gic>;
 306                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
 307         };
 308
 309         psci {
 310                 compatible = "arm,psci-1.0";
 311                 method = "smc";
 312         };
 313
 314         timer {
 315                 compatible = "arm,armv8-timer";
 316                 interrupt-parent = <&gic>;
 317                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 318                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 319                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 320                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 321         };
 322
 323         soc {
 324                 #address-cells = <2>;
 325                 #size-cells = <2>;
 326                 compatible = "simple-bus";
 327                 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
 328                 ranges;
 329
 330                 gic: interrupt-controller@c000000 {
 331                         compatible = "arm,gic-v3";
 332                         #interrupt-cells = <4>;
 333                         #redistributor-regions = <1>;
 334                         interrupt-parent = <&gic>;
 335                         interrupt-controller;
 336                         reg = <0 0x0c000000 0 0x40000>,
 337                               <0 0x0c040000 0 0x200000>;
 338                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 339
 340                         ppi-partitions {
 341                                 ppi_cluster0: interrupt-partition-0 {
 342                                         affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
 343                                 };
 344
 345                                 ppi_cluster1: interrupt-partition-1 {
 346                                         affinity = <&cpu6 &cpu7>;
 347                                 };
 348                         };
 349                 };
 350
 351                 mcusys: syscon@c53a000 {
 352                         compatible = "mediatek,mt8186-mcusys", "syscon";
 353                         reg = <0 0xc53a000 0 0x1000>;
 354                         #clock-cells = <1>;
 355                 };
 356
 357                 topckgen: syscon@10000000 {
 358                         compatible = "mediatek,mt8186-topckgen", "syscon";
 359                         reg = <0 0x10000000 0 0x1000>;
 360                         #clock-cells = <1>;
 361                 };
 362
 363                 infracfg_ao: syscon@10001000 {
 364                         compatible = "mediatek,mt8186-infracfg_ao", "syscon";
 365                         reg = <0 0x10001000 0 0x1000>;
 366                         #clock-cells = <1>;
 367                         #reset-cells = <1>;
 368                 };
 369
 370                 pericfg: syscon@10003000 {
 371                         compatible = "mediatek,mt8186-pericfg", "syscon";
 372                         reg = <0 0x10003000 0 0x1000>;
 373                 };
 374
 375                 pio: pinctrl@10005000 {
 376                         compatible = "mediatek,mt8186-pinctrl";
 377                         reg = <0 0x10005000 0 0x1000>,
 378                               <0 0x10002000 0 0x0200>,
 379                               <0 0x10002200 0 0x0200>,
 380                               <0 0x10002400 0 0x0200>,
 381                               <0 0x10002600 0 0x0200>,
 382                               <0 0x10002a00 0 0x0200>,
 383                               <0 0x10002c00 0 0x0200>,
 384                               <0 0x1000b000 0 0x1000>;
 385                         reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb",
 386                                     "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint";
 387                         gpio-controller;
 388                         #gpio-cells = <2>;
 389                         gpio-ranges = <&pio 0 0 185>;
 390                         interrupt-controller;
 391                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
 392                         #interrupt-cells = <2>;
 393                 };
 394
 395                 scpsys: syscon@10006000 {
 396                         compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd";
 397                         reg = <0 0x10006000 0 0x1000>;
 398
 399                         /* System Power Manager */
 400                         spm: power-controller {
 401                                 compatible = "mediatek,mt8186-power-controller";
 402                                 #address-cells = <1>;
 403                                 #size-cells = <0>;
 404                                 #power-domain-cells = <1>;
 405
 406                                 /* power domain of the SoC */
 407                                 mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 {
 408                                         reg = <MT8186_POWER_DOMAIN_MFG0>;
 409                                         clocks = <&topckgen CLK_TOP_MFG>;
 410                                         clock-names = "mfg00";
 411                                         #address-cells = <1>;
 412                                         #size-cells = <0>;
 413                                         #power-domain-cells = <1>;
 414
 415                                         power-domain@MT8186_POWER_DOMAIN_MFG1 {
 416                                                 reg = <MT8186_POWER_DOMAIN_MFG1>;
 417                                                 mediatek,infracfg = <&infracfg_ao>;
 418                                                 #address-cells = <1>;
 419                                                 #size-cells = <0>;
 420                                                 #power-domain-cells = <1>;
 421
 422                                                 power-domain@MT8186_POWER_DOMAIN_MFG2 {
 423                                                         reg = <MT8186_POWER_DOMAIN_MFG2>;
 424                                                         #power-domain-cells = <0>;
 425                                                 };
 426
 427                                                 power-domain@MT8186_POWER_DOMAIN_MFG3 {
 428                                                         reg = <MT8186_POWER_DOMAIN_MFG3>;
 429                                                         #power-domain-cells = <0>;
 430                                                 };
 431                                         };
 432                                 };
 433
 434                                 power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP {
 435                                         reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>;
 436                                         clocks = <&topckgen CLK_TOP_SENINF>,
 437                                                  <&topckgen CLK_TOP_SENINF1>;
 438                                         clock-names = "csirx_top0", "csirx_top1";
 439                                         #power-domain-cells = <0>;
 440                                 };
 441
 442                                 power-domain@MT8186_POWER_DOMAIN_SSUSB {
 443                                         reg = <MT8186_POWER_DOMAIN_SSUSB>;
 444                                         #power-domain-cells = <0>;
 445                                 };
 446
 447                                 power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 {
 448                                         reg = <MT8186_POWER_DOMAIN_SSUSB_P1>;
 449                                         #power-domain-cells = <0>;
 450                                 };
 451
 452                                 power-domain@MT8186_POWER_DOMAIN_ADSP_AO {
 453                                         reg = <MT8186_POWER_DOMAIN_ADSP_AO>;
 454                                         clocks = <&topckgen CLK_TOP_AUDIODSP>,
 455                                                  <&topckgen CLK_TOP_ADSP_BUS>;
 456                                         clock-names = "audioadsp", "adsp_bus";
 457                                         #address-cells = <1>;
 458                                         #size-cells = <0>;
 459                                         #power-domain-cells = <1>;
 460
 461                                         power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA {
 462                                                 reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>;
 463                                                 #address-cells = <1>;
 464                                                 #size-cells = <0>;
 465                                                 #power-domain-cells = <1>;
 466
 467                                                 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP {
 468                                                         reg = <MT8186_POWER_DOMAIN_ADSP_TOP>;
 469                                                         mediatek,infracfg = <&infracfg_ao>;
 470                                                         #power-domain-cells = <0>;
 471                                                 };
 472                                         };
 473                                 };
 474
 475                                 power-domain@MT8186_POWER_DOMAIN_CONN_ON {
 476                                         reg = <MT8186_POWER_DOMAIN_CONN_ON>;
 477                                         mediatek,infracfg = <&infracfg_ao>;
 478                                         #power-domain-cells = <0>;
 479                                 };
 480
 481                                 power-domain@MT8186_POWER_DOMAIN_DIS {
 482                                         reg = <MT8186_POWER_DOMAIN_DIS>;
 483                                         clocks = <&topckgen CLK_TOP_DISP>,
 484                                                  <&topckgen CLK_TOP_MDP>,
 485                                                  <&mmsys CLK_MM_SMI_INFRA>,
 486                                                  <&mmsys CLK_MM_SMI_COMMON>,
 487                                                  <&mmsys CLK_MM_SMI_GALS>,
 488                                                  <&mmsys CLK_MM_SMI_IOMMU>;
 489                                         clock-names = "disp", "mdp", "smi_infra", "smi_common",
 490                                                      "smi_gals", "smi_iommu";
 491                                         mediatek,infracfg = <&infracfg_ao>;
 492                                         #address-cells = <1>;
 493                                         #size-cells = <0>;
 494                                         #power-domain-cells = <1>;
 495
 496                                         power-domain@MT8186_POWER_DOMAIN_VDEC {
 497                                                 reg = <MT8186_POWER_DOMAIN_VDEC>;
 498                                                 clocks = <&topckgen CLK_TOP_VDEC>,
 499                                                          <&vdecsys CLK_VDEC_LARB1_CKEN>;
 500                                                 clock-names = "vdec0", "larb";
 501                                                 mediatek,infracfg = <&infracfg_ao>;
 502                                                 #power-domain-cells = <0>;
 503                                         };
 504
 505                                         power-domain@MT8186_POWER_DOMAIN_CAM {
 506                                                 reg = <MT8186_POWER_DOMAIN_CAM>;
 507                                                 clocks = <&topckgen CLK_TOP_CAM>,
 508                                                          <&topckgen CLK_TOP_SENINF>,
 509                                                          <&topckgen CLK_TOP_SENINF1>,
 510                                                          <&topckgen CLK_TOP_SENINF2>,
 511                                                          <&topckgen CLK_TOP_SENINF3>,
 512                                                          <&topckgen CLK_TOP_CAMTM>,
 513                                                          <&camsys CLK_CAM2MM_GALS>;
 514                                                 clock-names = "cam-top", "cam0", "cam1", "cam2",
 515                                                              "cam3", "cam-tm", "gals";
 516                                                 mediatek,infracfg = <&infracfg_ao>;
 517                                                 #address-cells = <1>;
 518                                                 #size-cells = <0>;
 519                                                 #power-domain-cells = <1>;
 520
 521                                                 power-domain@MT8186_POWER_DOMAIN_CAM_RAWB {
 522                                                         reg = <MT8186_POWER_DOMAIN_CAM_RAWB>;
 523                                                         #power-domain-cells = <0>;
 524                                                 };
 525
 526                                                 power-domain@MT8186_POWER_DOMAIN_CAM_RAWA {
 527                                                         reg = <MT8186_POWER_DOMAIN_CAM_RAWA>;
 528                                                         #power-domain-cells = <0>;
 529                                                 };
 530                                         };
 531
 532                                         power-domain@MT8186_POWER_DOMAIN_IMG {
 533                                                 reg = <MT8186_POWER_DOMAIN_IMG>;
 534                                                 clocks = <&topckgen CLK_TOP_IMG1>,
 535                                                          <&imgsys1 CLK_IMG1_GALS_IMG1>;
 536                                                 clock-names = "img-top", "gals";
 537                                                 mediatek,infracfg = <&infracfg_ao>;
 538                                                 #address-cells = <1>;
 539                                                 #size-cells = <0>;
 540                                                 #power-domain-cells = <1>;
 541
 542                                                 power-domain@MT8186_POWER_DOMAIN_IMG2 {
 543                                                         reg = <MT8186_POWER_DOMAIN_IMG2>;
 544                                                         #power-domain-cells = <0>;
 545                                                 };
 546                                         };
 547
 548                                         power-domain@MT8186_POWER_DOMAIN_IPE {
 549                                                 reg = <MT8186_POWER_DOMAIN_IPE>;
 550                                                 clocks = <&topckgen CLK_TOP_IPE>,
 551                                                          <&ipesys CLK_IPE_LARB19>,
 552                                                          <&ipesys CLK_IPE_LARB20>,
 553                                                          <&ipesys CLK_IPE_SMI_SUBCOM>,
 554                                                          <&ipesys CLK_IPE_GALS_IPE>;
 555                                                 clock-names = "ipe-top", "ipe-larb0", "ipe-larb1",
 556                                                               "ipe-smi", "ipe-gals";
 557                                                 mediatek,infracfg = <&infracfg_ao>;
 558                                                 #power-domain-cells = <0>;
 559                                         };
 560
 561                                         power-domain@MT8186_POWER_DOMAIN_VENC {
 562                                                 reg = <MT8186_POWER_DOMAIN_VENC>;
 563                                                 clocks = <&topckgen CLK_TOP_VENC>,
 564                                                          <&vencsys CLK_VENC_CKE1_VENC>;
 565                                                 clock-names = "venc0", "larb";
 566                                                 mediatek,infracfg = <&infracfg_ao>;
 567                                                 #power-domain-cells = <0>;
 568                                         };
 569
 570                                         power-domain@MT8186_POWER_DOMAIN_WPE {
 571                                                 reg = <MT8186_POWER_DOMAIN_WPE>;
 572                                                 clocks = <&topckgen CLK_TOP_WPE>,
 573                                                          <&wpesys CLK_WPE_SMI_LARB8_CK_EN>,
 574                                                          <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>;
 575                                                 clock-names = "wpe0", "larb-ck", "larb-pclk";
 576                                                 mediatek,infracfg = <&infracfg_ao>;
 577                                                 #power-domain-cells = <0>;
 578                                         };
 579                                 };
 580                         };
 581                 };
 582
 583                 watchdog: watchdog@10007000 {
 584                         compatible = "mediatek,mt8186-wdt";
 585                         mediatek,disable-extrst;
 586                         reg = <0 0x10007000 0 0x1000>;
 587                         #reset-cells = <1>;
 588                 };
 589
 590                 apmixedsys: syscon@1000c000 {
 591                         compatible = "mediatek,mt8186-apmixedsys", "syscon";
 592                         reg = <0 0x1000c000 0 0x1000>;
 593                         #clock-cells = <1>;
 594                 };
 595
 596                 pwrap: pwrap@1000d000 {
 597                         compatible = "mediatek,mt8186-pwrap", "syscon";
 598                         reg = <0 0x1000d000 0 0x1000>;
 599                         reg-names = "pwrap";
 600                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
 601                         clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
 602                                  <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
 603                         clock-names = "spi", "wrap";
 604                 };
 605
 606                 systimer: timer@10017000 {
 607                         compatible = "mediatek,mt8186-timer",
 608                                      "mediatek,mt6765-timer";
 609                         reg = <0 0x10017000 0 0x1000>;
 610                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>;
 611                         clocks = <&clk13m>;
 612                 };
 613
 614                 scp: scp@10500000 {
 615                         compatible = "mediatek,mt8186-scp";
 616                         reg = <0 0x10500000 0 0x40000>,
 617                               <0 0x105c0000 0 0x19080>;
 618                         reg-names = "sram", "cfg";
 619                         interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
 620                 };
 621
 622                 adsp_mailbox0: mailbox@10686000 {
 623                         compatible = "mediatek,mt8186-adsp-mbox";
 624                         #mbox-cells = <0>;
 625                         reg = <0 0x10686100 0 0x1000>;
 626                         interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>;
 627                 };
 628
 629                 adsp_mailbox1: mailbox@10687000 {
 630                         compatible = "mediatek,mt8186-adsp-mbox";
 631                         #mbox-cells = <0>;
 632                         reg = <0 0x10687100 0 0x1000>;
 633                         interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>;
 634                 };
 635
 636                 nor_flash: spi@11000000 {
 637                         compatible = "mediatek,mt8186-nor";
 638                         reg = <0 0x11000000 0 0x1000>;
 639                         clocks = <&topckgen CLK_TOP_SPINOR>,
 640                                  <&infracfg_ao CLK_INFRA_AO_SPINOR>,
 641                                  <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>,
 642                                  <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>;
 643                         clock-names = "spi", "sf", "axi", "axi_s";
 644                         assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
 645                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>;
 646                         interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>;
 647                         status = "disabled";
 648                 };
 649
 650                 auxadc: adc@11001000 {
 651                         compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc";
 652                         reg = <0 0x11001000 0 0x1000>;
 653                         #io-channel-cells = <1>;
 654                         clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
 655                         clock-names = "main";
 656                 };
 657
 658                 uart0: serial@11002000 {
 659                         compatible = "mediatek,mt8186-uart",
 660                                      "mediatek,mt6577-uart";
 661                         reg = <0 0x11002000 0 0x1000>;
 662                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
 663                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
 664                         clock-names = "baud", "bus";
 665                         status = "disabled";
 666                 };
 667
 668                 uart1: serial@11003000 {
 669                         compatible = "mediatek,mt8186-uart",
 670                                      "mediatek,mt6577-uart";
 671                         reg = <0 0x11003000 0 0x1000>;
 672                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
 673                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
 674                         clock-names = "baud", "bus";
 675                         status = "disabled";
 676                 };
 677
 678                 i2c0: i2c@11007000 {
 679                         compatible = "mediatek,mt8186-i2c";
 680                         reg = <0 0x11007000 0 0x1000>,
 681                               <0 0x10200100 0 0x100>;
 682                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 683                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>,
 684                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
 685                         clock-names = "main", "dma";
 686                         clock-div = <1>;
 687                         #address-cells = <1>;
 688                         #size-cells = <0>;
 689                         status = "disabled";
 690                 };
 691
 692                 i2c1: i2c@11008000 {
 693                         compatible = "mediatek,mt8186-i2c";
 694                         reg = <0 0x11008000 0 0x1000>,
 695                               <0 0x10200200 0 0x100>;
 696                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
 697                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>,
 698                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
 699                         clock-names = "main", "dma";
 700                         clock-div = <1>;
 701                         #address-cells = <1>;
 702                         #size-cells = <0>;
 703                         status = "disabled";
 704                 };
 705
 706                 i2c2: i2c@11009000 {
 707                         compatible = "mediatek,mt8186-i2c";
 708                         reg = <0 0x11009000 0 0x1000>,
 709                               <0 0x10200300 0 0x180>;
 710                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>;
 711                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>,
 712                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
 713                         clock-names = "main", "dma";
 714                         clock-div = <1>;
 715                         #address-cells = <1>;
 716                         #size-cells = <0>;
 717                         status = "disabled";
 718                 };
 719
 720                 i2c3: i2c@1100f000 {
 721                         compatible = "mediatek,mt8186-i2c";
 722                         reg = <0 0x1100f000 0 0x1000>,
 723                               <0 0x10200480 0 0x100>;
 724                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
 725                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>,
 726                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
 727                         clock-names = "main", "dma";
 728                         clock-div = <1>;
 729                         #address-cells = <1>;
 730                         #size-cells = <0>;
 731                         status = "disabled";
 732                 };
 733
 734                 i2c4: i2c@11011000 {
 735                         compatible = "mediatek,mt8186-i2c";
 736                         reg = <0 0x11011000 0 0x1000>,
 737                               <0 0x10200580 0 0x180>;
 738                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
 739                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>,
 740                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
 741                         clock-names = "main", "dma";
 742                         clock-div = <1>;
 743                         #address-cells = <1>;
 744                         #size-cells = <0>;
 745                         status = "disabled";
 746                 };
 747
 748                 i2c5: i2c@11016000 {
 749                         compatible = "mediatek,mt8186-i2c";
 750                         reg = <0 0x11016000 0 0x1000>,
 751                               <0 0x10200700 0 0x100>;
 752                         interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>;
 753                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>,
 754                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
 755                         clock-names = "main", "dma";
 756                         clock-div = <1>;
 757                         #address-cells = <1>;
 758                         #size-cells = <0>;
 759                         status = "disabled";
 760                 };
 761
 762                 i2c6: i2c@1100d000 {
 763                         compatible = "mediatek,mt8186-i2c";
 764                         reg = <0 0x1100d000 0 0x1000>,
 765                               <0 0x10200800 0 0x100>;
 766                         interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
 767                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>,
 768                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
 769                         clock-names = "main", "dma";
 770                         clock-div = <1>;
 771                         #address-cells = <1>;
 772                         #size-cells = <0>;
 773                         status = "disabled";
 774                 };
 775
 776                 i2c7: i2c@11004000 {
 777                         compatible = "mediatek,mt8186-i2c";
 778                         reg = <0 0x11004000 0 0x1000>,
 779                               <0 0x10200900 0 0x180>;
 780                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 781                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>,
 782                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
 783                         clock-names = "main", "dma";
 784                         clock-div = <1>;
 785                         #address-cells = <1>;
 786                         #size-cells = <0>;
 787                         status = "disabled";
 788                 };
 789
 790                 i2c8: i2c@11005000 {
 791                         compatible = "mediatek,mt8186-i2c";
 792                         reg = <0 0x11005000 0 0x1000>,
 793                               <0 0x10200A80 0 0x180>;
 794                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
 795                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>,
 796                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
 797                         clock-names = "main", "dma";
 798                         clock-div = <1>;
 799                         #address-cells = <1>;
 800                         #size-cells = <0>;
 801                         status = "disabled";
 802                 };
 803
 804                 spi0: spi@1100a000 {
 805                         compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
 806                         #address-cells = <1>;
 807                         #size-cells = <0>;
 808                         reg = <0 0x1100a000 0 0x1000>;
 809                         interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>;
 810                         clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
 811                                  <&topckgen CLK_TOP_SPI>,
 812                                  <&infracfg_ao CLK_INFRA_AO_SPI0>;
 813                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 814                         status = "disabled";
 815                 };
 816
 817                 pwm0: pwm@1100e000 {
 818                         compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm";
 819                         reg = <0 0x1100e000 0 0x1000>;
 820                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
 821                         #pwm-cells = <2>;
 822                         clocks = <&topckgen CLK_TOP_DISP_PWM>,
 823                                  <&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
 824                         clock-names = "main", "mm";
 825                         status = "disabled";
 826                 };
 827
 828                 spi1: spi@11010000 {
 829                         compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
 830                         #address-cells = <1>;
 831                         #size-cells = <0>;
 832                         reg = <0 0x11010000 0 0x1000>;
 833                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>;
 834                         clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
 835                                  <&topckgen CLK_TOP_SPI>,
 836                                  <&infracfg_ao CLK_INFRA_AO_SPI1>;
 837                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 838                         status = "disabled";
 839                 };
 840
 841                 spi2: spi@11012000 {
 842                         compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
 843                         #address-cells = <1>;
 844                         #size-cells = <0>;
 845                         reg = <0 0x11012000 0 0x1000>;
 846                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>;
 847                         clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
 848                                  <&topckgen CLK_TOP_SPI>,
 849                                  <&infracfg_ao CLK_INFRA_AO_SPI2>;
 850                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 851                         status = "disabled";
 852                 };
 853
 854                 spi3: spi@11013000 {
 855                         compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
 856                         #address-cells = <1>;
 857                         #size-cells = <0>;
 858                         reg = <0 0x11013000 0 0x1000>;
 859                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>;
 860                         clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
 861                                  <&topckgen CLK_TOP_SPI>,
 862                                  <&infracfg_ao CLK_INFRA_AO_SPI3>;
 863                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 864                         status = "disabled";
 865                 };
 866
 867                 spi4: spi@11014000 {
 868                         compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
 869                         #address-cells = <1>;
 870                         #size-cells = <0>;
 871                         reg = <0 0x11014000 0 0x1000>;
 872                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
 873                         clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
 874                                  <&topckgen CLK_TOP_SPI>,
 875                                  <&infracfg_ao CLK_INFRA_AO_SPI4>;
 876                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 877                         status = "disabled";
 878                 };
 879
 880                 spi5: spi@11015000 {
 881                         compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
 882                         #address-cells = <1>;
 883                         #size-cells = <0>;
 884                         reg = <0 0x11015000 0 0x1000>;
 885                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
 886                         clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
 887                                  <&topckgen CLK_TOP_SPI>,
 888                                  <&infracfg_ao CLK_INFRA_AO_SPI5>;
 889                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 890                         status = "disabled";
 891                 };
 892
 893                 imp_iic_wrap: clock-controller@11017000 {
 894                         compatible = "mediatek,mt8186-imp_iic_wrap";
 895                         reg = <0 0x11017000 0 0x1000>;
 896                         #clock-cells = <1>;
 897                 };
 898
 899                 uart2: serial@11018000 {
 900                         compatible = "mediatek,mt8186-uart",
 901                                      "mediatek,mt6577-uart";
 902                         reg = <0 0x11018000 0 0x1000>;
 903                         interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>;
 904                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
 905                         clock-names = "baud", "bus";
 906                         status = "disabled";
 907                 };
 908
 909                 i2c9: i2c@11019000 {
 910                         compatible = "mediatek,mt8186-i2c";
 911                         reg = <0 0x11019000 0 0x1000>,
 912                               <0 0x10200c00 0 0x180>;
 913                         interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
 914                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>,
 915                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
 916                         clock-names = "main", "dma";
 917                         clock-div = <1>;
 918                         #address-cells = <1>;
 919                         #size-cells = <0>;
 920                         status = "disabled";
 921                 };
 922
 923                 afe: audio-controller@11210000 {
 924                         compatible = "mediatek,mt8186-sound";
 925                         reg = <0 0x11210000 0 0x2000>;
 926                         clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>,
 927                                  <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>,
 928                                  <&topckgen CLK_TOP_AUDIO>,
 929                                  <&topckgen CLK_TOP_AUD_INTBUS>,
 930                                  <&topckgen CLK_TOP_MAINPLL_D2_D4>,
 931                                  <&topckgen CLK_TOP_AUD_1>,
 932                                  <&apmixedsys CLK_APMIXED_APLL1>,
 933                                  <&topckgen CLK_TOP_AUD_2>,
 934                                  <&apmixedsys CLK_APMIXED_APLL2>,
 935                                  <&topckgen CLK_TOP_AUD_ENGEN1>,
 936                                  <&topckgen CLK_TOP_APLL1_D8>,
 937                                  <&topckgen CLK_TOP_AUD_ENGEN2>,
 938                                  <&topckgen CLK_TOP_APLL2_D8>,
 939                                  <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>,
 940                                  <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>,
 941                                  <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>,
 942                                  <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>,
 943                                  <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>,
 944                                  <&topckgen CLK_TOP_APLL12_CK_DIV0>,
 945                                  <&topckgen CLK_TOP_APLL12_CK_DIV1>,
 946                                  <&topckgen CLK_TOP_APLL12_CK_DIV2>,
 947                                  <&topckgen CLK_TOP_APLL12_CK_DIV4>,
 948                                  <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>,
 949                                  <&topckgen CLK_TOP_AUDIO_H>,
 950                                  <&clk26m>;
 951                         clock-names = "aud_infra_clk",
 952                                       "mtkaif_26m_clk",
 953                                       "top_mux_audio",
 954                                       "top_mux_audio_int",
 955                                       "top_mainpll_d2_d4",
 956                                       "top_mux_aud_1",
 957                                       "top_apll1_ck",
 958                                       "top_mux_aud_2",
 959                                       "top_apll2_ck",
 960                                       "top_mux_aud_eng1",
 961                                       "top_apll1_d8",
 962                                       "top_mux_aud_eng2",
 963                                       "top_apll2_d8",
 964                                       "top_i2s0_m_sel",
 965                                       "top_i2s1_m_sel",
 966                                       "top_i2s2_m_sel",
 967                                       "top_i2s4_m_sel",
 968                                       "top_tdm_m_sel",
 969                                       "top_apll12_div0",
 970                                       "top_apll12_div1",
 971                                       "top_apll12_div2",
 972                                       "top_apll12_div4",
 973                                       "top_apll12_div_tdm",
 974                                       "top_mux_audio_h",
 975                                       "top_clk26m_clk";
 976                         interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
 977                         mediatek,apmixedsys = <&apmixedsys>;
 978                         mediatek,infracfg = <&infracfg_ao>;
 979                         mediatek,topckgen = <&topckgen>;
 980                         resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>;
 981                         reset-names = "audiosys";
 982                         status = "disabled";
 983                 };
 984
 985                 mmc0: mmc@11230000 {
 986                         compatible = "mediatek,mt8186-mmc",
 987                                      "mediatek,mt8183-mmc";
 988                         reg = <0 0x11230000 0 0x10000>,
 989                               <0 0x11cd0000 0 0x1000>;
 990                         clocks = <&topckgen CLK_TOP_MSDC50_0>,
 991                                  <&infracfg_ao CLK_INFRA_AO_MSDC0>,
 992                                  <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>,
 993                                  <&infracfg_ao CLK_INFRA_AO_MSDCFDE>;
 994                         clock-names = "source", "hclk", "source_cg", "crypto";
 995                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 996                         assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>;
 997                         assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>;
 998                         status = "disabled";
 999                 };
1000
1001                 mmc1: mmc@11240000 {
1002                         compatible = "mediatek,mt8186-mmc",
1003                                      "mediatek,mt8183-mmc";
1004                         reg = <0 0x11240000 0 0x1000>,
1005                               <0 0x11c90000 0 0x1000>;
1006                         clocks = <&topckgen CLK_TOP_MSDC30_1>,
1007                                  <&infracfg_ao CLK_INFRA_AO_MSDC1>,
1008                                  <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
1009                         clock-names = "source", "hclk", "source_cg";
1010                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
1011                         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1012                         assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1013                         status = "disabled";
1014                 };
1015
1016                 u3phy0: t-phy@11c80000 {
1017                         compatible = "mediatek,mt8186-tphy",
1018                                      "mediatek,generic-tphy-v2";
1019                         #address-cells = <1>;
1020                         #size-cells = <1>;
1021                         ranges = <0x0 0x0 0x11c80000 0x1000>;
1022                         status = "disabled";
1023
1024                         u2port1: usb-phy@0 {
1025                                 reg = <0x0 0x700>;
1026                                 clocks = <&clk26m>;
1027                                 clock-names = "ref";
1028                                 #phy-cells = <1>;
1029                         };
1030
1031                         u3port1: usb-phy@700 {
1032                                 reg = <0x700 0x900>;
1033                                 clocks = <&clk26m>;
1034                                 clock-names = "ref";
1035                                 #phy-cells = <1>;
1036                         };
1037                 };
1038
1039                 u3phy1: t-phy@11ca0000 {
1040                         compatible = "mediatek,mt8186-tphy",
1041                                      "mediatek,generic-tphy-v2";
1042                         #address-cells = <1>;
1043                         #size-cells = <1>;
1044                         ranges = <0x0 0x0 0x11ca0000 0x1000>;
1045                         status = "disabled";
1046
1047                         u2port0: usb-phy@0 {
1048                                 reg = <0x0 0x700>;
1049                                 clocks = <&clk26m>;
1050                                 clock-names = "ref";
1051                                 #phy-cells = <1>;
1052                                 mediatek,discth = <0x8>;
1053                         };
1054                 };
1055
1056                 efuse: efuse@11cb0000 {
1057                         compatible = "mediatek,mt8186-efuse", "mediatek,efuse";
1058                         reg = <0 0x11cb0000 0 0x1000>;
1059                         #address-cells = <1>;
1060                         #size-cells = <1>;
1061                 };
1062
1063                 mipi_tx0: dsi-phy@11cc0000 {
1064                         compatible = "mediatek,mt8183-mipi-tx";
1065                         reg = <0 0x11cc0000 0 0x1000>;
1066                         clocks = <&clk26m>;
1067                         #clock-cells = <0>;
1068                         #phy-cells = <0>;
1069                         clock-output-names = "mipi_tx0_pll";
1070                         status = "disabled";
1071                 };
1072
1073                 mfgsys: clock-controller@13000000 {
1074                         compatible = "mediatek,mt8186-mfgsys";
1075                         reg = <0 0x13000000 0 0x1000>;
1076                         #clock-cells = <1>;
1077                 };
1078
1079                 gpu: gpu@13040000 {
1080                         compatible = "mediatek,mt8186-mali",
1081                                      "arm,mali-bifrost";
1082                         reg = <0 0x13040000 0 0x4000>;
1083
1084                         clocks = <&mfgsys CLK_MFG_BG3D>;
1085                         interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>,
1086                                      <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>,
1087                                      <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
1088                         interrupt-names = "job", "mmu", "gpu";
1089                         power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>,
1090                                         <&spm MT8186_POWER_DOMAIN_MFG3>;
1091                         power-domain-names = "core0", "core1";
1092                         #cooling-cells = <2>;
1093                         status = "disabled";
1094                 };
1095
1096                 mmsys: syscon@14000000 {
1097                         compatible = "mediatek,mt8186-mmsys", "syscon";
1098                         reg = <0 0x14000000 0 0x1000>;
1099                         #clock-cells = <1>;
1100                         #reset-cells = <1>;
1101                 };
1102
1103                 smi_common: smi@14002000 {
1104                         compatible = "mediatek,mt8186-smi-common";
1105                         reg = <0 0x14002000 0 0x1000>;
1106                         clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>,
1107                                  <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>;
1108                         clock-names = "apb", "smi", "gals0", "gals1";
1109                         power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1110                 };
1111
1112                 larb0: smi@14003000 {
1113                         compatible = "mediatek,mt8186-smi-larb";
1114                         reg = <0 0x14003000 0 0x1000>;
1115                         clocks = <&mmsys CLK_MM_SMI_COMMON>,
1116                                  <&mmsys CLK_MM_SMI_COMMON>;
1117                         clock-names = "apb", "smi";
1118                         mediatek,larb-id = <0>;
1119                         mediatek,smi = <&smi_common>;
1120                         power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1121                 };
1122
1123                 larb1: smi@14004000 {
1124                         compatible = "mediatek,mt8186-smi-larb";
1125                         reg = <0 0x14004000 0 0x1000>;
1126                         clocks = <&mmsys CLK_MM_SMI_COMMON>,
1127                                  <&mmsys CLK_MM_SMI_COMMON>;
1128                         clock-names = "apb", "smi";
1129                         mediatek,larb-id = <1>;
1130                         mediatek,smi = <&smi_common>;
1131                         power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1132                 };
1133
1134                 dpi: dpi@1400a000 {
1135                         compatible = "mediatek,mt8186-dpi";
1136                         reg = <0 0x1400a000 0 0x1000>;
1137                         clocks = <&topckgen CLK_TOP_DPI>,
1138                                  <&mmsys CLK_MM_DISP_DPI>,
1139                                  <&apmixedsys CLK_APMIXED_TVDPLL>;
1140                         clock-names = "pixel", "engine", "pll";
1141                         assigned-clocks = <&topckgen CLK_TOP_DPI>;
1142                         assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>;
1143                         interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>;
1144                         status = "disabled";
1145
1146                         port {
1147                                 dpi_out: endpoint { };
1148                         };
1149                 };
1150
1151                 dsi0: dsi@14013000 {
1152                         compatible = "mediatek,mt8186-dsi";
1153                         reg = <0 0x14013000 0 0x1000>;
1154                         clocks = <&mmsys CLK_MM_DSI0>,
1155                                  <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>,
1156                                  <&mipi_tx0>;
1157                         clock-names = "engine", "digital", "hs";
1158                         interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>;
1159                         power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1160                         resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>;
1161                         phys = <&mipi_tx0>;
1162                         phy-names = "dphy";
1163                         status = "disabled";
1164
1165                         port {
1166                                 dsi_out: endpoint { };
1167                         };
1168                 };
1169
1170                 iommu_mm: iommu@14016000 {
1171                         compatible = "mediatek,mt8186-iommu-mm";
1172                         reg = <0 0x14016000 0 0x1000>;
1173                         clocks = <&mmsys CLK_MM_SMI_IOMMU>;
1174                         clock-names = "bclk";
1175                         interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>;
1176                         mediatek,larbs = <&larb0 &larb1 &larb2 &larb4
1177                                           &larb7 &larb8 &larb9 &larb11
1178                                           &larb13 &larb14 &larb16 &larb17
1179                                           &larb19 &larb20>;
1180                         power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1181                         #iommu-cells = <1>;
1182                 };
1183
1184                 wpesys: clock-controller@14020000 {
1185                         compatible = "mediatek,mt8186-wpesys";
1186                         reg = <0 0x14020000 0 0x1000>;
1187                         #clock-cells = <1>;
1188                 };
1189
1190                 larb8: smi@14023000 {
1191                         compatible = "mediatek,mt8186-smi-larb";
1192                         reg = <0 0x14023000 0 0x1000>;
1193                         clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>,
1194                                  <&wpesys CLK_WPE_SMI_LARB8_CK_EN>;
1195                         clock-names = "apb", "smi";
1196                         mediatek,larb-id = <8>;
1197                         mediatek,smi = <&smi_common>;
1198                         power-domains = <&spm MT8186_POWER_DOMAIN_WPE>;
1199                 };
1200
1201                 imgsys1: clock-controller@15020000 {
1202                         compatible = "mediatek,mt8186-imgsys1";
1203                         reg = <0 0x15020000 0 0x1000>;
1204                         #clock-cells = <1>;
1205                 };
1206
1207                 larb9: smi@1502e000 {
1208                         compatible = "mediatek,mt8186-smi-larb";
1209                         reg = <0 0x1502e000 0 0x1000>;
1210                         clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>,
1211                                  <&imgsys1 CLK_IMG1_LARB9_IMG1>;
1212                         clock-names = "apb", "smi";
1213                         mediatek,larb-id = <9>;
1214                         mediatek,smi = <&smi_common>;
1215                         power-domains = <&spm MT8186_POWER_DOMAIN_IMG>;
1216                 };
1217
1218                 imgsys2: clock-controller@15820000 {
1219                         compatible = "mediatek,mt8186-imgsys2";
1220                         reg = <0 0x15820000 0 0x1000>;
1221                         #clock-cells = <1>;
1222                 };
1223
1224                 larb11: smi@1582e000 {
1225                         compatible = "mediatek,mt8186-smi-larb";
1226                         reg = <0 0x1582e000 0 0x1000>;
1227                         clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>,
1228                                  <&imgsys2 CLK_IMG2_LARB9_IMG2>;
1229                         clock-names = "apb", "smi";
1230                         mediatek,larb-id = <11>;
1231                         mediatek,smi = <&smi_common>;
1232                         power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>;
1233                 };
1234
1235                 larb4: smi@1602e000 {
1236                         compatible = "mediatek,mt8186-smi-larb";
1237                         reg = <0 0x1602e000 0 0x1000>;
1238                         clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>,
1239                                  <&vdecsys CLK_VDEC_LARB1_CKEN>;
1240                         clock-names = "apb", "smi";
1241                         mediatek,larb-id = <4>;
1242                         mediatek,smi = <&smi_common>;
1243                         power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>;
1244                 };
1245
1246                 vdecsys: clock-controller@1602f000 {
1247                         compatible = "mediatek,mt8186-vdecsys";
1248                         reg = <0 0x1602f000 0 0x1000>;
1249                         #clock-cells = <1>;
1250                 };
1251
1252                 vencsys: clock-controller@17000000 {
1253                         compatible = "mediatek,mt8186-vencsys";
1254                         reg = <0 0x17000000 0 0x1000>;
1255                         #clock-cells = <1>;
1256                 };
1257
1258                 larb7: smi@17010000 {
1259                         compatible = "mediatek,mt8186-smi-larb";
1260                         reg = <0 0x17010000 0 0x1000>;
1261                         clocks = <&vencsys CLK_VENC_CKE1_VENC>,
1262                                  <&vencsys CLK_VENC_CKE1_VENC>;
1263                         clock-names = "apb", "smi";
1264                         mediatek,larb-id = <7>;
1265                         mediatek,smi = <&smi_common>;
1266                         power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
1267                 };
1268
1269                 camsys: clock-controller@1a000000 {
1270                         compatible = "mediatek,mt8186-camsys";
1271                         reg = <0 0x1a000000 0 0x1000>;
1272                         #clock-cells = <1>;
1273                 };
1274
1275                 larb13: smi@1a001000 {
1276                         compatible = "mediatek,mt8186-smi-larb";
1277                         reg = <0 0x1a001000 0 0x1000>;
1278                         clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>;
1279                         clock-names = "apb", "smi";
1280                         mediatek,larb-id = <13>;
1281                         mediatek,smi = <&smi_common>;
1282                         power-domains = <&spm MT8186_POWER_DOMAIN_CAM>;
1283                 };
1284
1285                 larb14: smi@1a002000 {
1286                         compatible = "mediatek,mt8186-smi-larb";
1287                         reg = <0 0x1a002000 0 0x1000>;
1288                         clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>;
1289                         clock-names = "apb", "smi";
1290                         mediatek,larb-id = <14>;
1291                         mediatek,smi = <&smi_common>;
1292                         power-domains = <&spm MT8186_POWER_DOMAIN_CAM>;
1293                 };
1294
1295                 larb16: smi@1a00f000 {
1296                         compatible = "mediatek,mt8186-smi-larb";
1297                         reg = <0 0x1a00f000 0 0x1000>;
1298                         clocks = <&camsys CLK_CAM_LARB14>,
1299                                  <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>;
1300                         clock-names = "apb", "smi";
1301                         mediatek,larb-id = <16>;
1302                         mediatek,smi = <&smi_common>;
1303                         power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>;
1304                 };
1305
1306                 larb17: smi@1a010000 {
1307                         compatible = "mediatek,mt8186-smi-larb";
1308                         reg = <0 0x1a010000 0 0x1000>;
1309                         clocks = <&camsys CLK_CAM_LARB13>,
1310                                  <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>;
1311                         clock-names = "apb", "smi";
1312                         mediatek,larb-id = <17>;
1313                         mediatek,smi = <&smi_common>;
1314                         power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>;
1315                 };
1316
1317                 camsys_rawa: clock-controller@1a04f000 {
1318                         compatible = "mediatek,mt8186-camsys_rawa";
1319                         reg = <0 0x1a04f000 0 0x1000>;
1320                         #clock-cells = <1>;
1321                 };
1322
1323                 camsys_rawb: clock-controller@1a06f000 {
1324                         compatible = "mediatek,mt8186-camsys_rawb";
1325                         reg = <0 0x1a06f000 0 0x1000>;
1326                         #clock-cells = <1>;
1327                 };
1328
1329                 mdpsys: clock-controller@1b000000 {
1330                         compatible = "mediatek,mt8186-mdpsys";
1331                         reg = <0 0x1b000000 0 0x1000>;
1332                         #clock-cells = <1>;
1333                 };
1334
1335                 larb2: smi@1b002000 {
1336                         compatible = "mediatek,mt8186-smi-larb";
1337                         reg = <0 0x1b002000 0 0x1000>;
1338                         clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>;
1339                         clock-names = "apb", "smi";
1340                         mediatek,larb-id = <2>;
1341                         mediatek,smi = <&smi_common>;
1342                         power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1343                 };
1344
1345                 ipesys: clock-controller@1c000000 {
1346                         compatible = "mediatek,mt8186-ipesys";
1347                         reg = <0 0x1c000000 0 0x1000>;
1348                         #clock-cells = <1>;
1349                 };
1350
1351                 larb20: smi@1c00f000 {
1352                         compatible = "mediatek,mt8186-smi-larb";
1353                         reg = <0 0x1c00f000 0 0x1000>;
1354                         clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>;
1355                         clock-names = "apb", "smi";
1356                         mediatek,larb-id = <20>;
1357                         mediatek,smi = <&smi_common>;
1358                         power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
1359                 };
1360
1361                 larb19: smi@1c10f000 {
1362                         compatible = "mediatek,mt8186-smi-larb";
1363                         reg = <0 0x1c10f000 0 0x1000>;
1364                         clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>;
1365                         clock-names = "apb", "smi";
1366                         mediatek,larb-id = <19>;
1367                         mediatek,smi = <&smi_common>;
1368                         power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
1369                 };
1370         };
1371 };