src/arm64/mediatek/mt8192.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2020 MediaTek Inc.
   4  * Author: Seiya Wang <seiya.wang@mediatek.com>
   5  */
   6
   7 /dts-v1/;
   8 #include <dt-bindings/clock/mt8192-clk.h>
   9 #include <dt-bindings/gce/mt8192-gce.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include <dt-bindings/memory/mt8192-larb-port.h>
  13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
  14 #include <dt-bindings/phy/phy.h>
  15 #include <dt-bindings/power/mt8192-power.h>
  16 #include <dt-bindings/reset/mt8192-resets.h>
  17
  18 / {
  19         compatible = "mediatek,mt8192";
  20         interrupt-parent = <&gic>;
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         aliases {
  25                 ovl0 = &ovl0;
  26                 ovl-2l0 = &ovl_2l0;
  27                 ovl-2l2 = &ovl_2l2;
  28                 rdma0 = &rdma0;
  29                 rdma4 = &rdma4;
  30         };
  31
  32         clk26m: oscillator0 {
  33                 compatible = "fixed-clock";
  34                 #clock-cells = <0>;
  35                 clock-frequency = <26000000>;
  36                 clock-output-names = "clk26m";
  37         };
  38
  39         clk32k: oscillator1 {
  40                 compatible = "fixed-clock";
  41                 #clock-cells = <0>;
  42                 clock-frequency = <32768>;
  43                 clock-output-names = "clk32k";
  44         };
  45
  46         cpus {
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49
  50                 cpu0: cpu@0 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a55";
  53                         reg = <0x000>;
  54                         enable-method = "psci";
  55                         clock-frequency = <1701000000>;
  56                         cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
  57                         next-level-cache = <&l2_0>;
  58                         capacity-dmips-mhz = <530>;
  59                 };
  60
  61                 cpu1: cpu@100 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a55";
  64                         reg = <0x100>;
  65                         enable-method = "psci";
  66                         clock-frequency = <1701000000>;
  67                         cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
  68                         next-level-cache = <&l2_0>;
  69                         capacity-dmips-mhz = <530>;
  70                 };
  71
  72                 cpu2: cpu@200 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a55";
  75                         reg = <0x200>;
  76                         enable-method = "psci";
  77                         clock-frequency = <1701000000>;
  78                         cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
  79                         next-level-cache = <&l2_0>;
  80                         capacity-dmips-mhz = <530>;
  81                 };
  82
  83                 cpu3: cpu@300 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a55";
  86                         reg = <0x300>;
  87                         enable-method = "psci";
  88                         clock-frequency = <1701000000>;
  89                         cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
  90                         next-level-cache = <&l2_0>;
  91                         capacity-dmips-mhz = <530>;
  92                 };
  93
  94                 cpu4: cpu@400 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a76";
  97                         reg = <0x400>;
  98                         enable-method = "psci";
  99                         clock-frequency = <2171000000>;
 100                         cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
 101                         next-level-cache = <&l2_1>;
 102                         capacity-dmips-mhz = <1024>;
 103                 };
 104
 105                 cpu5: cpu@500 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a76";
 108                         reg = <0x500>;
 109                         enable-method = "psci";
 110                         clock-frequency = <2171000000>;
 111                         cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
 112                         next-level-cache = <&l2_1>;
 113                         capacity-dmips-mhz = <1024>;
 114                 };
 115
 116                 cpu6: cpu@600 {
 117                         device_type = "cpu";
 118                         compatible = "arm,cortex-a76";
 119                         reg = <0x600>;
 120                         enable-method = "psci";
 121                         clock-frequency = <2171000000>;
 122                         cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
 123                         next-level-cache = <&l2_1>;
 124                         capacity-dmips-mhz = <1024>;
 125                 };
 126
 127                 cpu7: cpu@700 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a76";
 130                         reg = <0x700>;
 131                         enable-method = "psci";
 132                         clock-frequency = <2171000000>;
 133                         cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
 134                         next-level-cache = <&l2_1>;
 135                         capacity-dmips-mhz = <1024>;
 136                 };
 137
 138                 cpu-map {
 139                         cluster0 {
 140                                 core0 {
 141                                         cpu = <&cpu0>;
 142                                 };
 143                                 core1 {
 144                                         cpu = <&cpu1>;
 145                                 };
 146                                 core2 {
 147                                         cpu = <&cpu2>;
 148                                 };
 149                                 core3 {
 150                                         cpu = <&cpu3>;
 151                                 };
 152                         };
 153
 154                         cluster1 {
 155                                 core0 {
 156                                         cpu = <&cpu4>;
 157                                 };
 158                                 core1 {
 159                                         cpu = <&cpu5>;
 160                                 };
 161                                 core2 {
 162                                         cpu = <&cpu6>;
 163                                 };
 164                                 core3 {
 165                                         cpu = <&cpu7>;
 166                                 };
 167                         };
 168                 };
 169
 170                 l2_0: l2-cache0 {
 171                         compatible = "cache";
 172                         cache-level = <2>;
 173                         next-level-cache = <&l3_0>;
 174                 };
 175
 176                 l2_1: l2-cache1 {
 177                         compatible = "cache";
 178                         cache-level = <2>;
 179                         next-level-cache = <&l3_0>;
 180                 };
 181
 182                 l3_0: l3-cache {
 183                         compatible = "cache";
 184                         cache-level = <3>;
 185                 };
 186
 187                 idle-states {
 188                         entry-method = "psci";
 189                         cpu_sleep_l: cpu-sleep-l {
 190                                 compatible = "arm,idle-state";
 191                                 arm,psci-suspend-param = <0x00010001>;
 192                                 local-timer-stop;
 193                                 entry-latency-us = <55>;
 194                                 exit-latency-us = <140>;
 195                                 min-residency-us = <780>;
 196                         };
 197                         cpu_sleep_b: cpu-sleep-b {
 198                                 compatible = "arm,idle-state";
 199                                 arm,psci-suspend-param = <0x00010001>;
 200                                 local-timer-stop;
 201                                 entry-latency-us = <35>;
 202                                 exit-latency-us = <145>;
 203                                 min-residency-us = <720>;
 204                         };
 205                         cluster_sleep_l: cluster-sleep-l {
 206                                 compatible = "arm,idle-state";
 207                                 arm,psci-suspend-param = <0x01010002>;
 208                                 local-timer-stop;
 209                                 entry-latency-us = <60>;
 210                                 exit-latency-us = <155>;
 211                                 min-residency-us = <860>;
 212                         };
 213                         cluster_sleep_b: cluster-sleep-b {
 214                                 compatible = "arm,idle-state";
 215                                 arm,psci-suspend-param = <0x01010002>;
 216                                 local-timer-stop;
 217                                 entry-latency-us = <40>;
 218                                 exit-latency-us = <155>;
 219                                 min-residency-us = <780>;
 220                         };
 221                 };
 222         };
 223
 224         pmu-a55 {
 225                 compatible = "arm,cortex-a55-pmu";
 226                 interrupt-parent = <&gic>;
 227                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
 228         };
 229
 230         pmu-a76 {
 231                 compatible = "arm,cortex-a76-pmu";
 232                 interrupt-parent = <&gic>;
 233                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
 234         };
 235
 236         psci {
 237                 compatible = "arm,psci-1.0";
 238                 method = "smc";
 239         };
 240
 241         timer: timer {
 242                 compatible = "arm,armv8-timer";
 243                 interrupt-parent = <&gic>;
 244                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
 245                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
 246                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
 247                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
 248                 clock-frequency = <13000000>;
 249         };
 250
 251         soc {
 252                 #address-cells = <2>;
 253                 #size-cells = <2>;
 254                 compatible = "simple-bus";
 255                 ranges;
 256
 257                 gic: interrupt-controller@c000000 {
 258                         compatible = "arm,gic-v3";
 259                         #interrupt-cells = <4>;
 260                         #redistributor-regions = <1>;
 261                         interrupt-parent = <&gic>;
 262                         interrupt-controller;
 263                         reg = <0 0x0c000000 0 0x40000>,
 264                               <0 0x0c040000 0 0x200000>;
 265                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 266
 267                         ppi-partitions {
 268                                 ppi_cluster0: interrupt-partition-0 {
 269                                         affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
 270                                 };
 271                                 ppi_cluster1: interrupt-partition-1 {
 272                                         affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
 273                                 };
 274                         };
 275                 };
 276
 277                 topckgen: syscon@10000000 {
 278                         compatible = "mediatek,mt8192-topckgen", "syscon";
 279                         reg = <0 0x10000000 0 0x1000>;
 280                         #clock-cells = <1>;
 281                 };
 282
 283                 infracfg: syscon@10001000 {
 284                         compatible = "mediatek,mt8192-infracfg", "syscon";
 285                         reg = <0 0x10001000 0 0x1000>;
 286                         #clock-cells = <1>;
 287                         #reset-cells = <1>;
 288                 };
 289
 290                 pericfg: syscon@10003000 {
 291                         compatible = "mediatek,mt8192-pericfg", "syscon";
 292                         reg = <0 0x10003000 0 0x1000>;
 293                         #clock-cells = <1>;
 294                 };
 295
 296                 pio: pinctrl@10005000 {
 297                         compatible = "mediatek,mt8192-pinctrl";
 298                         reg = <0 0x10005000 0 0x1000>,
 299                               <0 0x11c20000 0 0x1000>,
 300                               <0 0x11d10000 0 0x1000>,
 301                               <0 0x11d30000 0 0x1000>,
 302                               <0 0x11d40000 0 0x1000>,
 303                               <0 0x11e20000 0 0x1000>,
 304                               <0 0x11e70000 0 0x1000>,
 305                               <0 0x11ea0000 0 0x1000>,
 306                               <0 0x11f20000 0 0x1000>,
 307                               <0 0x11f30000 0 0x1000>,
 308                               <0 0x1000b000 0 0x1000>;
 309                         reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
 310                                     "iocfg_bl", "iocfg_br", "iocfg_lm",
 311                                     "iocfg_lb", "iocfg_rt", "iocfg_lt",
 312                                     "iocfg_tl", "eint";
 313                         gpio-controller;
 314                         #gpio-cells = <2>;
 315                         gpio-ranges = <&pio 0 0 220>;
 316                         interrupt-controller;
 317                         interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
 318                         #interrupt-cells = <2>;
 319                 };
 320
 321                 scpsys: syscon@10006000 {
 322                         compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd";
 323                         reg = <0 0x10006000 0 0x1000>;
 324
 325                         /* System Power Manager */
 326                         spm: power-controller {
 327                                 compatible = "mediatek,mt8192-power-controller";
 328                                 #address-cells = <1>;
 329                                 #size-cells = <0>;
 330                                 #power-domain-cells = <1>;
 331
 332                                 /* power domain of the SoC */
 333                                 power-domain@MT8192_POWER_DOMAIN_AUDIO {
 334                                         reg = <MT8192_POWER_DOMAIN_AUDIO>;
 335                                         clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
 336                                                  <&infracfg CLK_INFRA_AUDIO_26M_B>,
 337                                                  <&infracfg CLK_INFRA_AUDIO>;
 338                                         clock-names = "audio", "audio1", "audio2";
 339                                         mediatek,infracfg = <&infracfg>;
 340                                         #power-domain-cells = <0>;
 341                                 };
 342
 343                                 power-domain@MT8192_POWER_DOMAIN_CONN {
 344                                         reg = <MT8192_POWER_DOMAIN_CONN>;
 345                                         clocks = <&infracfg CLK_INFRA_PMIC_CONN>;
 346                                         clock-names = "conn";
 347                                         mediatek,infracfg = <&infracfg>;
 348                                         #power-domain-cells = <0>;
 349                                 };
 350
 351                                 power-domain@MT8192_POWER_DOMAIN_MFG0 {
 352                                         reg = <MT8192_POWER_DOMAIN_MFG0>;
 353                                         clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>;
 354                                         clock-names = "mfg";
 355                                         #address-cells = <1>;
 356                                         #size-cells = <0>;
 357                                         #power-domain-cells = <1>;
 358
 359                                         power-domain@MT8192_POWER_DOMAIN_MFG1 {
 360                                                 reg = <MT8192_POWER_DOMAIN_MFG1>;
 361                                                 mediatek,infracfg = <&infracfg>;
 362                                                 #address-cells = <1>;
 363                                                 #size-cells = <0>;
 364                                                 #power-domain-cells = <1>;
 365
 366                                                 power-domain@MT8192_POWER_DOMAIN_MFG2 {
 367                                                         reg = <MT8192_POWER_DOMAIN_MFG2>;
 368                                                         #power-domain-cells = <0>;
 369                                                 };
 370
 371                                                 power-domain@MT8192_POWER_DOMAIN_MFG3 {
 372                                                         reg = <MT8192_POWER_DOMAIN_MFG3>;
 373                                                         #power-domain-cells = <0>;
 374                                                 };
 375
 376                                                 power-domain@MT8192_POWER_DOMAIN_MFG4 {
 377                                                         reg = <MT8192_POWER_DOMAIN_MFG4>;
 378                                                         #power-domain-cells = <0>;
 379                                                 };
 380
 381                                                 power-domain@MT8192_POWER_DOMAIN_MFG5 {
 382                                                         reg = <MT8192_POWER_DOMAIN_MFG5>;
 383                                                         #power-domain-cells = <0>;
 384                                                 };
 385
 386                                                 power-domain@MT8192_POWER_DOMAIN_MFG6 {
 387                                                         reg = <MT8192_POWER_DOMAIN_MFG6>;
 388                                                         #power-domain-cells = <0>;
 389                                                 };
 390                                         };
 391                                 };
 392
 393                                 power-domain@MT8192_POWER_DOMAIN_DISP {
 394                                         reg = <MT8192_POWER_DOMAIN_DISP>;
 395                                         clocks = <&topckgen CLK_TOP_DISP_SEL>,
 396                                                  <&mmsys CLK_MM_SMI_INFRA>,
 397                                                  <&mmsys CLK_MM_SMI_COMMON>,
 398                                                  <&mmsys CLK_MM_SMI_GALS>,
 399                                                  <&mmsys CLK_MM_SMI_IOMMU>;
 400                                         clock-names = "disp", "disp-0", "disp-1", "disp-2",
 401                                                       "disp-3";
 402                                         mediatek,infracfg = <&infracfg>;
 403                                         #address-cells = <1>;
 404                                         #size-cells = <0>;
 405                                         #power-domain-cells = <1>;
 406
 407                                         power-domain@MT8192_POWER_DOMAIN_IPE {
 408                                                 reg = <MT8192_POWER_DOMAIN_IPE>;
 409                                                 clocks = <&topckgen CLK_TOP_IPE_SEL>,
 410                                                          <&ipesys CLK_IPE_LARB19>,
 411                                                          <&ipesys CLK_IPE_LARB20>,
 412                                                          <&ipesys CLK_IPE_SMI_SUBCOM>,
 413                                                          <&ipesys CLK_IPE_GALS>;
 414                                                 clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2",
 415                                                               "ipe-3";
 416                                                 mediatek,infracfg = <&infracfg>;
 417                                                 #power-domain-cells = <0>;
 418                                         };
 419
 420                                         power-domain@MT8192_POWER_DOMAIN_ISP {
 421                                                 reg = <MT8192_POWER_DOMAIN_ISP>;
 422                                                 clocks = <&topckgen CLK_TOP_IMG1_SEL>,
 423                                                          <&imgsys CLK_IMG_LARB9>,
 424                                                          <&imgsys CLK_IMG_GALS>;
 425                                                 clock-names = "isp", "isp-0", "isp-1";
 426                                                 mediatek,infracfg = <&infracfg>;
 427                                                 #power-domain-cells = <0>;
 428                                         };
 429
 430                                         power-domain@MT8192_POWER_DOMAIN_ISP2 {
 431                                                 reg = <MT8192_POWER_DOMAIN_ISP2>;
 432                                                 clocks = <&topckgen CLK_TOP_IMG2_SEL>,
 433                                                          <&imgsys2 CLK_IMG2_LARB11>,
 434                                                          <&imgsys2 CLK_IMG2_GALS>;
 435                                                 clock-names = "isp2", "isp2-0", "isp2-1";
 436                                                 mediatek,infracfg = <&infracfg>;
 437                                                 #power-domain-cells = <0>;
 438                                         };
 439
 440                                         power-domain@MT8192_POWER_DOMAIN_MDP {
 441                                                 reg = <MT8192_POWER_DOMAIN_MDP>;
 442                                                 clocks = <&topckgen CLK_TOP_MDP_SEL>,
 443                                                          <&mdpsys CLK_MDP_SMI0>;
 444                                                 clock-names = "mdp", "mdp-0";
 445                                                 mediatek,infracfg = <&infracfg>;
 446                                                 #power-domain-cells = <0>;
 447                                         };
 448
 449                                         power-domain@MT8192_POWER_DOMAIN_VENC {
 450                                                 reg = <MT8192_POWER_DOMAIN_VENC>;
 451                                                 clocks = <&topckgen CLK_TOP_VENC_SEL>,
 452                                                          <&vencsys CLK_VENC_SET1_VENC>;
 453                                                 clock-names = "venc", "venc-0";
 454                                                 mediatek,infracfg = <&infracfg>;
 455                                                 #power-domain-cells = <0>;
 456                                         };
 457
 458                                         power-domain@MT8192_POWER_DOMAIN_VDEC {
 459                                                 reg = <MT8192_POWER_DOMAIN_VDEC>;
 460                                                 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
 461                                                          <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
 462                                                          <&vdecsys_soc CLK_VDEC_SOC_LAT>,
 463                                                          <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
 464                                                 clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2";
 465                                                 mediatek,infracfg = <&infracfg>;
 466                                                 #address-cells = <1>;
 467                                                 #size-cells = <0>;
 468                                                 #power-domain-cells = <1>;
 469
 470                                                 power-domain@MT8192_POWER_DOMAIN_VDEC2 {
 471                                                         reg = <MT8192_POWER_DOMAIN_VDEC2>;
 472                                                         clocks = <&vdecsys CLK_VDEC_VDEC>,
 473                                                                  <&vdecsys CLK_VDEC_LAT>,
 474                                                                  <&vdecsys CLK_VDEC_LARB1>;
 475                                                         clock-names = "vdec2-0", "vdec2-1",
 476                                                                       "vdec2-2";
 477                                                         #power-domain-cells = <0>;
 478                                                 };
 479                                         };
 480
 481                                         power-domain@MT8192_POWER_DOMAIN_CAM {
 482                                                 reg = <MT8192_POWER_DOMAIN_CAM>;
 483                                                 clocks = <&topckgen CLK_TOP_CAM_SEL>,
 484                                                          <&camsys CLK_CAM_LARB13>,
 485                                                          <&camsys CLK_CAM_LARB14>,
 486                                                          <&camsys CLK_CAM_CCU_GALS>,
 487                                                          <&camsys CLK_CAM_CAM2MM_GALS>;
 488                                                 clock-names = "cam", "cam-0", "cam-1", "cam-2",
 489                                                               "cam-3";
 490                                                 mediatek,infracfg = <&infracfg>;
 491                                                 #address-cells = <1>;
 492                                                 #size-cells = <0>;
 493                                                 #power-domain-cells = <1>;
 494
 495                                                 power-domain@MT8192_POWER_DOMAIN_CAM_RAWA {
 496                                                         reg = <MT8192_POWER_DOMAIN_CAM_RAWA>;
 497                                                         clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>;
 498                                                         clock-names = "cam_rawa-0";
 499                                                         #power-domain-cells = <0>;
 500                                                 };
 501
 502                                                 power-domain@MT8192_POWER_DOMAIN_CAM_RAWB {
 503                                                         reg = <MT8192_POWER_DOMAIN_CAM_RAWB>;
 504                                                         clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>;
 505                                                         clock-names = "cam_rawb-0";
 506                                                         #power-domain-cells = <0>;
 507                                                 };
 508
 509                                                 power-domain@MT8192_POWER_DOMAIN_CAM_RAWC {
 510                                                         reg = <MT8192_POWER_DOMAIN_CAM_RAWC>;
 511                                                         clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>;
 512                                                         clock-names = "cam_rawc-0";
 513                                                         #power-domain-cells = <0>;
 514                                                 };
 515                                         };
 516                                 };
 517                         };
 518                 };
 519
 520                 watchdog: watchdog@10007000 {
 521                         compatible = "mediatek,mt8192-wdt";
 522                         reg = <0 0x10007000 0 0x100>;
 523                         #reset-cells = <1>;
 524                 };
 525
 526                 apmixedsys: syscon@1000c000 {
 527                         compatible = "mediatek,mt8192-apmixedsys", "syscon";
 528                         reg = <0 0x1000c000 0 0x1000>;
 529                         #clock-cells = <1>;
 530                 };
 531
 532                 systimer: timer@10017000 {
 533                         compatible = "mediatek,mt8192-timer",
 534                                      "mediatek,mt6765-timer";
 535                         reg = <0 0x10017000 0 0x1000>;
 536                         interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
 537                         clocks = <&topckgen CLK_TOP_CSW_F26M_D2>;
 538                         clock-names = "clk13m";
 539                 };
 540
 541                 pwrap: pwrap@10026000 {
 542                         compatible = "mediatek,mt6873-pwrap";
 543                         reg = <0 0x10026000 0 0x1000>;
 544                         reg-names = "pwrap";
 545                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
 546                         clocks = <&infracfg CLK_INFRA_PMIC_AP>,
 547                                  <&infracfg CLK_INFRA_PMIC_TMR>;
 548                         clock-names = "spi", "wrap";
 549                         assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
 550                         assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
 551                 };
 552
 553                 spmi: spmi@10027000 {
 554                         compatible = "mediatek,mt6873-spmi";
 555                         reg = <0 0x10027000 0 0x000e00>,
 556                               <0 0x10029000 0 0x000100>;
 557                         reg-names = "pmif", "spmimst";
 558                         clocks = <&infracfg CLK_INFRA_PMIC_AP>,
 559                                  <&infracfg CLK_INFRA_PMIC_TMR>,
 560                                  <&topckgen CLK_TOP_SPMI_MST_SEL>;
 561                         clock-names = "pmif_sys_ck",
 562                                       "pmif_tmr_ck",
 563                                       "spmimst_clk_mux";
 564                         assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
 565                         assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
 566                 };
 567
 568                 gce: mailbox@10228000 {
 569                         compatible = "mediatek,mt8192-gce";
 570                         reg = <0 0x10228000 0 0x4000>;
 571                         interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
 572                         #mbox-cells = <2>;
 573                         clocks = <&infracfg CLK_INFRA_GCE>;
 574                         clock-names = "gce";
 575                 };
 576
 577                 scp_adsp: clock-controller@10720000 {
 578                         compatible = "mediatek,mt8192-scp_adsp";
 579                         reg = <0 0x10720000 0 0x1000>;
 580                         #clock-cells = <1>;
 581                 };
 582
 583                 uart0: serial@11002000 {
 584                         compatible = "mediatek,mt8192-uart",
 585                                      "mediatek,mt6577-uart";
 586                         reg = <0 0x11002000 0 0x1000>;
 587                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
 588                         clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
 589                         clock-names = "baud", "bus";
 590                         status = "disabled";
 591                 };
 592
 593                 uart1: serial@11003000 {
 594                         compatible = "mediatek,mt8192-uart",
 595                                      "mediatek,mt6577-uart";
 596                         reg = <0 0x11003000 0 0x1000>;
 597                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 598                         clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
 599                         clock-names = "baud", "bus";
 600                         status = "disabled";
 601                 };
 602
 603                 imp_iic_wrap_c: clock-controller@11007000 {
 604                         compatible = "mediatek,mt8192-imp_iic_wrap_c";
 605                         reg = <0 0x11007000 0 0x1000>;
 606                         #clock-cells = <1>;
 607                 };
 608
 609                 spi0: spi@1100a000 {
 610                         compatible = "mediatek,mt8192-spi",
 611                                      "mediatek,mt6765-spi";
 612                         #address-cells = <1>;
 613                         #size-cells = <0>;
 614                         reg = <0 0x1100a000 0 0x1000>;
 615                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>;
 616                         clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
 617                                  <&topckgen CLK_TOP_SPI_SEL>,
 618                                  <&infracfg CLK_INFRA_SPI0>;
 619                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 620                         status = "disabled";
 621                 };
 622
 623                 pwm0: pwm@1100e000 {
 624                         compatible = "mediatek,mt8183-disp-pwm";
 625                         reg = <0 0x1100e000 0 0x1000>;
 626                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;
 627                         #pwm-cells = <2>;
 628                         clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
 629                                  <&infracfg CLK_INFRA_DISP_PWM>;
 630                         clock-names = "main", "mm";
 631                         status = "disabled";
 632                 };
 633
 634                 spi1: spi@11010000 {
 635                         compatible = "mediatek,mt8192-spi",
 636                                      "mediatek,mt6765-spi";
 637                         #address-cells = <1>;
 638                         #size-cells = <0>;
 639                         reg = <0 0x11010000 0 0x1000>;
 640                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>;
 641                         clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
 642                                  <&topckgen CLK_TOP_SPI_SEL>,
 643                                  <&infracfg CLK_INFRA_SPI1>;
 644                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 645                         status = "disabled";
 646                 };
 647
 648                 spi2: spi@11012000 {
 649                         compatible = "mediatek,mt8192-spi",
 650                                      "mediatek,mt6765-spi";
 651                         #address-cells = <1>;
 652                         #size-cells = <0>;
 653                         reg = <0 0x11012000 0 0x1000>;
 654                         interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
 655                         clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
 656                                  <&topckgen CLK_TOP_SPI_SEL>,
 657                                  <&infracfg CLK_INFRA_SPI2>;
 658                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 659                         status = "disabled";
 660                 };
 661
 662                 spi3: spi@11013000 {
 663                         compatible = "mediatek,mt8192-spi",
 664                                      "mediatek,mt6765-spi";
 665                         #address-cells = <1>;
 666                         #size-cells = <0>;
 667                         reg = <0 0x11013000 0 0x1000>;
 668                         interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>;
 669                         clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
 670                                  <&topckgen CLK_TOP_SPI_SEL>,
 671                                  <&infracfg CLK_INFRA_SPI3>;
 672                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 673                         status = "disabled";
 674                 };
 675
 676                 spi4: spi@11018000 {
 677                         compatible = "mediatek,mt8192-spi",
 678                                      "mediatek,mt6765-spi";
 679                         #address-cells = <1>;
 680                         #size-cells = <0>;
 681                         reg = <0 0x11018000 0 0x1000>;
 682                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>;
 683                         clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
 684                                  <&topckgen CLK_TOP_SPI_SEL>,
 685                                  <&infracfg CLK_INFRA_SPI4>;
 686                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 687                         status = "disabled";
 688                 };
 689
 690                 spi5: spi@11019000 {
 691                         compatible = "mediatek,mt8192-spi",
 692                                      "mediatek,mt6765-spi";
 693                         #address-cells = <1>;
 694                         #size-cells = <0>;
 695                         reg = <0 0x11019000 0 0x1000>;
 696                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>;
 697                         clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
 698                                  <&topckgen CLK_TOP_SPI_SEL>,
 699                                  <&infracfg CLK_INFRA_SPI5>;
 700                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 701                         status = "disabled";
 702                 };
 703
 704                 spi6: spi@1101d000 {
 705                         compatible = "mediatek,mt8192-spi",
 706                                      "mediatek,mt6765-spi";
 707                         #address-cells = <1>;
 708                         #size-cells = <0>;
 709                         reg = <0 0x1101d000 0 0x1000>;
 710                         interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>;
 711                         clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
 712                                  <&topckgen CLK_TOP_SPI_SEL>,
 713                                  <&infracfg CLK_INFRA_SPI6>;
 714                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 715                         status = "disabled";
 716                 };
 717
 718                 spi7: spi@1101e000 {
 719                         compatible = "mediatek,mt8192-spi",
 720                                      "mediatek,mt6765-spi";
 721                         #address-cells = <1>;
 722                         #size-cells = <0>;
 723                         reg = <0 0x1101e000 0 0x1000>;
 724                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>;
 725                         clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
 726                                  <&topckgen CLK_TOP_SPI_SEL>,
 727                                  <&infracfg CLK_INFRA_SPI7>;
 728                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 729                         status = "disabled";
 730                 };
 731
 732                 scp: scp@10500000 {
 733                         compatible = "mediatek,mt8192-scp";
 734                         reg = <0 0x10500000 0 0x100000>,
 735                               <0 0x10720000 0 0xe0000>,
 736                               <0 0x10700000 0 0x8000>;
 737                         reg-names = "sram", "cfg", "l1tcm";
 738                         interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
 739                         clocks = <&infracfg CLK_INFRA_SCPSYS>;
 740                         clock-names = "main";
 741                         status = "disabled";
 742                 };
 743
 744                 xhci: usb@11200000 {
 745                         compatible = "mediatek,mt8192-xhci",
 746                                      "mediatek,mtk-xhci";
 747                         reg = <0 0x11200000 0 0x1000>,
 748                               <0 0x11203e00 0 0x0100>;
 749                         reg-names = "mac", "ippc";
 750                         interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 751                         interrupt-names = "host";
 752                         phys = <&u2port0 PHY_TYPE_USB2>,
 753                                <&u3port0 PHY_TYPE_USB3>;
 754                         assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
 755                                           <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
 756                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
 757                                                  <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
 758                         clocks = <&infracfg CLK_INFRA_SSUSB>,
 759                                  <&apmixedsys CLK_APMIXED_USBPLL>,
 760                                  <&clk26m>,
 761                                  <&clk26m>,
 762                                  <&infracfg CLK_INFRA_SSUSB_XHCI>;
 763                         clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
 764                                       "xhci_ck";
 765                         wakeup-source;
 766                         mediatek,syscon-wakeup = <&pericfg 0x420 102>;
 767                         status = "disabled";
 768                 };
 769
 770                 audsys: syscon@11210000 {
 771                         compatible = "mediatek,mt8192-audsys", "syscon";
 772                         reg = <0 0x11210000 0 0x2000>;
 773                         #clock-cells = <1>;
 774
 775                         afe: mt8192-afe-pcm {
 776                                 compatible = "mediatek,mt8192-audio";
 777                                 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
 778                                 resets = <&watchdog 17>;
 779                                 reset-names = "audiosys";
 780                                 mediatek,apmixedsys = <&apmixedsys>;
 781                                 mediatek,infracfg = <&infracfg>;
 782                                 mediatek,topckgen = <&topckgen>;
 783                                 power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
 784                                 clocks = <&audsys CLK_AUD_AFE>,
 785                                          <&audsys CLK_AUD_DAC>,
 786                                          <&audsys CLK_AUD_DAC_PREDIS>,
 787                                          <&audsys CLK_AUD_ADC>,
 788                                          <&audsys CLK_AUD_ADDA6_ADC>,
 789                                          <&audsys CLK_AUD_22M>,
 790                                          <&audsys CLK_AUD_24M>,
 791                                          <&audsys CLK_AUD_APLL_TUNER>,
 792                                          <&audsys CLK_AUD_APLL2_TUNER>,
 793                                          <&audsys CLK_AUD_TDM>,
 794                                          <&audsys CLK_AUD_TML>,
 795                                          <&audsys CLK_AUD_NLE>,
 796                                          <&audsys CLK_AUD_DAC_HIRES>,
 797                                          <&audsys CLK_AUD_ADC_HIRES>,
 798                                          <&audsys CLK_AUD_ADC_HIRES_TML>,
 799                                          <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
 800                                          <&audsys CLK_AUD_3RD_DAC>,
 801                                          <&audsys CLK_AUD_3RD_DAC_PREDIS>,
 802                                          <&audsys CLK_AUD_3RD_DAC_TML>,
 803                                          <&audsys CLK_AUD_3RD_DAC_HIRES>,
 804                                          <&infracfg CLK_INFRA_AUDIO>,
 805                                          <&infracfg CLK_INFRA_AUDIO_26M_B>,
 806                                          <&topckgen CLK_TOP_AUDIO_SEL>,
 807                                          <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
 808                                          <&topckgen CLK_TOP_MAINPLL_D4_D4>,
 809                                          <&topckgen CLK_TOP_AUD_1_SEL>,
 810                                          <&topckgen CLK_TOP_APLL1>,
 811                                          <&topckgen CLK_TOP_AUD_2_SEL>,
 812                                          <&topckgen CLK_TOP_APLL2>,
 813                                          <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
 814                                          <&topckgen CLK_TOP_APLL1_D4>,
 815                                          <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
 816                                          <&topckgen CLK_TOP_APLL2_D4>,
 817                                          <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
 818                                          <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
 819                                          <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
 820                                          <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
 821                                          <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
 822                                          <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
 823                                          <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
 824                                          <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
 825                                          <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
 826                                          <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
 827                                          <&topckgen CLK_TOP_APLL12_DIV0>,
 828                                          <&topckgen CLK_TOP_APLL12_DIV1>,
 829                                          <&topckgen CLK_TOP_APLL12_DIV2>,
 830                                          <&topckgen CLK_TOP_APLL12_DIV3>,
 831                                          <&topckgen CLK_TOP_APLL12_DIV4>,
 832                                          <&topckgen CLK_TOP_APLL12_DIVB>,
 833                                          <&topckgen CLK_TOP_APLL12_DIV5>,
 834                                          <&topckgen CLK_TOP_APLL12_DIV6>,
 835                                          <&topckgen CLK_TOP_APLL12_DIV7>,
 836                                          <&topckgen CLK_TOP_APLL12_DIV8>,
 837                                          <&topckgen CLK_TOP_APLL12_DIV9>,
 838                                          <&topckgen CLK_TOP_AUDIO_H_SEL>,
 839                                          <&clk26m>;
 840                                 clock-names = "aud_afe_clk",
 841                                               "aud_dac_clk",
 842                                               "aud_dac_predis_clk",
 843                                               "aud_adc_clk",
 844                                               "aud_adda6_adc_clk",
 845                                               "aud_apll22m_clk",
 846                                               "aud_apll24m_clk",
 847                                               "aud_apll1_tuner_clk",
 848                                               "aud_apll2_tuner_clk",
 849                                               "aud_tdm_clk",
 850                                               "aud_tml_clk",
 851                                               "aud_nle",
 852                                               "aud_dac_hires_clk",
 853                                               "aud_adc_hires_clk",
 854                                               "aud_adc_hires_tml",
 855                                               "aud_adda6_adc_hires_clk",
 856                                               "aud_3rd_dac_clk",
 857                                               "aud_3rd_dac_predis_clk",
 858                                               "aud_3rd_dac_tml",
 859                                               "aud_3rd_dac_hires_clk",
 860                                               "aud_infra_clk",
 861                                               "aud_infra_26m_clk",
 862                                               "top_mux_audio",
 863                                               "top_mux_audio_int",
 864                                               "top_mainpll_d4_d4",
 865                                               "top_mux_aud_1",
 866                                               "top_apll1_ck",
 867                                               "top_mux_aud_2",
 868                                               "top_apll2_ck",
 869                                               "top_mux_aud_eng1",
 870                                               "top_apll1_d4",
 871                                               "top_mux_aud_eng2",
 872                                               "top_apll2_d4",
 873                                               "top_i2s0_m_sel",
 874                                               "top_i2s1_m_sel",
 875                                               "top_i2s2_m_sel",
 876                                               "top_i2s3_m_sel",
 877                                               "top_i2s4_m_sel",
 878                                               "top_i2s5_m_sel",
 879                                               "top_i2s6_m_sel",
 880                                               "top_i2s7_m_sel",
 881                                               "top_i2s8_m_sel",
 882                                               "top_i2s9_m_sel",
 883                                               "top_apll12_div0",
 884                                               "top_apll12_div1",
 885                                               "top_apll12_div2",
 886                                               "top_apll12_div3",
 887                                               "top_apll12_div4",
 888                                               "top_apll12_divb",
 889                                               "top_apll12_div5",
 890                                               "top_apll12_div6",
 891                                               "top_apll12_div7",
 892                                               "top_apll12_div8",
 893                                               "top_apll12_div9",
 894                                               "top_mux_audio_h",
 895                                               "top_clk26m_clk";
 896                         };
 897                 };
 898
 899                 pcie: pcie@11230000 {
 900                         compatible = "mediatek,mt8192-pcie";
 901                         device_type = "pci";
 902                         reg = <0 0x11230000 0 0x2000>;
 903                         reg-names = "pcie-mac";
 904                         #address-cells = <3>;
 905                         #size-cells = <2>;
 906                         clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>,
 907                                  <&infracfg CLK_INFRA_PCIE_TL_26M>,
 908                                  <&infracfg CLK_INFRA_PCIE_TL_96M>,
 909                                  <&infracfg CLK_INFRA_PCIE_TL_32K>,
 910                                  <&infracfg CLK_INFRA_PCIE_PERI_26M>,
 911                                  <&infracfg CLK_INFRA_PCIE_TOP_H_133M>;
 912                         clock-names = "pl_250m", "tl_26m", "tl_96m",
 913                                       "tl_32k", "peri_26m", "top_133m";
 914                         assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
 915                         assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
 916                         interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
 917                         bus-range = <0x00 0xff>;
 918                         ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
 919                                  <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
 920                         #interrupt-cells = <1>;
 921                         interrupt-map-mask = <0 0 0 7>;
 922                         interrupt-map = <0 0 0 1 &pcie_intc0 0>,
 923                                         <0 0 0 2 &pcie_intc0 1>,
 924                                         <0 0 0 3 &pcie_intc0 2>,
 925                                         <0 0 0 4 &pcie_intc0 3>;
 926
 927                         pcie_intc0: interrupt-controller {
 928                                 interrupt-controller;
 929                                 #address-cells = <0>;
 930                                 #interrupt-cells = <1>;
 931                         };
 932                 };
 933
 934                 nor_flash: spi@11234000 {
 935                         compatible = "mediatek,mt8192-nor";
 936                         reg = <0 0x11234000 0 0xe0>;
 937                         interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>;
 938                         clocks = <&topckgen CLK_TOP_SFLASH_SEL>,
 939                                  <&infracfg CLK_INFRA_FLASHIF_SFLASH>,
 940                                  <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>;
 941                         clock-names = "spi", "sf", "axi";
 942                         assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>;
 943                         assigned-clock-parents = <&clk26m>;
 944                         #address-cells = <1>;
 945                         #size-cells = <0>;
 946                         status = "disabled";
 947                 };
 948
 949                 efuse: efuse@11c10000 {
 950                         compatible = "mediatek,mt8192-efuse", "mediatek,efuse";
 951                         reg = <0 0x11c10000 0 0x1000>;
 952                         #address-cells = <1>;
 953                         #size-cells = <1>;
 954
 955                         lvts_e_data1: data1@1c0 {
 956                                 reg = <0x1c0 0x58>;
 957                         };
 958
 959                         svs_calibration: calib@580 {
 960                                 reg = <0x580 0x68>;
 961                         };
 962                 };
 963
 964                 i2c3: i2c@11cb0000 {
 965                         compatible = "mediatek,mt8192-i2c";
 966                         reg = <0 0x11cb0000 0 0x1000>,
 967                               <0 0x10217300 0 0x80>;
 968                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
 969                         clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>,
 970                                  <&infracfg CLK_INFRA_AP_DMA>;
 971                         clock-names = "main", "dma";
 972                         clock-div = <1>;
 973                         #address-cells = <1>;
 974                         #size-cells = <0>;
 975                         status = "disabled";
 976                 };
 977
 978                 imp_iic_wrap_e: clock-controller@11cb1000 {
 979                         compatible = "mediatek,mt8192-imp_iic_wrap_e";
 980                         reg = <0 0x11cb1000 0 0x1000>;
 981                         #clock-cells = <1>;
 982                 };
 983
 984                 i2c7: i2c@11d00000 {
 985                         compatible = "mediatek,mt8192-i2c";
 986                         reg = <0 0x11d00000 0 0x1000>,
 987                               <0 0x10217600 0 0x180>;
 988                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
 989                         clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
 990                                  <&infracfg CLK_INFRA_AP_DMA>;
 991                         clock-names = "main", "dma";
 992                         clock-div = <1>;
 993                         #address-cells = <1>;
 994                         #size-cells = <0>;
 995                         status = "disabled";
 996                 };
 997
 998                 i2c8: i2c@11d01000 {
 999                         compatible = "mediatek,mt8192-i2c";
1000                         reg = <0 0x11d01000 0 0x1000>,
1001                               <0 0x10217780 0 0x180>;
1002                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1003                         clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>,
1004                                  <&infracfg CLK_INFRA_AP_DMA>;
1005                         clock-names = "main", "dma";
1006                         clock-div = <1>;
1007                         #address-cells = <1>;
1008                         #size-cells = <0>;
1009                         status = "disabled";
1010                 };
1011
1012                 i2c9: i2c@11d02000 {
1013                         compatible = "mediatek,mt8192-i2c";
1014                         reg = <0 0x11d02000 0 0x1000>,
1015                               <0 0x10217900 0 0x180>;
1016                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
1017                         clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>,
1018                                  <&infracfg CLK_INFRA_AP_DMA>;
1019                         clock-names = "main", "dma";
1020                         clock-div = <1>;
1021                         #address-cells = <1>;
1022                         #size-cells = <0>;
1023                         status = "disabled";
1024                 };
1025
1026                 imp_iic_wrap_s: clock-controller@11d03000 {
1027                         compatible = "mediatek,mt8192-imp_iic_wrap_s";
1028                         reg = <0 0x11d03000 0 0x1000>;
1029                         #clock-cells = <1>;
1030                 };
1031
1032                 i2c1: i2c@11d20000 {
1033                         compatible = "mediatek,mt8192-i2c";
1034                         reg = <0 0x11d20000 0 0x1000>,
1035                               <0 0x10217100 0 0x80>;
1036                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1037                         clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>,
1038                                  <&infracfg CLK_INFRA_AP_DMA>;
1039                         clock-names = "main", "dma";
1040                         clock-div = <1>;
1041                         #address-cells = <1>;
1042                         #size-cells = <0>;
1043                         status = "disabled";
1044                 };
1045
1046                 i2c2: i2c@11d21000 {
1047                         compatible = "mediatek,mt8192-i2c";
1048                         reg = <0 0x11d21000 0 0x1000>,
1049                               <0 0x10217180 0 0x180>;
1050                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
1051                         clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>,
1052                                  <&infracfg CLK_INFRA_AP_DMA>;
1053                         clock-names = "main", "dma";
1054                         clock-div = <1>;
1055                         #address-cells = <1>;
1056                         #size-cells = <0>;
1057                         status = "disabled";
1058                 };
1059
1060                 i2c4: i2c@11d22000 {
1061                         compatible = "mediatek,mt8192-i2c";
1062                         reg = <0 0x11d22000 0 0x1000>,
1063                               <0 0x10217380 0 0x180>;
1064                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1065                         clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>,
1066                                  <&infracfg CLK_INFRA_AP_DMA>;
1067                         clock-names = "main", "dma";
1068                         clock-div = <1>;
1069                         #address-cells = <1>;
1070                         #size-cells = <0>;
1071                         status = "disabled";
1072                 };
1073
1074                 imp_iic_wrap_ws: clock-controller@11d23000 {
1075                         compatible = "mediatek,mt8192-imp_iic_wrap_ws";
1076                         reg = <0 0x11d23000 0 0x1000>;
1077                         #clock-cells = <1>;
1078                 };
1079
1080                 i2c5: i2c@11e00000 {
1081                         compatible = "mediatek,mt8192-i2c";
1082                         reg = <0 0x11e00000 0 0x1000>,
1083                               <0 0x10217500 0 0x80>;
1084                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1085                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>,
1086                                  <&infracfg CLK_INFRA_AP_DMA>;
1087                         clock-names = "main", "dma";
1088                         clock-div = <1>;
1089                         #address-cells = <1>;
1090                         #size-cells = <0>;
1091                         status = "disabled";
1092                 };
1093
1094                 imp_iic_wrap_w: clock-controller@11e01000 {
1095                         compatible = "mediatek,mt8192-imp_iic_wrap_w";
1096                         reg = <0 0x11e01000 0 0x1000>;
1097                         #clock-cells = <1>;
1098                 };
1099
1100                 u3phy0: t-phy@11e40000 {
1101                         compatible = "mediatek,mt8192-tphy",
1102                                      "mediatek,generic-tphy-v2";
1103                         #address-cells = <1>;
1104                         #size-cells = <1>;
1105                         ranges = <0x0 0x0 0x11e40000 0x1000>;
1106
1107                         u2port0: usb-phy@0 {
1108                                 reg = <0x0 0x700>;
1109                                 clocks = <&clk26m>;
1110                                 clock-names = "ref";
1111                                 #phy-cells = <1>;
1112                         };
1113
1114                         u3port0: usb-phy@700 {
1115                                 reg = <0x700 0x900>;
1116                                 clocks = <&clk26m>;
1117                                 clock-names = "ref";
1118                                 #phy-cells = <1>;
1119                         };
1120                 };
1121
1122                 mipi_tx0: dsi-phy@11e50000 {
1123                         compatible = "mediatek,mt8183-mipi-tx";
1124                         reg = <0 0x11e50000 0 0x1000>;
1125                         clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
1126                         #clock-cells = <0>;
1127                         #phy-cells = <0>;
1128                         clock-output-names = "mipi_tx0_pll";
1129                         status = "disabled";
1130                 };
1131
1132                 i2c0: i2c@11f00000 {
1133                         compatible = "mediatek,mt8192-i2c";
1134                         reg = <0 0x11f00000 0 0x1000>,
1135                               <0 0x10217080 0 0x80>;
1136                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
1137                         clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>,
1138                                  <&infracfg CLK_INFRA_AP_DMA>;
1139                         clock-names = "main", "dma";
1140                         clock-div = <1>;
1141                         #address-cells = <1>;
1142                         #size-cells = <0>;
1143                         status = "disabled";
1144                 };
1145
1146                 i2c6: i2c@11f01000 {
1147                         compatible = "mediatek,mt8192-i2c";
1148                         reg = <0 0x11f01000 0 0x1000>,
1149                               <0 0x10217580 0 0x80>;
1150                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1151                         clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>,
1152                                  <&infracfg CLK_INFRA_AP_DMA>;
1153                         clock-names = "main", "dma";
1154                         clock-div = <1>;
1155                         #address-cells = <1>;
1156                         #size-cells = <0>;
1157                         status = "disabled";
1158                 };
1159
1160                 imp_iic_wrap_n: clock-controller@11f02000 {
1161                         compatible = "mediatek,mt8192-imp_iic_wrap_n";
1162                         reg = <0 0x11f02000 0 0x1000>;
1163                         #clock-cells = <1>;
1164                 };
1165
1166                 msdc_top: clock-controller@11f10000 {
1167                         compatible = "mediatek,mt8192-msdc_top";
1168                         reg = <0 0x11f10000 0 0x1000>;
1169                         #clock-cells = <1>;
1170                 };
1171
1172                 mmc0: mmc@11f60000 {
1173                         compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
1174                         reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>;
1175                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
1176                         clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
1177                                  <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
1178                                  <&msdc_top CLK_MSDC_TOP_SRC_0P>,
1179                                  <&msdc_top CLK_MSDC_TOP_P_CFG>,
1180                                  <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
1181                                  <&msdc_top CLK_MSDC_TOP_AXI>,
1182                                  <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
1183                         clock-names = "source", "hclk", "source_cg", "sys_cg",
1184                                       "pclk_cg", "axi_cg", "ahb_cg";
1185                         status = "disabled";
1186                 };
1187
1188                 mmc1: mmc@11f70000 {
1189                         compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
1190                         reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>;
1191                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
1192                         clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
1193                                  <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
1194                                  <&msdc_top CLK_MSDC_TOP_SRC_1P>,
1195                                  <&msdc_top CLK_MSDC_TOP_P_CFG>,
1196                                  <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
1197                                  <&msdc_top CLK_MSDC_TOP_AXI>,
1198                                  <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
1199                         clock-names = "source", "hclk", "source_cg", "sys_cg",
1200                                       "pclk_cg", "axi_cg", "ahb_cg";
1201                         status = "disabled";
1202                 };
1203
1204                 mfgcfg: clock-controller@13fbf000 {
1205                         compatible = "mediatek,mt8192-mfgcfg";
1206                         reg = <0 0x13fbf000 0 0x1000>;
1207                         #clock-cells = <1>;
1208                 };
1209
1210                 mmsys: syscon@14000000 {
1211                         compatible = "mediatek,mt8192-mmsys", "syscon";
1212                         reg = <0 0x14000000 0 0x1000>;
1213                         #clock-cells = <1>;
1214                         #reset-cells = <1>;
1215                         mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1216                                  <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1217                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1218                 };
1219
1220                 mutex: mutex@14001000 {
1221                         compatible = "mediatek,mt8192-disp-mutex";
1222                         reg = <0 0x14001000 0 0x1000>;
1223                         interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
1224                         clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
1225                         mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
1226                                               <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
1227                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1228                 };
1229
1230                 smi_common: smi@14002000 {
1231                         compatible = "mediatek,mt8192-smi-common";
1232                         reg = <0 0x14002000 0 0x1000>;
1233                         clocks = <&mmsys CLK_MM_SMI_COMMON>,
1234                                  <&mmsys CLK_MM_SMI_INFRA>,
1235                                  <&mmsys CLK_MM_SMI_GALS>,
1236                                  <&mmsys CLK_MM_SMI_GALS>;
1237                         clock-names = "apb", "smi", "gals0", "gals1";
1238                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1239                 };
1240
1241                 larb0: larb@14003000 {
1242                         compatible = "mediatek,mt8192-smi-larb";
1243                         reg = <0 0x14003000 0 0x1000>;
1244                         mediatek,larb-id = <0>;
1245                         mediatek,smi = <&smi_common>;
1246                         clocks = <&clk26m>, <&clk26m>;
1247                         clock-names = "apb", "smi";
1248                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1249                 };
1250
1251                 larb1: larb@14004000 {
1252                         compatible = "mediatek,mt8192-smi-larb";
1253                         reg = <0 0x14004000 0 0x1000>;
1254                         mediatek,larb-id = <1>;
1255                         mediatek,smi = <&smi_common>;
1256                         clocks = <&clk26m>, <&clk26m>;
1257                         clock-names = "apb", "smi";
1258                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1259                 };
1260
1261                 ovl0: ovl@14005000 {
1262                         compatible = "mediatek,mt8192-disp-ovl";
1263                         reg = <0 0x14005000 0 0x1000>;
1264                         interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
1265                         clocks = <&mmsys CLK_MM_DISP_OVL0>;
1266                         iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
1267                                  <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
1268                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1269                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1270                 };
1271
1272                 ovl_2l0: ovl@14006000 {
1273                         compatible = "mediatek,mt8192-disp-ovl-2l";
1274                         reg = <0 0x14006000 0 0x1000>;
1275                         interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
1276                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1277                         clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
1278                         iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
1279                                  <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
1280                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1281                 };
1282
1283                 rdma0: rdma@14007000 {
1284                         compatible = "mediatek,mt8192-disp-rdma",
1285                                      "mediatek,mt8183-disp-rdma";
1286                         reg = <0 0x14007000 0 0x1000>;
1287                         interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
1288                         clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1289                         iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
1290                         mediatek,rdma-fifo-size = <5120>;
1291                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1292                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
1293                 };
1294
1295                 color0: color@14009000 {
1296                         compatible = "mediatek,mt8192-disp-color",
1297                                      "mediatek,mt8173-disp-color";
1298                         reg = <0 0x14009000 0 0x1000>;
1299                         interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
1300                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1301                         clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1302                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
1303                 };
1304
1305                 ccorr0: ccorr@1400a000 {
1306                         compatible = "mediatek,mt8192-disp-ccorr";
1307                         reg = <0 0x1400a000 0 0x1000>;
1308                         interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
1309                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1310                         clocks = <&mmsys CLK_MM_DISP_CCORR0>;
1311                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
1312                 };
1313
1314                 aal0: aal@1400b000 {
1315                         compatible = "mediatek,mt8192-disp-aal",
1316                                      "mediatek,mt8183-disp-aal";
1317                         reg = <0 0x1400b000 0 0x1000>;
1318                         interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
1319                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1320                         clocks = <&mmsys CLK_MM_DISP_AAL0>;
1321                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1322                 };
1323
1324                 gamma0: gamma@1400c000 {
1325                         compatible = "mediatek,mt8192-disp-gamma",
1326                                      "mediatek,mt8183-disp-gamma";
1327                         reg = <0 0x1400c000 0 0x1000>;
1328                         interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
1329                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1330                         clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
1331                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1332                 };
1333
1334                 postmask0: postmask@1400d000 {
1335                         compatible = "mediatek,mt8192-disp-postmask";
1336                         reg = <0 0x1400d000 0 0x1000>;
1337                         interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
1338                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1339                         clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
1340                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1341                 };
1342
1343                 dither0: dither@1400e000 {
1344                         compatible = "mediatek,mt8192-disp-dither",
1345                                      "mediatek,mt8183-disp-dither";
1346                         reg = <0 0x1400e000 0 0x1000>;
1347                         interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
1348                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1349                         clocks = <&mmsys CLK_MM_DISP_DITHER0>;
1350                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1351                 };
1352
1353                 dsi0: dsi@14010000 {
1354                         compatible = "mediatek,mt8183-dsi";
1355                         reg = <0 0x14010000 0 0x1000>;
1356                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
1357                         clocks = <&mmsys CLK_MM_DSI0>,
1358                                  <&mmsys CLK_MM_DSI_DSI0>,
1359                                  <&mipi_tx0>;
1360                         clock-names = "engine", "digital", "hs";
1361                         phys = <&mipi_tx0>;
1362                         phy-names = "dphy";
1363                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1364                         resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>;
1365                         status = "disabled";
1366
1367                         port {
1368                                 dsi_out: endpoint { };
1369                         };
1370                 };
1371
1372                 ovl_2l2: ovl@14014000 {
1373                         compatible = "mediatek,mt8192-disp-ovl-2l";
1374                         reg = <0 0x14014000 0 0x1000>;
1375                         interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
1376                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1377                         clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
1378                         iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
1379                                  <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
1380                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1381                 };
1382
1383                 rdma4: rdma@14015000 {
1384                         compatible = "mediatek,mt8192-disp-rdma",
1385                                      "mediatek,mt8183-disp-rdma";
1386                         reg = <0 0x14015000 0 0x1000>;
1387                         interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
1388                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1389                         clocks = <&mmsys CLK_MM_DISP_RDMA4>;
1390                         iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
1391                         mediatek,rdma-fifo-size = <2048>;
1392                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1393                 };
1394
1395                 dpi0: dpi@14016000 {
1396                         compatible = "mediatek,mt8192-dpi";
1397                         reg = <0 0x14016000 0 0x1000>;
1398                         interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
1399                         clocks = <&mmsys CLK_MM_DPI_DPI0>,
1400                                  <&mmsys CLK_MM_DISP_DPI0>,
1401                                  <&apmixedsys CLK_APMIXED_TVDPLL>;
1402                         clock-names = "pixel", "engine", "pll";
1403                         status = "disabled";
1404                 };
1405
1406                 iommu0: m4u@1401d000 {
1407                         compatible = "mediatek,mt8192-m4u";
1408                         reg = <0 0x1401d000 0 0x1000>;
1409                         mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
1410                                          <&larb4>, <&larb5>, <&larb7>,
1411                                          <&larb9>, <&larb11>, <&larb13>,
1412                                          <&larb14>, <&larb16>, <&larb17>,
1413                                          <&larb18>, <&larb19>, <&larb20>;
1414                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
1415                         clocks = <&mmsys CLK_MM_SMI_IOMMU>;
1416                         clock-names = "bclk";
1417                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1418                         #iommu-cells = <1>;
1419                 };
1420
1421                 imgsys: clock-controller@15020000 {
1422                         compatible = "mediatek,mt8192-imgsys";
1423                         reg = <0 0x15020000 0 0x1000>;
1424                         #clock-cells = <1>;
1425                 };
1426
1427                 larb9: larb@1502e000 {
1428                         compatible = "mediatek,mt8192-smi-larb";
1429                         reg = <0 0x1502e000 0 0x1000>;
1430                         mediatek,larb-id = <9>;
1431                         mediatek,smi = <&smi_common>;
1432                         clocks = <&imgsys CLK_IMG_LARB9>,
1433                                  <&imgsys CLK_IMG_LARB9>;
1434                         clock-names = "apb", "smi";
1435                         power-domains = <&spm MT8192_POWER_DOMAIN_ISP>;
1436                 };
1437
1438                 imgsys2: clock-controller@15820000 {
1439                         compatible = "mediatek,mt8192-imgsys2";
1440                         reg = <0 0x15820000 0 0x1000>;
1441                         #clock-cells = <1>;
1442                 };
1443
1444                 larb11: larb@1582e000 {
1445                         compatible = "mediatek,mt8192-smi-larb";
1446                         reg = <0 0x1582e000 0 0x1000>;
1447                         mediatek,larb-id = <11>;
1448                         mediatek,smi = <&smi_common>;
1449                         clocks = <&imgsys2 CLK_IMG2_LARB11>,
1450                                  <&imgsys2 CLK_IMG2_LARB11>;
1451                         clock-names = "apb", "smi";
1452                         power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
1453                 };
1454
1455                 larb5: larb@1600d000 {
1456                         compatible = "mediatek,mt8192-smi-larb";
1457                         reg = <0 0x1600d000 0 0x1000>;
1458                         mediatek,larb-id = <5>;
1459                         mediatek,smi = <&smi_common>;
1460                         clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
1461                                  <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
1462                         clock-names = "apb", "smi";
1463                         power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
1464                 };
1465
1466                 vdecsys_soc: clock-controller@1600f000 {
1467                         compatible = "mediatek,mt8192-vdecsys_soc";
1468                         reg = <0 0x1600f000 0 0x1000>;
1469                         #clock-cells = <1>;
1470                 };
1471
1472                 larb4: larb@1602e000 {
1473                         compatible = "mediatek,mt8192-smi-larb";
1474                         reg = <0 0x1602e000 0 0x1000>;
1475                         mediatek,larb-id = <4>;
1476                         mediatek,smi = <&smi_common>;
1477                         clocks = <&vdecsys CLK_VDEC_SOC_LARB1>,
1478                                  <&vdecsys CLK_VDEC_SOC_LARB1>;
1479                         clock-names = "apb", "smi";
1480                         power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
1481                 };
1482
1483                 vdecsys: clock-controller@1602f000 {
1484                         compatible = "mediatek,mt8192-vdecsys";
1485                         reg = <0 0x1602f000 0 0x1000>;
1486                         #clock-cells = <1>;
1487                 };
1488
1489                 vencsys: clock-controller@17000000 {
1490                         compatible = "mediatek,mt8192-vencsys";
1491                         reg = <0 0x17000000 0 0x1000>;
1492                         #clock-cells = <1>;
1493                 };
1494
1495                 larb7: larb@17010000 {
1496                         compatible = "mediatek,mt8192-smi-larb";
1497                         reg = <0 0x17010000 0 0x1000>;
1498                         mediatek,larb-id = <7>;
1499                         mediatek,smi = <&smi_common>;
1500                         clocks = <&vencsys CLK_VENC_SET0_LARB>,
1501                                  <&vencsys CLK_VENC_SET1_VENC>;
1502                         clock-names = "apb", "smi";
1503                         power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
1504                 };
1505
1506                 vcodec_enc: vcodec@17020000 {
1507                         compatible = "mediatek,mt8192-vcodec-enc";
1508                         reg = <0 0x17020000 0 0x2000>;
1509                         iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
1510                                  <&iommu0 M4U_PORT_L7_VENC_REC>,
1511                                  <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
1512                                  <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
1513                                  <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
1514                                  <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
1515                                  <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
1516                                  <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
1517                                  <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
1518                                  <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
1519                                  <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
1520                         interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
1521                         mediatek,scp = <&scp>;
1522                         power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
1523                         clocks = <&vencsys CLK_VENC_SET1_VENC>;
1524                         clock-names = "venc-set1";
1525                         assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1526                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
1527                 };
1528
1529                 camsys: clock-controller@1a000000 {
1530                         compatible = "mediatek,mt8192-camsys";
1531                         reg = <0 0x1a000000 0 0x1000>;
1532                         #clock-cells = <1>;
1533                 };
1534
1535                 larb13: larb@1a001000 {
1536                         compatible = "mediatek,mt8192-smi-larb";
1537                         reg = <0 0x1a001000 0 0x1000>;
1538                         mediatek,larb-id = <13>;
1539                         mediatek,smi = <&smi_common>;
1540                         clocks = <&camsys CLK_CAM_CAM>,
1541                                  <&camsys CLK_CAM_LARB13>;
1542                         clock-names = "apb", "smi";
1543                         power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
1544                 };
1545
1546                 larb14: larb@1a002000 {
1547                         compatible = "mediatek,mt8192-smi-larb";
1548                         reg = <0 0x1a002000 0 0x1000>;
1549                         mediatek,larb-id = <14>;
1550                         mediatek,smi = <&smi_common>;
1551                         clocks = <&camsys CLK_CAM_CAM>,
1552                                  <&camsys CLK_CAM_LARB14>;
1553                         clock-names = "apb", "smi";
1554                         power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
1555                 };
1556
1557                 larb16: larb@1a00f000 {
1558                         compatible = "mediatek,mt8192-smi-larb";
1559                         reg = <0 0x1a00f000 0 0x1000>;
1560                         mediatek,larb-id = <16>;
1561                         mediatek,smi = <&smi_common>;
1562                         clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
1563                                  <&camsys_rawa CLK_CAM_RAWA_LARBX>;
1564                         clock-names = "apb", "smi";
1565                         power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>;
1566                 };
1567
1568                 larb17: larb@1a010000 {
1569                         compatible = "mediatek,mt8192-smi-larb";
1570                         reg = <0 0x1a010000 0 0x1000>;
1571                         mediatek,larb-id = <17>;
1572                         mediatek,smi = <&smi_common>;
1573                         clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>,
1574                                  <&camsys_rawb CLK_CAM_RAWB_LARBX>;
1575                         clock-names = "apb", "smi";
1576                         power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>;
1577                 };
1578
1579                 larb18: larb@1a011000 {
1580                         compatible = "mediatek,mt8192-smi-larb";
1581                         reg = <0 0x1a011000 0 0x1000>;
1582                         mediatek,larb-id = <18>;
1583                         mediatek,smi = <&smi_common>;
1584                         clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>,
1585                                  <&camsys_rawc CLK_CAM_RAWC_CAM>;
1586                         clock-names = "apb", "smi";
1587                         power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>;
1588                 };
1589
1590                 camsys_rawa: clock-controller@1a04f000 {
1591                         compatible = "mediatek,mt8192-camsys_rawa";
1592                         reg = <0 0x1a04f000 0 0x1000>;
1593                         #clock-cells = <1>;
1594                 };
1595
1596                 camsys_rawb: clock-controller@1a06f000 {
1597                         compatible = "mediatek,mt8192-camsys_rawb";
1598                         reg = <0 0x1a06f000 0 0x1000>;
1599                         #clock-cells = <1>;
1600                 };
1601
1602                 camsys_rawc: clock-controller@1a08f000 {
1603                         compatible = "mediatek,mt8192-camsys_rawc";
1604                         reg = <0 0x1a08f000 0 0x1000>;
1605                         #clock-cells = <1>;
1606                 };
1607
1608                 ipesys: clock-controller@1b000000 {
1609                         compatible = "mediatek,mt8192-ipesys";
1610                         reg = <0 0x1b000000 0 0x1000>;
1611                         #clock-cells = <1>;
1612                 };
1613
1614                 larb20: larb@1b00f000 {
1615                         compatible = "mediatek,mt8192-smi-larb";
1616                         reg = <0 0x1b00f000 0 0x1000>;
1617                         mediatek,larb-id = <20>;
1618                         mediatek,smi = <&smi_common>;
1619                         clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
1620                                  <&ipesys CLK_IPE_LARB20>;
1621                         clock-names = "apb", "smi";
1622                         power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
1623                 };
1624
1625                 larb19: larb@1b10f000 {
1626                         compatible = "mediatek,mt8192-smi-larb";
1627                         reg = <0 0x1b10f000 0 0x1000>;
1628                         mediatek,larb-id = <19>;
1629                         mediatek,smi = <&smi_common>;
1630                         clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
1631                                  <&ipesys CLK_IPE_LARB19>;
1632                         clock-names = "apb", "smi";
1633                         power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
1634                 };
1635
1636                 mdpsys: clock-controller@1f000000 {
1637                         compatible = "mediatek,mt8192-mdpsys";
1638                         reg = <0 0x1f000000 0 0x1000>;
1639                         #clock-cells = <1>;
1640                 };
1641
1642                 larb2: larb@1f002000 {
1643                         compatible = "mediatek,mt8192-smi-larb";
1644                         reg = <0 0x1f002000 0 0x1000>;
1645                         mediatek,larb-id = <2>;
1646                         mediatek,smi = <&smi_common>;
1647                         clocks = <&mdpsys CLK_MDP_SMI0>,
1648                                  <&mdpsys CLK_MDP_SMI0>;
1649                         clock-names = "apb", "smi";
1650                         power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
1651                 };
1652         };
1653 };