src/arm64/mediatek/mt8195.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (c) 2021 MediaTek Inc.
   4  * Author: Seiya Wang <seiya.wang@mediatek.com>
   5  */
   6
   7 /dts-v1/;
   8 #include <dt-bindings/clock/mt8195-clk.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/phy/phy.h>
  12 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
  13
  14 / {
  15         compatible = "mediatek,mt8195";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu0: cpu@0 {
  25                         device_type = "cpu";
  26                         compatible = "arm,cortex-a55";
  27                         reg = <0x000>;
  28                         enable-method = "psci";
  29                         clock-frequency = <1701000000>;
  30                         capacity-dmips-mhz = <578>;
  31                         cpu-idle-states = <&cpu_off_l &cluster_off_l>;
  32                         next-level-cache = <&l2_0>;
  33                         #cooling-cells = <2>;
  34                 };
  35
  36                 cpu1: cpu@100 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a55";
  39                         reg = <0x100>;
  40                         enable-method = "psci";
  41                         clock-frequency = <1701000000>;
  42                         capacity-dmips-mhz = <578>;
  43                         cpu-idle-states = <&cpu_off_l &cluster_off_l>;
  44                         next-level-cache = <&l2_0>;
  45                         #cooling-cells = <2>;
  46                 };
  47
  48                 cpu2: cpu@200 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a55";
  51                         reg = <0x200>;
  52                         enable-method = "psci";
  53                         clock-frequency = <1701000000>;
  54                         capacity-dmips-mhz = <578>;
  55                         cpu-idle-states = <&cpu_off_l &cluster_off_l>;
  56                         next-level-cache = <&l2_0>;
  57                         #cooling-cells = <2>;
  58                 };
  59
  60                 cpu3: cpu@300 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a55";
  63                         reg = <0x300>;
  64                         enable-method = "psci";
  65                         clock-frequency = <1701000000>;
  66                         capacity-dmips-mhz = <578>;
  67                         cpu-idle-states = <&cpu_off_l &cluster_off_l>;
  68                         next-level-cache = <&l2_0>;
  69                         #cooling-cells = <2>;
  70                 };
  71
  72                 cpu4: cpu@400 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a78";
  75                         reg = <0x400>;
  76                         enable-method = "psci";
  77                         clock-frequency = <2171000000>;
  78                         capacity-dmips-mhz = <1024>;
  79                         cpu-idle-states = <&cpu_off_b &cluster_off_b>;
  80                         next-level-cache = <&l2_1>;
  81                         #cooling-cells = <2>;
  82                 };
  83
  84                 cpu5: cpu@500 {
  85                         device_type = "cpu";
  86                         compatible = "arm,cortex-a78";
  87                         reg = <0x500>;
  88                         enable-method = "psci";
  89                         clock-frequency = <2171000000>;
  90                         capacity-dmips-mhz = <1024>;
  91                         cpu-idle-states = <&cpu_off_b &cluster_off_b>;
  92                         next-level-cache = <&l2_1>;
  93                         #cooling-cells = <2>;
  94                 };
  95
  96                 cpu6: cpu@600 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a78";
  99                         reg = <0x600>;
 100                         enable-method = "psci";
 101                         clock-frequency = <2171000000>;
 102                         capacity-dmips-mhz = <1024>;
 103                         cpu-idle-states = <&cpu_off_b &cluster_off_b>;
 104                         next-level-cache = <&l2_1>;
 105                         #cooling-cells = <2>;
 106                 };
 107
 108                 cpu7: cpu@700 {
 109                         device_type = "cpu";
 110                         compatible = "arm,cortex-a78";
 111                         reg = <0x700>;
 112                         enable-method = "psci";
 113                         clock-frequency = <2171000000>;
 114                         capacity-dmips-mhz = <1024>;
 115                         cpu-idle-states = <&cpu_off_b &cluster_off_b>;
 116                         next-level-cache = <&l2_1>;
 117                         #cooling-cells = <2>;
 118                 };
 119
 120                 cpu-map {
 121                         cluster0 {
 122                                 core0 {
 123                                         cpu = <&cpu0>;
 124                                 };
 125
 126                                 core1 {
 127                                         cpu = <&cpu1>;
 128                                 };
 129
 130                                 core2 {
 131                                         cpu = <&cpu2>;
 132                                 };
 133
 134                                 core3 {
 135                                         cpu = <&cpu3>;
 136                                 };
 137                         };
 138
 139                         cluster1 {
 140                                 core0 {
 141                                         cpu = <&cpu4>;
 142                                 };
 143
 144                                 core1 {
 145                                         cpu = <&cpu5>;
 146                                 };
 147
 148                                 core2 {
 149                                         cpu = <&cpu6>;
 150                                 };
 151
 152                                 core3 {
 153                                         cpu = <&cpu7>;
 154                                 };
 155                         };
 156                 };
 157
 158                 idle-states {
 159                         entry-method = "psci";
 160
 161                         cpu_off_l: cpu-off-l {
 162                                 compatible = "arm,idle-state";
 163                                 arm,psci-suspend-param = <0x00010001>;
 164                                 local-timer-stop;
 165                                 entry-latency-us = <50>;
 166                                 exit-latency-us = <95>;
 167                                 min-residency-us = <580>;
 168                         };
 169
 170                         cpu_off_b: cpu-off-b {
 171                                 compatible = "arm,idle-state";
 172                                 arm,psci-suspend-param = <0x00010001>;
 173                                 local-timer-stop;
 174                                 entry-latency-us = <45>;
 175                                 exit-latency-us = <140>;
 176                                 min-residency-us = <740>;
 177                         };
 178
 179                         cluster_off_l: cluster-off-l {
 180                                 compatible = "arm,idle-state";
 181                                 arm,psci-suspend-param = <0x01010002>;
 182                                 local-timer-stop;
 183                                 entry-latency-us = <55>;
 184                                 exit-latency-us = <155>;
 185                                 min-residency-us = <840>;
 186                         };
 187
 188                         cluster_off_b: cluster-off-b {
 189                                 compatible = "arm,idle-state";
 190                                 arm,psci-suspend-param = <0x01010002>;
 191                                 local-timer-stop;
 192                                 entry-latency-us = <50>;
 193                                 exit-latency-us = <200>;
 194                                 min-residency-us = <1000>;
 195                         };
 196                 };
 197
 198                 l2_0: l2-cache0 {
 199                         compatible = "cache";
 200                         next-level-cache = <&l3_0>;
 201                 };
 202
 203                 l2_1: l2-cache1 {
 204                         compatible = "cache";
 205                         next-level-cache = <&l3_0>;
 206                 };
 207
 208                 l3_0: l3-cache {
 209                         compatible = "cache";
 210                 };
 211         };
 212
 213         dsu-pmu {
 214                 compatible = "arm,dsu-pmu";
 215                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
 216                 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
 217                        <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
 218         };
 219
 220         clk26m: oscillator-26m {
 221                 compatible = "fixed-clock";
 222                 #clock-cells = <0>;
 223                 clock-frequency = <26000000>;
 224                 clock-output-names = "clk26m";
 225         };
 226
 227         clk32k: oscillator-32k {
 228                 compatible = "fixed-clock";
 229                 #clock-cells = <0>;
 230                 clock-frequency = <32768>;
 231                 clock-output-names = "clk32k";
 232         };
 233
 234         pmu-a55 {
 235                 compatible = "arm,cortex-a55-pmu";
 236                 interrupt-parent = <&gic>;
 237                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
 238         };
 239
 240         pmu-a78 {
 241                 compatible = "arm,cortex-a78-pmu";
 242                 interrupt-parent = <&gic>;
 243                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
 244         };
 245
 246         psci {
 247                 compatible = "arm,psci-1.0";
 248                 method = "smc";
 249         };
 250
 251         timer: timer {
 252                 compatible = "arm,armv8-timer";
 253                 interrupt-parent = <&gic>;
 254                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
 255                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
 256                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
 257                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
 258         };
 259
 260         soc {
 261                 #address-cells = <2>;
 262                 #size-cells = <2>;
 263                 compatible = "simple-bus";
 264                 ranges;
 265
 266                 gic: interrupt-controller@c000000 {
 267                         compatible = "arm,gic-v3";
 268                         #interrupt-cells = <4>;
 269                         #redistributor-regions = <1>;
 270                         interrupt-parent = <&gic>;
 271                         interrupt-controller;
 272                         reg = <0 0x0c000000 0 0x40000>,
 273                               <0 0x0c040000 0 0x200000>;
 274                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 275
 276                         ppi-partitions {
 277                                 ppi_cluster0: interrupt-partition-0 {
 278                                         affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
 279                                 };
 280
 281                                 ppi_cluster1: interrupt-partition-1 {
 282                                         affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
 283                                 };
 284                         };
 285                 };
 286
 287                 topckgen: syscon@10000000 {
 288                         compatible = "mediatek,mt8195-topckgen", "syscon";
 289                         reg = <0 0x10000000 0 0x1000>;
 290                         #clock-cells = <1>;
 291                 };
 292
 293                 infracfg_ao: syscon@10001000 {
 294                         compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
 295                         reg = <0 0x10001000 0 0x1000>;
 296                         #clock-cells = <1>;
 297                         #reset-cells = <1>;
 298                 };
 299
 300                 pericfg: syscon@10003000 {
 301                         compatible = "mediatek,mt8195-pericfg", "syscon";
 302                         reg = <0 0x10003000 0 0x1000>;
 303                         #clock-cells = <1>;
 304                 };
 305
 306                 pio: pinctrl@10005000 {
 307                         compatible = "mediatek,mt8195-pinctrl";
 308                         reg = <0 0x10005000 0 0x1000>,
 309                               <0 0x11d10000 0 0x1000>,
 310                               <0 0x11d30000 0 0x1000>,
 311                               <0 0x11d40000 0 0x1000>,
 312                               <0 0x11e20000 0 0x1000>,
 313                               <0 0x11eb0000 0 0x1000>,
 314                               <0 0x11f40000 0 0x1000>,
 315                               <0 0x1000b000 0 0x1000>;
 316                         reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
 317                                     "iocfg_br", "iocfg_lm", "iocfg_rb",
 318                                     "iocfg_tl", "eint";
 319                         gpio-controller;
 320                         #gpio-cells = <2>;
 321                         gpio-ranges = <&pio 0 0 144>;
 322                         interrupt-controller;
 323                         interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
 324                         #interrupt-cells = <2>;
 325                 };
 326
 327                 watchdog: watchdog@10007000 {
 328                         compatible = "mediatek,mt8195-wdt",
 329                                      "mediatek,mt6589-wdt";
 330                         reg = <0 0x10007000 0 0x100>;
 331                 };
 332
 333                 apmixedsys: syscon@1000c000 {
 334                         compatible = "mediatek,mt8195-apmixedsys", "syscon";
 335                         reg = <0 0x1000c000 0 0x1000>;
 336                         #clock-cells = <1>;
 337                 };
 338
 339                 systimer: timer@10017000 {
 340                         compatible = "mediatek,mt8195-timer",
 341                                      "mediatek,mt6765-timer";
 342                         reg = <0 0x10017000 0 0x1000>;
 343                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
 344                         clocks = <&topckgen CLK_TOP_CLK26M_D2>;
 345                 };
 346
 347                 pwrap: pwrap@10024000 {
 348                         compatible = "mediatek,mt8195-pwrap", "syscon";
 349                         reg = <0 0x10024000 0 0x1000>;
 350                         reg-names = "pwrap";
 351                         interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
 352                         clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
 353                                  <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
 354                         clock-names = "spi", "wrap";
 355                         assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
 356                         assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
 357                 };
 358
 359                 scp_adsp: clock-controller@10720000 {
 360                         compatible = "mediatek,mt8195-scp_adsp";
 361                         reg = <0 0x10720000 0 0x1000>;
 362                         #clock-cells = <1>;
 363                 };
 364
 365                 uart0: serial@11001100 {
 366                         compatible = "mediatek,mt8195-uart",
 367                                      "mediatek,mt6577-uart";
 368                         reg = <0 0x11001100 0 0x100>;
 369                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
 370                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
 371                         clock-names = "baud", "bus";
 372                         status = "disabled";
 373                 };
 374
 375                 uart1: serial@11001200 {
 376                         compatible = "mediatek,mt8195-uart",
 377                                      "mediatek,mt6577-uart";
 378                         reg = <0 0x11001200 0 0x100>;
 379                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
 380                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
 381                         clock-names = "baud", "bus";
 382                         status = "disabled";
 383                 };
 384
 385                 uart2: serial@11001300 {
 386                         compatible = "mediatek,mt8195-uart",
 387                                      "mediatek,mt6577-uart";
 388                         reg = <0 0x11001300 0 0x100>;
 389                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
 390                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
 391                         clock-names = "baud", "bus";
 392                         status = "disabled";
 393                 };
 394
 395                 uart3: serial@11001400 {
 396                         compatible = "mediatek,mt8195-uart",
 397                                      "mediatek,mt6577-uart";
 398                         reg = <0 0x11001400 0 0x100>;
 399                         interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
 400                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
 401                         clock-names = "baud", "bus";
 402                         status = "disabled";
 403                 };
 404
 405                 uart4: serial@11001500 {
 406                         compatible = "mediatek,mt8195-uart",
 407                                      "mediatek,mt6577-uart";
 408                         reg = <0 0x11001500 0 0x100>;
 409                         interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>;
 410                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>;
 411                         clock-names = "baud", "bus";
 412                         status = "disabled";
 413                 };
 414
 415                 uart5: serial@11001600 {
 416                         compatible = "mediatek,mt8195-uart",
 417                                      "mediatek,mt6577-uart";
 418                         reg = <0 0x11001600 0 0x100>;
 419                         interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>;
 420                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>;
 421                         clock-names = "baud", "bus";
 422                         status = "disabled";
 423                 };
 424
 425                 auxadc: auxadc@11002000 {
 426                         compatible = "mediatek,mt8195-auxadc",
 427                                      "mediatek,mt8173-auxadc";
 428                         reg = <0 0x11002000 0 0x1000>;
 429                         clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
 430                         clock-names = "main";
 431                         #io-channel-cells = <1>;
 432                         status = "disabled";
 433                 };
 434
 435                 pericfg_ao: syscon@11003000 {
 436                         compatible = "mediatek,mt8195-pericfg_ao", "syscon";
 437                         reg = <0 0x11003000 0 0x1000>;
 438                         #clock-cells = <1>;
 439                 };
 440
 441                 spi0: spi@1100a000 {
 442                         compatible = "mediatek,mt8195-spi",
 443                                      "mediatek,mt6765-spi";
 444                         #address-cells = <1>;
 445                         #size-cells = <0>;
 446                         reg = <0 0x1100a000 0 0x1000>;
 447                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
 448                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
 449                                  <&topckgen CLK_TOP_SPI>,
 450                                  <&infracfg_ao CLK_INFRA_AO_SPI0>;
 451                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 452                         status = "disabled";
 453                 };
 454
 455                 spi1: spi@11010000 {
 456                         compatible = "mediatek,mt8195-spi",
 457                                      "mediatek,mt6765-spi";
 458                         #address-cells = <1>;
 459                         #size-cells = <0>;
 460                         reg = <0 0x11010000 0 0x1000>;
 461                         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
 462                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
 463                                  <&topckgen CLK_TOP_SPI>,
 464                                  <&infracfg_ao CLK_INFRA_AO_SPI1>;
 465                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 466                         status = "disabled";
 467                 };
 468
 469                 spi2: spi@11012000 {
 470                         compatible = "mediatek,mt8195-spi",
 471                                      "mediatek,mt6765-spi";
 472                         #address-cells = <1>;
 473                         #size-cells = <0>;
 474                         reg = <0 0x11012000 0 0x1000>;
 475                         interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
 476                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
 477                                  <&topckgen CLK_TOP_SPI>,
 478                                  <&infracfg_ao CLK_INFRA_AO_SPI2>;
 479                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 480                         status = "disabled";
 481                 };
 482
 483                 spi3: spi@11013000 {
 484                         compatible = "mediatek,mt8195-spi",
 485                                      "mediatek,mt6765-spi";
 486                         #address-cells = <1>;
 487                         #size-cells = <0>;
 488                         reg = <0 0x11013000 0 0x1000>;
 489                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
 490                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
 491                                  <&topckgen CLK_TOP_SPI>,
 492                                  <&infracfg_ao CLK_INFRA_AO_SPI3>;
 493                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 494                         status = "disabled";
 495                 };
 496
 497                 spi4: spi@11018000 {
 498                         compatible = "mediatek,mt8195-spi",
 499                                      "mediatek,mt6765-spi";
 500                         #address-cells = <1>;
 501                         #size-cells = <0>;
 502                         reg = <0 0x11018000 0 0x1000>;
 503                         interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
 504                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
 505                                  <&topckgen CLK_TOP_SPI>,
 506                                  <&infracfg_ao CLK_INFRA_AO_SPI4>;
 507                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 508                         status = "disabled";
 509                 };
 510
 511                 spi5: spi@11019000 {
 512                         compatible = "mediatek,mt8195-spi",
 513                                      "mediatek,mt6765-spi";
 514                         #address-cells = <1>;
 515                         #size-cells = <0>;
 516                         reg = <0 0x11019000 0 0x1000>;
 517                         interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
 518                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
 519                                  <&topckgen CLK_TOP_SPI>,
 520                                  <&infracfg_ao CLK_INFRA_AO_SPI5>;
 521                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 522                         status = "disabled";
 523                 };
 524
 525                 spis0: spi@1101d000 {
 526                         compatible = "mediatek,mt8195-spi-slave";
 527                         reg = <0 0x1101d000 0 0x1000>;
 528                         interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
 529                         clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>;
 530                         clock-names = "spi";
 531                         assigned-clocks = <&topckgen CLK_TOP_SPIS>;
 532                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
 533                         status = "disabled";
 534                 };
 535
 536                 spis1: spi@1101e000 {
 537                         compatible = "mediatek,mt8195-spi-slave";
 538                         reg = <0 0x1101e000 0 0x1000>;
 539                         interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
 540                         clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
 541                         clock-names = "spi";
 542                         assigned-clocks = <&topckgen CLK_TOP_SPIS>;
 543                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
 544                         status = "disabled";
 545                 };
 546
 547                 xhci0: usb@11200000 {
 548                         compatible = "mediatek,mt8195-xhci",
 549                                      "mediatek,mtk-xhci";
 550                         reg = <0 0x11200000 0 0x1000>,
 551                               <0 0x11203e00 0 0x0100>;
 552                         reg-names = "mac", "ippc";
 553                         interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
 554                         phys = <&u2port0 PHY_TYPE_USB2>,
 555                                <&u3port0 PHY_TYPE_USB3>;
 556                         assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
 557                                           <&topckgen CLK_TOP_SSUSB_XHCI>;
 558                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
 559                                                  <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
 560                         clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
 561                                  <&topckgen CLK_TOP_SSUSB_REF>,
 562                                  <&apmixedsys CLK_APMIXED_USB1PLL>,
 563                                  <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
 564                         clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck";
 565                         mediatek,syscon-wakeup = <&pericfg 0x400 103>;
 566                         wakeup-source;
 567                         status = "disabled";
 568                 };
 569
 570                 mmc0: mmc@11230000 {
 571                         compatible = "mediatek,mt8195-mmc",
 572                                      "mediatek,mt8183-mmc";
 573                         reg = <0 0x11230000 0 0x10000>,
 574                               <0 0x11f50000 0 0x1000>;
 575                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
 576                         clocks = <&topckgen CLK_TOP_MSDC50_0>,
 577                                  <&infracfg_ao CLK_INFRA_AO_MSDC0>,
 578                                  <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
 579                         clock-names = "source", "hclk", "source_cg";
 580                         status = "disabled";
 581                 };
 582
 583                 mmc1: mmc@11240000 {
 584                         compatible = "mediatek,mt8195-mmc",
 585                                      "mediatek,mt8183-mmc";
 586                         reg = <0 0x11240000 0 0x1000>,
 587                               <0 0x11c70000 0 0x1000>;
 588                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
 589                         clocks = <&topckgen CLK_TOP_MSDC30_1>,
 590                                  <&infracfg_ao CLK_INFRA_AO_MSDC1>,
 591                                  <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
 592                         clock-names = "source", "hclk", "source_cg";
 593                         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
 594                         assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
 595                         status = "disabled";
 596                 };
 597
 598                 mmc2: mmc@11250000 {
 599                         compatible = "mediatek,mt8195-mmc",
 600                                      "mediatek,mt8183-mmc";
 601                         reg = <0 0x11250000 0 0x1000>,
 602                               <0 0x11e60000 0 0x1000>;
 603                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
 604                         clocks = <&topckgen CLK_TOP_MSDC30_2>,
 605                                  <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>,
 606                                  <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>;
 607                         clock-names = "source", "hclk", "source_cg";
 608                         assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
 609                         assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
 610                         status = "disabled";
 611                 };
 612
 613                 xhci1: usb@11290000 {
 614                         compatible = "mediatek,mt8195-xhci",
 615                                      "mediatek,mtk-xhci";
 616                         reg = <0 0x11290000 0 0x1000>,
 617                               <0 0x11293e00 0 0x0100>;
 618                         reg-names = "mac", "ippc";
 619                         interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
 620                         phys = <&u2port1 PHY_TYPE_USB2>;
 621                         assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
 622                                           <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
 623                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
 624                                                  <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
 625                         clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
 626                                  <&topckgen CLK_TOP_SSUSB_P1_REF>,
 627                                  <&apmixedsys CLK_APMIXED_USB1PLL>,
 628                                  <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>;
 629                         clock-names = "sys_ck", "ref_ck", "mcu_ck","xhci_ck";
 630                         mediatek,syscon-wakeup = <&pericfg 0x400 104>;
 631                         wakeup-source;
 632                         status = "disabled";
 633                 };
 634
 635                 xhci2: usb@112a0000 {
 636                         compatible = "mediatek,mt8195-xhci",
 637                                      "mediatek,mtk-xhci";
 638                         reg = <0 0x112a0000 0 0x1000>,
 639                               <0 0x112a3e00 0 0x0100>;
 640                         reg-names = "mac", "ippc";
 641                         interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
 642                         phys = <&u2port2 PHY_TYPE_USB2>;
 643                         assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
 644                                           <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
 645                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
 646                                                  <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
 647                         clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
 648                                  <&topckgen CLK_TOP_SSUSB_P2_REF>,
 649                                  <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
 650                         clock-names = "sys_ck", "ref_ck", "xhci_ck";
 651                         mediatek,syscon-wakeup = <&pericfg 0x400 105>;
 652                         wakeup-source;
 653                         status = "disabled";
 654                 };
 655
 656                 xhci3: usb@112b0000 {
 657                         compatible = "mediatek,mt8195-xhci",
 658                                      "mediatek,mtk-xhci";
 659                         reg = <0 0x112b0000 0 0x1000>,
 660                               <0 0x112b3e00 0 0x0100>;
 661                         reg-names = "mac", "ippc";
 662                         interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
 663                         phys = <&u2port3 PHY_TYPE_USB2>;
 664                         assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
 665                                           <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
 666                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
 667                                                  <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
 668                         clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
 669                                  <&topckgen CLK_TOP_SSUSB_P3_REF>,
 670                                  <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
 671                         clock-names = "sys_ck", "ref_ck", "xhci_ck";
 672                         mediatek,syscon-wakeup = <&pericfg 0x400 106>;
 673                         wakeup-source;
 674                         status = "disabled";
 675                 };
 676
 677                 nor_flash: spi@1132c000 {
 678                         compatible = "mediatek,mt8195-nor",
 679                                      "mediatek,mt8173-nor";
 680                         reg = <0 0x1132c000 0 0x1000>;
 681                         interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
 682                         clocks = <&topckgen CLK_TOP_SPINOR>,
 683                                  <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>,
 684                                  <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
 685                         clock-names = "spi", "sf", "axi";
 686                         #address-cells = <1>;
 687                         #size-cells = <0>;
 688                         status = "disabled";
 689                 };
 690
 691                 efuse: efuse@11c10000 {
 692                         compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
 693                         reg = <0 0x11c10000 0 0x1000>;
 694                         #address-cells = <1>;
 695                         #size-cells = <1>;
 696                         u3_tx_imp_p0: usb3-tx-imp@184,1 {
 697                                 reg = <0x184 0x1>;
 698                                 bits = <0 5>;
 699                         };
 700                         u3_rx_imp_p0: usb3-rx-imp@184,2 {
 701                                 reg = <0x184 0x2>;
 702                                 bits = <5 5>;
 703                         };
 704                         u3_intr_p0: usb3-intr@185 {
 705                                 reg = <0x185 0x1>;
 706                                 bits = <2 6>;
 707                         };
 708                         comb_tx_imp_p1: usb3-tx-imp@186,1 {
 709                                 reg = <0x186 0x1>;
 710                                 bits = <0 5>;
 711                         };
 712                         comb_rx_imp_p1: usb3-rx-imp@186,2 {
 713                                 reg = <0x186 0x2>;
 714                                 bits = <5 5>;
 715                         };
 716                         comb_intr_p1: usb3-intr@187 {
 717                                 reg = <0x187 0x1>;
 718                                 bits = <2 6>;
 719                         };
 720                         u2_intr_p0: usb2-intr-p0@188,1 {
 721                                 reg = <0x188 0x1>;
 722                                 bits = <0 5>;
 723                         };
 724                         u2_intr_p1: usb2-intr-p1@188,2 {
 725                                 reg = <0x188 0x2>;
 726                                 bits = <5 5>;
 727                         };
 728                         u2_intr_p2: usb2-intr-p2@189,1 {
 729                                 reg = <0x189 0x1>;
 730                                 bits = <2 5>;
 731                         };
 732                         u2_intr_p3: usb2-intr-p3@189,2 {
 733                                 reg = <0x189 0x2>;
 734                                 bits = <7 5>;
 735                         };
 736                 };
 737
 738                 u3phy2: t-phy@11c40000 {
 739                         compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
 740                         #address-cells = <1>;
 741                         #size-cells = <1>;
 742                         ranges = <0 0 0x11c40000 0x700>;
 743                         status = "disabled";
 744
 745                         u2port2: usb-phy@0 {
 746                                 reg = <0x0 0x700>;
 747                                 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>;
 748                                 clock-names = "ref";
 749                                 #phy-cells = <1>;
 750                         };
 751                 };
 752
 753                 u3phy3: t-phy@11c50000 {
 754                         compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
 755                         #address-cells = <1>;
 756                         #size-cells = <1>;
 757                         ranges = <0 0 0x11c50000 0x700>;
 758                         status = "disabled";
 759
 760                         u2port3: usb-phy@0 {
 761                                 reg = <0x0 0x700>;
 762                                 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>;
 763                                 clock-names = "ref";
 764                                 #phy-cells = <1>;
 765                         };
 766                 };
 767
 768                 i2c5: i2c@11d00000 {
 769                         compatible = "mediatek,mt8195-i2c",
 770                                      "mediatek,mt8192-i2c";
 771                         reg = <0 0x11d00000 0 0x1000>,
 772                               <0 0x10220580 0 0x80>;
 773                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>;
 774                         clock-div = <1>;
 775                         clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>,
 776                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
 777                         clock-names = "main", "dma";
 778                         #address-cells = <1>;
 779                         #size-cells = <0>;
 780                         status = "disabled";
 781                 };
 782
 783                 i2c6: i2c@11d01000 {
 784                         compatible = "mediatek,mt8195-i2c",
 785                                      "mediatek,mt8192-i2c";
 786                         reg = <0 0x11d01000 0 0x1000>,
 787                               <0 0x10220600 0 0x80>;
 788                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
 789                         clock-div = <1>;
 790                         clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>,
 791                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
 792                         clock-names = "main", "dma";
 793                         #address-cells = <1>;
 794                         #size-cells = <0>;
 795                         status = "disabled";
 796                 };
 797
 798                 i2c7: i2c@11d02000 {
 799                         compatible = "mediatek,mt8195-i2c",
 800                                      "mediatek,mt8192-i2c";
 801                         reg = <0 0x11d02000 0 0x1000>,
 802                               <0 0x10220680 0 0x80>;
 803                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
 804                         clock-div = <1>;
 805                         clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
 806                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
 807                         clock-names = "main", "dma";
 808                         #address-cells = <1>;
 809                         #size-cells = <0>;
 810                         status = "disabled";
 811                 };
 812
 813                 imp_iic_wrap_s: clock-controller@11d03000 {
 814                         compatible = "mediatek,mt8195-imp_iic_wrap_s";
 815                         reg = <0 0x11d03000 0 0x1000>;
 816                         #clock-cells = <1>;
 817                 };
 818
 819                 i2c0: i2c@11e00000 {
 820                         compatible = "mediatek,mt8195-i2c",
 821                                      "mediatek,mt8192-i2c";
 822                         reg = <0 0x11e00000 0 0x1000>,
 823                               <0 0x10220080 0 0x80>;
 824                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>;
 825                         clock-div = <1>;
 826                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>,
 827                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
 828                         clock-names = "main", "dma";
 829                         #address-cells = <1>;
 830                         #size-cells = <0>;
 831                         status = "okay";
 832                 };
 833
 834                 i2c1: i2c@11e01000 {
 835                         compatible = "mediatek,mt8195-i2c",
 836                                      "mediatek,mt8192-i2c";
 837                         reg = <0 0x11e01000 0 0x1000>,
 838                               <0 0x10220200 0 0x80>;
 839                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
 840                         clock-div = <1>;
 841                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>,
 842                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
 843                         clock-names = "main", "dma";
 844                         #address-cells = <1>;
 845                         #size-cells = <0>;
 846                         status = "disabled";
 847                 };
 848
 849                 i2c2: i2c@11e02000 {
 850                         compatible = "mediatek,mt8195-i2c",
 851                                      "mediatek,mt8192-i2c";
 852                         reg = <0 0x11e02000 0 0x1000>,
 853                               <0 0x10220380 0 0x80>;
 854                         interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
 855                         clock-div = <1>;
 856                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>,
 857                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
 858                         clock-names = "main", "dma";
 859                         #address-cells = <1>;
 860                         #size-cells = <0>;
 861                         status = "disabled";
 862                 };
 863
 864                 i2c3: i2c@11e03000 {
 865                         compatible = "mediatek,mt8195-i2c",
 866                                      "mediatek,mt8192-i2c";
 867                         reg = <0 0x11e03000 0 0x1000>,
 868                               <0 0x10220480 0 0x80>;
 869                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
 870                         clock-div = <1>;
 871                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>,
 872                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
 873                         clock-names = "main", "dma";
 874                         #address-cells = <1>;
 875                         #size-cells = <0>;
 876                         status = "disabled";
 877                 };
 878
 879                 i2c4: i2c@11e04000 {
 880                         compatible = "mediatek,mt8195-i2c",
 881                                      "mediatek,mt8192-i2c";
 882                         reg = <0 0x11e04000 0 0x1000>,
 883                               <0 0x10220500 0 0x80>;
 884                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>;
 885                         clock-div = <1>;
 886                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>,
 887                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
 888                         clock-names = "main", "dma";
 889                         #address-cells = <1>;
 890                         #size-cells = <0>;
 891                         status = "disabled";
 892                 };
 893
 894                 imp_iic_wrap_w: clock-controller@11e05000 {
 895                         compatible = "mediatek,mt8195-imp_iic_wrap_w";
 896                         reg = <0 0x11e05000 0 0x1000>;
 897                         #clock-cells = <1>;
 898                 };
 899
 900                 u3phy1: t-phy@11e30000 {
 901                         compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
 902                         #address-cells = <1>;
 903                         #size-cells = <1>;
 904                         ranges = <0 0 0x11e30000 0xe00>;
 905                         status = "disabled";
 906
 907                         u2port1: usb-phy@0 {
 908                                 reg = <0x0 0x700>;
 909                                 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
 910                                          <&clk26m>;
 911                                 clock-names = "ref", "da_ref";
 912                                 #phy-cells = <1>;
 913                         };
 914
 915                         u3port1: usb-phy@700 {
 916                                 reg = <0x700 0x700>;
 917                                 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
 918                                          <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
 919                                 clock-names = "ref", "da_ref";
 920                                 nvmem-cells = <&comb_intr_p1>,
 921                                               <&comb_rx_imp_p1>,
 922                                               <&comb_tx_imp_p1>;
 923                                 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
 924                                 #phy-cells = <1>;
 925                         };
 926                 };
 927
 928                 u3phy0: t-phy@11e40000 {
 929                         compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
 930                         #address-cells = <1>;
 931                         #size-cells = <1>;
 932                         ranges = <0 0 0x11e40000 0xe00>;
 933                         status = "disabled";
 934
 935                         u2port0: usb-phy@0 {
 936                                 reg = <0x0 0x700>;
 937                                 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
 938                                          <&clk26m>;
 939                                 clock-names = "ref", "da_ref";
 940                                 #phy-cells = <1>;
 941                         };
 942
 943                         u3port0: usb-phy@700 {
 944                                 reg = <0x700 0x700>;
 945                                 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
 946                                          <&topckgen CLK_TOP_SSUSB_PHY_REF>;
 947                                 clock-names = "ref", "da_ref";
 948                                 nvmem-cells = <&u3_intr_p0>,
 949                                               <&u3_rx_imp_p0>,
 950                                               <&u3_tx_imp_p0>;
 951                                 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
 952                                 #phy-cells = <1>;
 953                         };
 954                 };
 955
 956                 ufsphy: ufs-phy@11fa0000 {
 957                         compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
 958                         reg = <0 0x11fa0000 0 0xc000>;
 959                         clocks = <&clk26m>, <&clk26m>;
 960                         clock-names = "unipro", "mp";
 961                         #phy-cells = <0>;
 962                         status = "disabled";
 963                 };
 964
 965                 mfgcfg: clock-controller@13fbf000 {
 966                         compatible = "mediatek,mt8195-mfgcfg";
 967                         reg = <0 0x13fbf000 0 0x1000>;
 968                         #clock-cells = <1>;
 969                 };
 970
 971                 wpesys: clock-controller@14e00000 {
 972                         compatible = "mediatek,mt8195-wpesys";
 973                         reg = <0 0x14e00000 0 0x1000>;
 974                         #clock-cells = <1>;
 975                 };
 976
 977                 wpesys_vpp0: clock-controller@14e02000 {
 978                         compatible = "mediatek,mt8195-wpesys_vpp0";
 979                         reg = <0 0x14e02000 0 0x1000>;
 980                         #clock-cells = <1>;
 981                 };
 982
 983                 wpesys_vpp1: clock-controller@14e03000 {
 984                         compatible = "mediatek,mt8195-wpesys_vpp1";
 985                         reg = <0 0x14e03000 0 0x1000>;
 986                         #clock-cells = <1>;
 987                 };
 988
 989                 imgsys: clock-controller@15000000 {
 990                         compatible = "mediatek,mt8195-imgsys";
 991                         reg = <0 0x15000000 0 0x1000>;
 992                         #clock-cells = <1>;
 993                 };
 994
 995                 imgsys1_dip_top: clock-controller@15110000 {
 996                         compatible = "mediatek,mt8195-imgsys1_dip_top";
 997                         reg = <0 0x15110000 0 0x1000>;
 998                         #clock-cells = <1>;
 999                 };
1000
1001                 imgsys1_dip_nr: clock-controller@15130000 {
1002                         compatible = "mediatek,mt8195-imgsys1_dip_nr";
1003                         reg = <0 0x15130000 0 0x1000>;
1004                         #clock-cells = <1>;
1005                 };
1006
1007                 imgsys1_wpe: clock-controller@15220000 {
1008                         compatible = "mediatek,mt8195-imgsys1_wpe";
1009                         reg = <0 0x15220000 0 0x1000>;
1010                         #clock-cells = <1>;
1011                 };
1012
1013                 ipesys: clock-controller@15330000 {
1014                         compatible = "mediatek,mt8195-ipesys";
1015                         reg = <0 0x15330000 0 0x1000>;
1016                         #clock-cells = <1>;
1017                 };
1018
1019                 camsys: clock-controller@16000000 {
1020                         compatible = "mediatek,mt8195-camsys";
1021                         reg = <0 0x16000000 0 0x1000>;
1022                         #clock-cells = <1>;
1023                 };
1024
1025                 camsys_rawa: clock-controller@1604f000 {
1026                         compatible = "mediatek,mt8195-camsys_rawa";
1027                         reg = <0 0x1604f000 0 0x1000>;
1028                         #clock-cells = <1>;
1029                 };
1030
1031                 camsys_yuva: clock-controller@1606f000 {
1032                         compatible = "mediatek,mt8195-camsys_yuva";
1033                         reg = <0 0x1606f000 0 0x1000>;
1034                         #clock-cells = <1>;
1035                 };
1036
1037                 camsys_rawb: clock-controller@1608f000 {
1038                         compatible = "mediatek,mt8195-camsys_rawb";
1039                         reg = <0 0x1608f000 0 0x1000>;
1040                         #clock-cells = <1>;
1041                 };
1042
1043                 camsys_yuvb: clock-controller@160af000 {
1044                         compatible = "mediatek,mt8195-camsys_yuvb";
1045                         reg = <0 0x160af000 0 0x1000>;
1046                         #clock-cells = <1>;
1047                 };
1048
1049                 camsys_mraw: clock-controller@16140000 {
1050                         compatible = "mediatek,mt8195-camsys_mraw";
1051                         reg = <0 0x16140000 0 0x1000>;
1052                         #clock-cells = <1>;
1053                 };
1054
1055                 ccusys: clock-controller@17200000 {
1056                         compatible = "mediatek,mt8195-ccusys";
1057                         reg = <0 0x17200000 0 0x1000>;
1058                         #clock-cells = <1>;
1059                 };
1060
1061                 vdecsys_soc: clock-controller@1800f000 {
1062                         compatible = "mediatek,mt8195-vdecsys_soc";
1063                         reg = <0 0x1800f000 0 0x1000>;
1064                         #clock-cells = <1>;
1065                 };
1066
1067                 vdecsys: clock-controller@1802f000 {
1068                         compatible = "mediatek,mt8195-vdecsys";
1069                         reg = <0 0x1802f000 0 0x1000>;
1070                         #clock-cells = <1>;
1071                 };
1072
1073                 vdecsys_core1: clock-controller@1803f000 {
1074                         compatible = "mediatek,mt8195-vdecsys_core1";
1075                         reg = <0 0x1803f000 0 0x1000>;
1076                         #clock-cells = <1>;
1077                 };
1078
1079                 apusys_pll: clock-controller@190f3000 {
1080                         compatible = "mediatek,mt8195-apusys_pll";
1081                         reg = <0 0x190f3000 0 0x1000>;
1082                         #clock-cells = <1>;
1083                 };
1084
1085                 vencsys: clock-controller@1a000000 {
1086                         compatible = "mediatek,mt8195-vencsys";
1087                         reg = <0 0x1a000000 0 0x1000>;
1088                         #clock-cells = <1>;
1089                 };
1090
1091                 vencsys_core1: clock-controller@1b000000 {
1092                         compatible = "mediatek,mt8195-vencsys_core1";
1093                         reg = <0 0x1b000000 0 0x1000>;
1094                         #clock-cells = <1>;
1095                 };
1096         };
1097 };