src/arm64/mediatek/mt8195.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (c) 2021 MediaTek Inc.
   4  * Author: Seiya Wang <seiya.wang@mediatek.com>
   5  */
   6
   7 /dts-v1/;
   8 #include <dt-bindings/clock/mt8195-clk.h>
   9 #include <dt-bindings/gce/mt8195-gce.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include <dt-bindings/memory/mt8195-memory-port.h>
  13 #include <dt-bindings/phy/phy.h>
  14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
  15 #include <dt-bindings/power/mt8195-power.h>
  16 #include <dt-bindings/reset/mt8195-resets.h>
  17 #include <dt-bindings/thermal/thermal.h>
  18 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
  19
  20 / {
  21         compatible = "mediatek,mt8195";
  22         interrupt-parent = <&gic>;
  23         #address-cells = <2>;
  24         #size-cells = <2>;
  25
  26         aliases {
  27                 gce0 = &gce0;
  28                 gce1 = &gce1;
  29                 ethdr0 = &ethdr0;
  30                 mutex0 = &mutex;
  31                 mutex1 = &mutex1;
  32                 merge1 = &merge1;
  33                 merge2 = &merge2;
  34                 merge3 = &merge3;
  35                 merge4 = &merge4;
  36                 merge5 = &merge5;
  37                 vdo1-rdma0 = &vdo1_rdma0;
  38                 vdo1-rdma1 = &vdo1_rdma1;
  39                 vdo1-rdma2 = &vdo1_rdma2;
  40                 vdo1-rdma3 = &vdo1_rdma3;
  41                 vdo1-rdma4 = &vdo1_rdma4;
  42                 vdo1-rdma5 = &vdo1_rdma5;
  43                 vdo1-rdma6 = &vdo1_rdma6;
  44                 vdo1-rdma7 = &vdo1_rdma7;
  45         };
  46
  47         cpus {
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50
  51                 cpu0: cpu@0 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a55";
  54                         reg = <0x000>;
  55                         enable-method = "psci";
  56                         performance-domains = <&performance 0>;
  57                         clock-frequency = <1701000000>;
  58                         capacity-dmips-mhz = <308>;
  59                         cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
  60                         i-cache-size = <32768>;
  61                         i-cache-line-size = <64>;
  62                         i-cache-sets = <128>;
  63                         d-cache-size = <32768>;
  64                         d-cache-line-size = <64>;
  65                         d-cache-sets = <128>;
  66                         next-level-cache = <&l2_0>;
  67                         #cooling-cells = <2>;
  68                 };
  69
  70                 cpu1: cpu@100 {
  71                         device_type = "cpu";
  72                         compatible = "arm,cortex-a55";
  73                         reg = <0x100>;
  74                         enable-method = "psci";
  75                         performance-domains = <&performance 0>;
  76                         clock-frequency = <1701000000>;
  77                         capacity-dmips-mhz = <308>;
  78                         cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
  79                         i-cache-size = <32768>;
  80                         i-cache-line-size = <64>;
  81                         i-cache-sets = <128>;
  82                         d-cache-size = <32768>;
  83                         d-cache-line-size = <64>;
  84                         d-cache-sets = <128>;
  85                         next-level-cache = <&l2_0>;
  86                         #cooling-cells = <2>;
  87                 };
  88
  89                 cpu2: cpu@200 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a55";
  92                         reg = <0x200>;
  93                         enable-method = "psci";
  94                         performance-domains = <&performance 0>;
  95                         clock-frequency = <1701000000>;
  96                         capacity-dmips-mhz = <308>;
  97                         cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
  98                         i-cache-size = <32768>;
  99                         i-cache-line-size = <64>;
 100                         i-cache-sets = <128>;
 101                         d-cache-size = <32768>;
 102                         d-cache-line-size = <64>;
 103                         d-cache-sets = <128>;
 104                         next-level-cache = <&l2_0>;
 105                         #cooling-cells = <2>;
 106                 };
 107
 108                 cpu3: cpu@300 {
 109                         device_type = "cpu";
 110                         compatible = "arm,cortex-a55";
 111                         reg = <0x300>;
 112                         enable-method = "psci";
 113                         performance-domains = <&performance 0>;
 114                         clock-frequency = <1701000000>;
 115                         capacity-dmips-mhz = <308>;
 116                         cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
 117                         i-cache-size = <32768>;
 118                         i-cache-line-size = <64>;
 119                         i-cache-sets = <128>;
 120                         d-cache-size = <32768>;
 121                         d-cache-line-size = <64>;
 122                         d-cache-sets = <128>;
 123                         next-level-cache = <&l2_0>;
 124                         #cooling-cells = <2>;
 125                 };
 126
 127                 cpu4: cpu@400 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a78";
 130                         reg = <0x400>;
 131                         enable-method = "psci";
 132                         performance-domains = <&performance 1>;
 133                         clock-frequency = <2171000000>;
 134                         capacity-dmips-mhz = <1024>;
 135                         cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
 136                         i-cache-size = <65536>;
 137                         i-cache-line-size = <64>;
 138                         i-cache-sets = <256>;
 139                         d-cache-size = <65536>;
 140                         d-cache-line-size = <64>;
 141                         d-cache-sets = <256>;
 142                         next-level-cache = <&l2_1>;
 143                         #cooling-cells = <2>;
 144                 };
 145
 146                 cpu5: cpu@500 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a78";
 149                         reg = <0x500>;
 150                         enable-method = "psci";
 151                         performance-domains = <&performance 1>;
 152                         clock-frequency = <2171000000>;
 153                         capacity-dmips-mhz = <1024>;
 154                         cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
 155                         i-cache-size = <65536>;
 156                         i-cache-line-size = <64>;
 157                         i-cache-sets = <256>;
 158                         d-cache-size = <65536>;
 159                         d-cache-line-size = <64>;
 160                         d-cache-sets = <256>;
 161                         next-level-cache = <&l2_1>;
 162                         #cooling-cells = <2>;
 163                 };
 164
 165                 cpu6: cpu@600 {
 166                         device_type = "cpu";
 167                         compatible = "arm,cortex-a78";
 168                         reg = <0x600>;
 169                         enable-method = "psci";
 170                         performance-domains = <&performance 1>;
 171                         clock-frequency = <2171000000>;
 172                         capacity-dmips-mhz = <1024>;
 173                         cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
 174                         i-cache-size = <65536>;
 175                         i-cache-line-size = <64>;
 176                         i-cache-sets = <256>;
 177                         d-cache-size = <65536>;
 178                         d-cache-line-size = <64>;
 179                         d-cache-sets = <256>;
 180                         next-level-cache = <&l2_1>;
 181                         #cooling-cells = <2>;
 182                 };
 183
 184                 cpu7: cpu@700 {
 185                         device_type = "cpu";
 186                         compatible = "arm,cortex-a78";
 187                         reg = <0x700>;
 188                         enable-method = "psci";
 189                         performance-domains = <&performance 1>;
 190                         clock-frequency = <2171000000>;
 191                         capacity-dmips-mhz = <1024>;
 192                         cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
 193                         i-cache-size = <65536>;
 194                         i-cache-line-size = <64>;
 195                         i-cache-sets = <256>;
 196                         d-cache-size = <65536>;
 197                         d-cache-line-size = <64>;
 198                         d-cache-sets = <256>;
 199                         next-level-cache = <&l2_1>;
 200                         #cooling-cells = <2>;
 201                 };
 202
 203                 cpu-map {
 204                         cluster0 {
 205                                 core0 {
 206                                         cpu = <&cpu0>;
 207                                 };
 208
 209                                 core1 {
 210                                         cpu = <&cpu1>;
 211                                 };
 212
 213                                 core2 {
 214                                         cpu = <&cpu2>;
 215                                 };
 216
 217                                 core3 {
 218                                         cpu = <&cpu3>;
 219                                 };
 220
 221                                 core4 {
 222                                         cpu = <&cpu4>;
 223                                 };
 224
 225                                 core5 {
 226                                         cpu = <&cpu5>;
 227                                 };
 228
 229                                 core6 {
 230                                         cpu = <&cpu6>;
 231                                 };
 232
 233                                 core7 {
 234                                         cpu = <&cpu7>;
 235                                 };
 236                         };
 237                 };
 238
 239                 idle-states {
 240                         entry-method = "psci";
 241
 242                         cpu_ret_l: cpu-retention-l {
 243                                 compatible = "arm,idle-state";
 244                                 arm,psci-suspend-param = <0x00010001>;
 245                                 local-timer-stop;
 246                                 entry-latency-us = <50>;
 247                                 exit-latency-us = <95>;
 248                                 min-residency-us = <580>;
 249                         };
 250
 251                         cpu_ret_b: cpu-retention-b {
 252                                 compatible = "arm,idle-state";
 253                                 arm,psci-suspend-param = <0x00010001>;
 254                                 local-timer-stop;
 255                                 entry-latency-us = <45>;
 256                                 exit-latency-us = <140>;
 257                                 min-residency-us = <740>;
 258                         };
 259
 260                         cpu_off_l: cpu-off-l {
 261                                 compatible = "arm,idle-state";
 262                                 arm,psci-suspend-param = <0x01010002>;
 263                                 local-timer-stop;
 264                                 entry-latency-us = <55>;
 265                                 exit-latency-us = <155>;
 266                                 min-residency-us = <840>;
 267                         };
 268
 269                         cpu_off_b: cpu-off-b {
 270                                 compatible = "arm,idle-state";
 271                                 arm,psci-suspend-param = <0x01010002>;
 272                                 local-timer-stop;
 273                                 entry-latency-us = <50>;
 274                                 exit-latency-us = <200>;
 275                                 min-residency-us = <1000>;
 276                         };
 277                 };
 278
 279                 l2_0: l2-cache0 {
 280                         compatible = "cache";
 281                         cache-level = <2>;
 282                         cache-size = <131072>;
 283                         cache-line-size = <64>;
 284                         cache-sets = <512>;
 285                         next-level-cache = <&l3_0>;
 286                 };
 287
 288                 l2_1: l2-cache1 {
 289                         compatible = "cache";
 290                         cache-level = <2>;
 291                         cache-size = <262144>;
 292                         cache-line-size = <64>;
 293                         cache-sets = <512>;
 294                         next-level-cache = <&l3_0>;
 295                 };
 296
 297                 l3_0: l3-cache {
 298                         compatible = "cache";
 299                         cache-level = <3>;
 300                         cache-size = <2097152>;
 301                         cache-line-size = <64>;
 302                         cache-sets = <2048>;
 303                         cache-unified;
 304                 };
 305         };
 306
 307         dsu-pmu {
 308                 compatible = "arm,dsu-pmu";
 309                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
 310                 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
 311                        <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
 312         };
 313
 314         dmic_codec: dmic-codec {
 315                 compatible = "dmic-codec";
 316                 num-channels = <2>;
 317                 wakeup-delay-ms = <50>;
 318         };
 319
 320         sound: mt8195-sound {
 321                 mediatek,platform = <&afe>;
 322                 status = "disabled";
 323         };
 324
 325         clk13m: fixed-factor-clock-13m {
 326                 compatible = "fixed-factor-clock";
 327                 #clock-cells = <0>;
 328                 clocks = <&clk26m>;
 329                 clock-div = <2>;
 330                 clock-mult = <1>;
 331                 clock-output-names = "clk13m";
 332         };
 333
 334         clk26m: oscillator-26m {
 335                 compatible = "fixed-clock";
 336                 #clock-cells = <0>;
 337                 clock-frequency = <26000000>;
 338                 clock-output-names = "clk26m";
 339         };
 340
 341         clk32k: oscillator-32k {
 342                 compatible = "fixed-clock";
 343                 #clock-cells = <0>;
 344                 clock-frequency = <32768>;
 345                 clock-output-names = "clk32k";
 346         };
 347
 348         performance: performance-controller@11bc10 {
 349                 compatible = "mediatek,cpufreq-hw";
 350                 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
 351                 #performance-domain-cells = <1>;
 352         };
 353
 354         gpu_opp_table: opp-table-gpu {
 355                 compatible = "operating-points-v2";
 356                 opp-shared;
 357
 358                 opp-390000000 {
 359                         opp-hz = /bits/ 64 <390000000>;
 360                         opp-microvolt = <625000>;
 361                 };
 362                 opp-410000000 {
 363                         opp-hz = /bits/ 64 <410000000>;
 364                         opp-microvolt = <631250>;
 365                 };
 366                 opp-431000000 {
 367                         opp-hz = /bits/ 64 <431000000>;
 368                         opp-microvolt = <631250>;
 369                 };
 370                 opp-473000000 {
 371                         opp-hz = /bits/ 64 <473000000>;
 372                         opp-microvolt = <637500>;
 373                 };
 374                 opp-515000000 {
 375                         opp-hz = /bits/ 64 <515000000>;
 376                         opp-microvolt = <637500>;
 377                 };
 378                 opp-556000000 {
 379                         opp-hz = /bits/ 64 <556000000>;
 380                         opp-microvolt = <643750>;
 381                 };
 382                 opp-598000000 {
 383                         opp-hz = /bits/ 64 <598000000>;
 384                         opp-microvolt = <650000>;
 385                 };
 386                 opp-640000000 {
 387                         opp-hz = /bits/ 64 <640000000>;
 388                         opp-microvolt = <650000>;
 389                 };
 390                 opp-670000000 {
 391                         opp-hz = /bits/ 64 <670000000>;
 392                         opp-microvolt = <662500>;
 393                 };
 394                 opp-700000000 {
 395                         opp-hz = /bits/ 64 <700000000>;
 396                         opp-microvolt = <675000>;
 397                 };
 398                 opp-730000000 {
 399                         opp-hz = /bits/ 64 <730000000>;
 400                         opp-microvolt = <687500>;
 401                 };
 402                 opp-760000000 {
 403                         opp-hz = /bits/ 64 <760000000>;
 404                         opp-microvolt = <700000>;
 405                 };
 406                 opp-790000000 {
 407                         opp-hz = /bits/ 64 <790000000>;
 408                         opp-microvolt = <712500>;
 409                 };
 410                 opp-820000000 {
 411                         opp-hz = /bits/ 64 <820000000>;
 412                         opp-microvolt = <725000>;
 413                 };
 414                 opp-850000000 {
 415                         opp-hz = /bits/ 64 <850000000>;
 416                         opp-microvolt = <737500>;
 417                 };
 418                 opp-880000000 {
 419                         opp-hz = /bits/ 64 <880000000>;
 420                         opp-microvolt = <750000>;
 421                 };
 422         };
 423
 424         pmu-a55 {
 425                 compatible = "arm,cortex-a55-pmu";
 426                 interrupt-parent = <&gic>;
 427                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
 428         };
 429
 430         pmu-a78 {
 431                 compatible = "arm,cortex-a78-pmu";
 432                 interrupt-parent = <&gic>;
 433                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
 434         };
 435
 436         psci {
 437                 compatible = "arm,psci-1.0";
 438                 method = "smc";
 439         };
 440
 441         timer: timer {
 442                 compatible = "arm,armv8-timer";
 443                 interrupt-parent = <&gic>;
 444                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
 445                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
 446                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
 447                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
 448         };
 449
 450         soc {
 451                 #address-cells = <2>;
 452                 #size-cells = <2>;
 453                 compatible = "simple-bus";
 454                 ranges;
 455                 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
 456
 457                 gic: interrupt-controller@c000000 {
 458                         compatible = "arm,gic-v3";
 459                         #interrupt-cells = <4>;
 460                         #redistributor-regions = <1>;
 461                         interrupt-parent = <&gic>;
 462                         interrupt-controller;
 463                         reg = <0 0x0c000000 0 0x40000>,
 464                               <0 0x0c040000 0 0x200000>;
 465                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 466
 467                         ppi-partitions {
 468                                 ppi_cluster0: interrupt-partition-0 {
 469                                         affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
 470                                 };
 471
 472                                 ppi_cluster1: interrupt-partition-1 {
 473                                         affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
 474                                 };
 475                         };
 476                 };
 477
 478                 topckgen: syscon@10000000 {
 479                         compatible = "mediatek,mt8195-topckgen", "syscon";
 480                         reg = <0 0x10000000 0 0x1000>;
 481                         #clock-cells = <1>;
 482                 };
 483
 484                 infracfg_ao: syscon@10001000 {
 485                         compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
 486                         reg = <0 0x10001000 0 0x1000>;
 487                         #clock-cells = <1>;
 488                         #reset-cells = <1>;
 489                 };
 490
 491                 pericfg: syscon@10003000 {
 492                         compatible = "mediatek,mt8195-pericfg", "syscon";
 493                         reg = <0 0x10003000 0 0x1000>;
 494                         #clock-cells = <1>;
 495                 };
 496
 497                 pio: pinctrl@10005000 {
 498                         compatible = "mediatek,mt8195-pinctrl";
 499                         reg = <0 0x10005000 0 0x1000>,
 500                               <0 0x11d10000 0 0x1000>,
 501                               <0 0x11d30000 0 0x1000>,
 502                               <0 0x11d40000 0 0x1000>,
 503                               <0 0x11e20000 0 0x1000>,
 504                               <0 0x11eb0000 0 0x1000>,
 505                               <0 0x11f40000 0 0x1000>,
 506                               <0 0x1000b000 0 0x1000>;
 507                         reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
 508                                     "iocfg_br", "iocfg_lm", "iocfg_rb",
 509                                     "iocfg_tl", "eint";
 510                         gpio-controller;
 511                         #gpio-cells = <2>;
 512                         gpio-ranges = <&pio 0 0 144>;
 513                         interrupt-controller;
 514                         interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
 515                         #interrupt-cells = <2>;
 516                 };
 517
 518                 scpsys: syscon@10006000 {
 519                         compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
 520                         reg = <0 0x10006000 0 0x1000>;
 521
 522                         /* System Power Manager */
 523                         spm: power-controller {
 524                                 compatible = "mediatek,mt8195-power-controller";
 525                                 #address-cells = <1>;
 526                                 #size-cells = <0>;
 527                                 #power-domain-cells = <1>;
 528
 529                                 /* power domain of the SoC */
 530                                 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
 531                                         reg = <MT8195_POWER_DOMAIN_MFG0>;
 532                                         #address-cells = <1>;
 533                                         #size-cells = <0>;
 534                                         #power-domain-cells = <1>;
 535
 536                                         power-domain@MT8195_POWER_DOMAIN_MFG1 {
 537                                                 reg = <MT8195_POWER_DOMAIN_MFG1>;
 538                                                 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>,
 539                                                          <&topckgen CLK_TOP_MFG_CORE_TMP>;
 540                                                 clock-names = "mfg", "alt";
 541                                                 mediatek,infracfg = <&infracfg_ao>;
 542                                                 #address-cells = <1>;
 543                                                 #size-cells = <0>;
 544                                                 #power-domain-cells = <1>;
 545
 546                                                 power-domain@MT8195_POWER_DOMAIN_MFG2 {
 547                                                         reg = <MT8195_POWER_DOMAIN_MFG2>;
 548                                                         #power-domain-cells = <0>;
 549                                                 };
 550
 551                                                 power-domain@MT8195_POWER_DOMAIN_MFG3 {
 552                                                         reg = <MT8195_POWER_DOMAIN_MFG3>;
 553                                                         #power-domain-cells = <0>;
 554                                                 };
 555
 556                                                 power-domain@MT8195_POWER_DOMAIN_MFG4 {
 557                                                         reg = <MT8195_POWER_DOMAIN_MFG4>;
 558                                                         #power-domain-cells = <0>;
 559                                                 };
 560
 561                                                 power-domain@MT8195_POWER_DOMAIN_MFG5 {
 562                                                         reg = <MT8195_POWER_DOMAIN_MFG5>;
 563                                                         #power-domain-cells = <0>;
 564                                                 };
 565
 566                                                 power-domain@MT8195_POWER_DOMAIN_MFG6 {
 567                                                         reg = <MT8195_POWER_DOMAIN_MFG6>;
 568                                                         #power-domain-cells = <0>;
 569                                                 };
 570                                         };
 571                                 };
 572
 573                                 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
 574                                         reg = <MT8195_POWER_DOMAIN_VPPSYS0>;
 575                                         clocks = <&topckgen CLK_TOP_VPP>,
 576                                                  <&topckgen CLK_TOP_CAM>,
 577                                                  <&topckgen CLK_TOP_CCU>,
 578                                                  <&topckgen CLK_TOP_IMG>,
 579                                                  <&topckgen CLK_TOP_VENC>,
 580                                                  <&topckgen CLK_TOP_VDEC>,
 581                                                  <&topckgen CLK_TOP_WPE_VPP>,
 582                                                  <&topckgen CLK_TOP_CFG_VPP0>,
 583                                                  <&vppsys0 CLK_VPP0_SMI_COMMON>,
 584                                                  <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>,
 585                                                  <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>,
 586                                                  <&vppsys0 CLK_VPP0_GALS_VENCSYS>,
 587                                                  <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>,
 588                                                  <&vppsys0 CLK_VPP0_GALS_INFRA>,
 589                                                  <&vppsys0 CLK_VPP0_GALS_CAMSYS>,
 590                                                  <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>,
 591                                                  <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>,
 592                                                  <&vppsys0 CLK_VPP0_SMI_REORDER>,
 593                                                  <&vppsys0 CLK_VPP0_SMI_IOMMU>,
 594                                                  <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
 595                                                  <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
 596                                                  <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
 597                                                  <&vppsys0 CLK_VPP0_SMI_RSI>,
 598                                                  <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
 599                                                  <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
 600                                                  <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
 601                                                  <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
 602                                         clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
 603                                                       "vppsys4", "vppsys5", "vppsys6", "vppsys7",
 604                                                       "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
 605                                                       "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
 606                                                       "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
 607                                                       "vppsys0-12", "vppsys0-13", "vppsys0-14",
 608                                                       "vppsys0-15", "vppsys0-16", "vppsys0-17",
 609                                                       "vppsys0-18";
 610                                         mediatek,infracfg = <&infracfg_ao>;
 611                                         #address-cells = <1>;
 612                                         #size-cells = <0>;
 613                                         #power-domain-cells = <1>;
 614
 615                                         power-domain@MT8195_POWER_DOMAIN_VDEC1 {
 616                                                 reg = <MT8195_POWER_DOMAIN_VDEC1>;
 617                                                 clocks = <&vdecsys CLK_VDEC_LARB1>;
 618                                                 clock-names = "vdec1-0";
 619                                                 mediatek,infracfg = <&infracfg_ao>;
 620                                                 #power-domain-cells = <0>;
 621                                         };
 622
 623                                         power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
 624                                                 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
 625                                                 mediatek,infracfg = <&infracfg_ao>;
 626                                                 #power-domain-cells = <0>;
 627                                         };
 628
 629                                         power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
 630                                                 reg = <MT8195_POWER_DOMAIN_VDOSYS0>;
 631                                                 clocks = <&topckgen CLK_TOP_CFG_VDO0>,
 632                                                          <&vdosys0 CLK_VDO0_SMI_GALS>,
 633                                                          <&vdosys0 CLK_VDO0_SMI_COMMON>,
 634                                                          <&vdosys0 CLK_VDO0_SMI_EMI>,
 635                                                          <&vdosys0 CLK_VDO0_SMI_IOMMU>,
 636                                                          <&vdosys0 CLK_VDO0_SMI_LARB>,
 637                                                          <&vdosys0 CLK_VDO0_SMI_RSI>;
 638                                                 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
 639                                                               "vdosys0-2", "vdosys0-3",
 640                                                               "vdosys0-4", "vdosys0-5";
 641                                                 mediatek,infracfg = <&infracfg_ao>;
 642                                                 #address-cells = <1>;
 643                                                 #size-cells = <0>;
 644                                                 #power-domain-cells = <1>;
 645
 646                                                 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
 647                                                         reg = <MT8195_POWER_DOMAIN_VPPSYS1>;
 648                                                         clocks = <&topckgen CLK_TOP_CFG_VPP1>,
 649                                                                  <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
 650                                                                  <&vppsys1 CLK_VPP1_VPPSYS1_LARB>;
 651                                                         clock-names = "vppsys1", "vppsys1-0",
 652                                                                       "vppsys1-1";
 653                                                         mediatek,infracfg = <&infracfg_ao>;
 654                                                         #power-domain-cells = <0>;
 655                                                 };
 656
 657                                                 power-domain@MT8195_POWER_DOMAIN_WPESYS {
 658                                                         reg = <MT8195_POWER_DOMAIN_WPESYS>;
 659                                                         clocks = <&wpesys CLK_WPE_SMI_LARB7>,
 660                                                                  <&wpesys CLK_WPE_SMI_LARB8>,
 661                                                                  <&wpesys CLK_WPE_SMI_LARB7_P>,
 662                                                                  <&wpesys CLK_WPE_SMI_LARB8_P>;
 663                                                         clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
 664                                                                       "wepsys-3";
 665                                                         mediatek,infracfg = <&infracfg_ao>;
 666                                                         #power-domain-cells = <0>;
 667                                                 };
 668
 669                                                 power-domain@MT8195_POWER_DOMAIN_VDEC0 {
 670                                                         reg = <MT8195_POWER_DOMAIN_VDEC0>;
 671                                                         clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
 672                                                         clock-names = "vdec0-0";
 673                                                         mediatek,infracfg = <&infracfg_ao>;
 674                                                         #power-domain-cells = <0>;
 675                                                 };
 676
 677                                                 power-domain@MT8195_POWER_DOMAIN_VDEC2 {
 678                                                         reg = <MT8195_POWER_DOMAIN_VDEC2>;
 679                                                         clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
 680                                                         clock-names = "vdec2-0";
 681                                                         mediatek,infracfg = <&infracfg_ao>;
 682                                                         #power-domain-cells = <0>;
 683                                                 };
 684
 685                                                 power-domain@MT8195_POWER_DOMAIN_VENC {
 686                                                         reg = <MT8195_POWER_DOMAIN_VENC>;
 687                                                         mediatek,infracfg = <&infracfg_ao>;
 688                                                         #power-domain-cells = <0>;
 689                                                 };
 690
 691                                                 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
 692                                                         reg = <MT8195_POWER_DOMAIN_VDOSYS1>;
 693                                                         clocks = <&topckgen CLK_TOP_CFG_VDO1>,
 694                                                                  <&vdosys1 CLK_VDO1_SMI_LARB2>,
 695                                                                  <&vdosys1 CLK_VDO1_SMI_LARB3>,
 696                                                                  <&vdosys1 CLK_VDO1_GALS>;
 697                                                         clock-names = "vdosys1", "vdosys1-0",
 698                                                                       "vdosys1-1", "vdosys1-2";
 699                                                         mediatek,infracfg = <&infracfg_ao>;
 700                                                         #address-cells = <1>;
 701                                                         #size-cells = <0>;
 702                                                         #power-domain-cells = <1>;
 703
 704                                                         power-domain@MT8195_POWER_DOMAIN_DP_TX {
 705                                                                 reg = <MT8195_POWER_DOMAIN_DP_TX>;
 706                                                                 mediatek,infracfg = <&infracfg_ao>;
 707                                                                 #power-domain-cells = <0>;
 708                                                         };
 709
 710                                                         power-domain@MT8195_POWER_DOMAIN_EPD_TX {
 711                                                                 reg = <MT8195_POWER_DOMAIN_EPD_TX>;
 712                                                                 mediatek,infracfg = <&infracfg_ao>;
 713                                                                 #power-domain-cells = <0>;
 714                                                         };
 715
 716                                                         power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
 717                                                                 reg = <MT8195_POWER_DOMAIN_HDMI_TX>;
 718                                                                 clocks = <&topckgen CLK_TOP_HDMI_APB>;
 719                                                                 clock-names = "hdmi_tx";
 720                                                                 #power-domain-cells = <0>;
 721                                                         };
 722                                                 };
 723
 724                                                 power-domain@MT8195_POWER_DOMAIN_IMG {
 725                                                         reg = <MT8195_POWER_DOMAIN_IMG>;
 726                                                         clocks = <&imgsys CLK_IMG_LARB9>,
 727                                                                  <&imgsys CLK_IMG_GALS>;
 728                                                         clock-names = "img-0", "img-1";
 729                                                         mediatek,infracfg = <&infracfg_ao>;
 730                                                         #address-cells = <1>;
 731                                                         #size-cells = <0>;
 732                                                         #power-domain-cells = <1>;
 733
 734                                                         power-domain@MT8195_POWER_DOMAIN_DIP {
 735                                                                 reg = <MT8195_POWER_DOMAIN_DIP>;
 736                                                                 #power-domain-cells = <0>;
 737                                                         };
 738
 739                                                         power-domain@MT8195_POWER_DOMAIN_IPE {
 740                                                                 reg = <MT8195_POWER_DOMAIN_IPE>;
 741                                                                 clocks = <&topckgen CLK_TOP_IPE>,
 742                                                                          <&imgsys CLK_IMG_IPE>,
 743                                                                          <&ipesys CLK_IPE_SMI_LARB12>;
 744                                                                 clock-names = "ipe", "ipe-0", "ipe-1";
 745                                                                 mediatek,infracfg = <&infracfg_ao>;
 746                                                                 #power-domain-cells = <0>;
 747                                                         };
 748                                                 };
 749
 750                                                 power-domain@MT8195_POWER_DOMAIN_CAM {
 751                                                         reg = <MT8195_POWER_DOMAIN_CAM>;
 752                                                         clocks = <&camsys CLK_CAM_LARB13>,
 753                                                                  <&camsys CLK_CAM_LARB14>,
 754                                                                  <&camsys CLK_CAM_CAM2MM0_GALS>,
 755                                                                  <&camsys CLK_CAM_CAM2MM1_GALS>,
 756                                                                  <&camsys CLK_CAM_CAM2SYS_GALS>;
 757                                                         clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
 758                                                                       "cam-4";
 759                                                         mediatek,infracfg = <&infracfg_ao>;
 760                                                         #address-cells = <1>;
 761                                                         #size-cells = <0>;
 762                                                         #power-domain-cells = <1>;
 763
 764                                                         power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
 765                                                                 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>;
 766                                                                 #power-domain-cells = <0>;
 767                                                         };
 768
 769                                                         power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
 770                                                                 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>;
 771                                                                 #power-domain-cells = <0>;
 772                                                         };
 773
 774                                                         power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
 775                                                                 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>;
 776                                                                 #power-domain-cells = <0>;
 777                                                         };
 778                                                 };
 779                                         };
 780                                 };
 781
 782                                 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
 783                                         reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
 784                                         mediatek,infracfg = <&infracfg_ao>;
 785                                         #power-domain-cells = <0>;
 786                                 };
 787
 788                                 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
 789                                         reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
 790                                         mediatek,infracfg = <&infracfg_ao>;
 791                                         #power-domain-cells = <0>;
 792                                 };
 793
 794                                 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
 795                                         reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
 796                                         #power-domain-cells = <0>;
 797                                 };
 798
 799                                 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
 800                                         reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
 801                                         #power-domain-cells = <0>;
 802                                 };
 803
 804                                 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
 805                                         reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>;
 806                                         clocks = <&topckgen CLK_TOP_SENINF>,
 807                                                  <&topckgen CLK_TOP_SENINF2>;
 808                                         clock-names = "csi_rx_top", "csi_rx_top1";
 809                                         #power-domain-cells = <0>;
 810                                 };
 811
 812                                 power-domain@MT8195_POWER_DOMAIN_ETHER {
 813                                         reg = <MT8195_POWER_DOMAIN_ETHER>;
 814                                         clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
 815                                         clock-names = "ether";
 816                                         #power-domain-cells = <0>;
 817                                 };
 818
 819                                 power-domain@MT8195_POWER_DOMAIN_ADSP {
 820                                         reg = <MT8195_POWER_DOMAIN_ADSP>;
 821                                         clocks = <&topckgen CLK_TOP_ADSP>,
 822                                                  <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>;
 823                                         clock-names = "adsp", "adsp1";
 824                                         #address-cells = <1>;
 825                                         #size-cells = <0>;
 826                                         mediatek,infracfg = <&infracfg_ao>;
 827                                         #power-domain-cells = <1>;
 828
 829                                         power-domain@MT8195_POWER_DOMAIN_AUDIO {
 830                                                 reg = <MT8195_POWER_DOMAIN_AUDIO>;
 831                                                 clocks = <&topckgen CLK_TOP_A1SYS_HP>,
 832                                                          <&topckgen CLK_TOP_AUD_INTBUS>,
 833                                                          <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
 834                                                          <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>;
 835                                                 clock-names = "audio", "audio1", "audio2",
 836                                                               "audio3";
 837                                                 mediatek,infracfg = <&infracfg_ao>;
 838                                                 #power-domain-cells = <0>;
 839                                         };
 840                                 };
 841                         };
 842                 };
 843
 844                 watchdog: watchdog@10007000 {
 845                         compatible = "mediatek,mt8195-wdt";
 846                         mediatek,disable-extrst;
 847                         reg = <0 0x10007000 0 0x100>;
 848                         #reset-cells = <1>;
 849                 };
 850
 851                 apmixedsys: syscon@1000c000 {
 852                         compatible = "mediatek,mt8195-apmixedsys", "syscon";
 853                         reg = <0 0x1000c000 0 0x1000>;
 854                         #clock-cells = <1>;
 855                 };
 856
 857                 systimer: timer@10017000 {
 858                         compatible = "mediatek,mt8195-timer",
 859                                      "mediatek,mt6765-timer";
 860                         reg = <0 0x10017000 0 0x1000>;
 861                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
 862                         clocks = <&clk13m>;
 863                 };
 864
 865                 pwrap: pwrap@10024000 {
 866                         compatible = "mediatek,mt8195-pwrap", "syscon";
 867                         reg = <0 0x10024000 0 0x1000>;
 868                         reg-names = "pwrap";
 869                         interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
 870                         clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
 871                                  <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
 872                         clock-names = "spi", "wrap";
 873                         assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
 874                         assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
 875                 };
 876
 877                 spmi: spmi@10027000 {
 878                         compatible = "mediatek,mt8195-spmi";
 879                         reg = <0 0x10027000 0 0x000e00>,
 880                               <0 0x10029000 0 0x000100>;
 881                         reg-names = "pmif", "spmimst";
 882                         clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
 883                                  <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
 884                                  <&topckgen CLK_TOP_SPMI_M_MST>;
 885                         clock-names = "pmif_sys_ck",
 886                                       "pmif_tmr_ck",
 887                                       "spmimst_clk_mux";
 888                         assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
 889                         assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
 890                 };
 891
 892                 iommu_infra: infra-iommu@10315000 {
 893                         compatible = "mediatek,mt8195-iommu-infra";
 894                         reg = <0 0x10315000 0 0x5000>;
 895                         interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>,
 896                                      <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>,
 897                                      <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>,
 898                                      <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>,
 899                                      <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>;
 900                         #iommu-cells = <1>;
 901                 };
 902
 903                 gce0: mailbox@10320000 {
 904                         compatible = "mediatek,mt8195-gce";
 905                         reg = <0 0x10320000 0 0x4000>;
 906                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
 907                         #mbox-cells = <2>;
 908                         clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
 909                 };
 910
 911                 gce1: mailbox@10330000 {
 912                         compatible = "mediatek,mt8195-gce";
 913                         reg = <0 0x10330000 0 0x4000>;
 914                         interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
 915                         #mbox-cells = <2>;
 916                         clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
 917                 };
 918
 919                 scp: scp@10500000 {
 920                         compatible = "mediatek,mt8195-scp";
 921                         reg = <0 0x10500000 0 0x100000>,
 922                               <0 0x10720000 0 0xe0000>,
 923                               <0 0x10700000 0 0x8000>;
 924                         reg-names = "sram", "cfg", "l1tcm";
 925                         interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
 926                         status = "disabled";
 927                 };
 928
 929                 scp_adsp: clock-controller@10720000 {
 930                         compatible = "mediatek,mt8195-scp_adsp";
 931                         reg = <0 0x10720000 0 0x1000>;
 932                         #clock-cells = <1>;
 933                 };
 934
 935                 adsp: dsp@10803000 {
 936                         compatible = "mediatek,mt8195-dsp";
 937                         reg = <0 0x10803000 0 0x1000>,
 938                               <0 0x10840000 0 0x40000>;
 939                         reg-names = "cfg", "sram";
 940                         clocks = <&topckgen CLK_TOP_ADSP>,
 941                                  <&clk26m>,
 942                                  <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
 943                                  <&topckgen CLK_TOP_MAINPLL_D7_D2>,
 944                                  <&scp_adsp CLK_SCP_ADSP_AUDIODSP>,
 945                                  <&topckgen CLK_TOP_AUDIO_H>;
 946                         clock-names = "adsp_sel",
 947                                  "clk26m_ck",
 948                                  "audio_local_bus",
 949                                  "mainpll_d7_d2",
 950                                  "scp_adsp_audiodsp",
 951                                  "audio_h";
 952                         power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
 953                         mbox-names = "rx", "tx";
 954                         mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
 955                         status = "disabled";
 956                 };
 957
 958                 adsp_mailbox0: mailbox@10816000 {
 959                         compatible = "mediatek,mt8195-adsp-mbox";
 960                         #mbox-cells = <0>;
 961                         reg = <0 0x10816000 0 0x1000>;
 962                         interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>;
 963                 };
 964
 965                 adsp_mailbox1: mailbox@10817000 {
 966                         compatible = "mediatek,mt8195-adsp-mbox";
 967                         #mbox-cells = <0>;
 968                         reg = <0 0x10817000 0 0x1000>;
 969                         interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>;
 970                 };
 971
 972                 afe: mt8195-afe-pcm@10890000 {
 973                         compatible = "mediatek,mt8195-audio";
 974                         reg = <0 0x10890000 0 0x10000>;
 975                         mediatek,topckgen = <&topckgen>;
 976                         power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
 977                         interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
 978                         resets = <&watchdog 14>;
 979                         reset-names = "audiosys";
 980                         clocks = <&clk26m>,
 981                                 <&apmixedsys CLK_APMIXED_APLL1>,
 982                                 <&apmixedsys CLK_APMIXED_APLL2>,
 983                                 <&topckgen CLK_TOP_APLL12_DIV0>,
 984                                 <&topckgen CLK_TOP_APLL12_DIV1>,
 985                                 <&topckgen CLK_TOP_APLL12_DIV2>,
 986                                 <&topckgen CLK_TOP_APLL12_DIV3>,
 987                                 <&topckgen CLK_TOP_APLL12_DIV9>,
 988                                 <&topckgen CLK_TOP_A1SYS_HP>,
 989                                 <&topckgen CLK_TOP_AUD_INTBUS>,
 990                                 <&topckgen CLK_TOP_AUDIO_H>,
 991                                 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
 992                                 <&topckgen CLK_TOP_DPTX_MCK>,
 993                                 <&topckgen CLK_TOP_I2SO1_MCK>,
 994                                 <&topckgen CLK_TOP_I2SO2_MCK>,
 995                                 <&topckgen CLK_TOP_I2SI1_MCK>,
 996                                 <&topckgen CLK_TOP_I2SI2_MCK>,
 997                                 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>,
 998                                 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>;
 999                         clock-names = "clk26m",
1000                                 "apll1_ck",
1001                                 "apll2_ck",
1002                                 "apll12_div0",
1003                                 "apll12_div1",
1004                                 "apll12_div2",
1005                                 "apll12_div3",
1006                                 "apll12_div9",
1007                                 "a1sys_hp_sel",
1008                                 "aud_intbus_sel",
1009                                 "audio_h_sel",
1010                                 "audio_local_bus_sel",
1011                                 "dptx_m_sel",
1012                                 "i2so1_m_sel",
1013                                 "i2so2_m_sel",
1014                                 "i2si1_m_sel",
1015                                 "i2si2_m_sel",
1016                                 "infra_ao_audio_26m_b",
1017                                 "scp_adsp_audiodsp";
1018                         status = "disabled";
1019                 };
1020
1021                 uart0: serial@11001100 {
1022                         compatible = "mediatek,mt8195-uart",
1023                                      "mediatek,mt6577-uart";
1024                         reg = <0 0x11001100 0 0x100>;
1025                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
1026                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
1027                         clock-names = "baud", "bus";
1028                         status = "disabled";
1029                 };
1030
1031                 uart1: serial@11001200 {
1032                         compatible = "mediatek,mt8195-uart",
1033                                      "mediatek,mt6577-uart";
1034                         reg = <0 0x11001200 0 0x100>;
1035                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
1036                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
1037                         clock-names = "baud", "bus";
1038                         status = "disabled";
1039                 };
1040
1041                 uart2: serial@11001300 {
1042                         compatible = "mediatek,mt8195-uart",
1043                                      "mediatek,mt6577-uart";
1044                         reg = <0 0x11001300 0 0x100>;
1045                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
1046                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
1047                         clock-names = "baud", "bus";
1048                         status = "disabled";
1049                 };
1050
1051                 uart3: serial@11001400 {
1052                         compatible = "mediatek,mt8195-uart",
1053                                      "mediatek,mt6577-uart";
1054                         reg = <0 0x11001400 0 0x100>;
1055                         interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
1056                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
1057                         clock-names = "baud", "bus";
1058                         status = "disabled";
1059                 };
1060
1061                 uart4: serial@11001500 {
1062                         compatible = "mediatek,mt8195-uart",
1063                                      "mediatek,mt6577-uart";
1064                         reg = <0 0x11001500 0 0x100>;
1065                         interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>;
1066                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>;
1067                         clock-names = "baud", "bus";
1068                         status = "disabled";
1069                 };
1070
1071                 uart5: serial@11001600 {
1072                         compatible = "mediatek,mt8195-uart",
1073                                      "mediatek,mt6577-uart";
1074                         reg = <0 0x11001600 0 0x100>;
1075                         interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>;
1076                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>;
1077                         clock-names = "baud", "bus";
1078                         status = "disabled";
1079                 };
1080
1081                 auxadc: auxadc@11002000 {
1082                         compatible = "mediatek,mt8195-auxadc",
1083                                      "mediatek,mt8173-auxadc";
1084                         reg = <0 0x11002000 0 0x1000>;
1085                         clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
1086                         clock-names = "main";
1087                         #io-channel-cells = <1>;
1088                         status = "disabled";
1089                 };
1090
1091                 pericfg_ao: syscon@11003000 {
1092                         compatible = "mediatek,mt8195-pericfg_ao", "syscon";
1093                         reg = <0 0x11003000 0 0x1000>;
1094                         #clock-cells = <1>;
1095                 };
1096
1097                 spi0: spi@1100a000 {
1098                         compatible = "mediatek,mt8195-spi",
1099                                      "mediatek,mt6765-spi";
1100                         #address-cells = <1>;
1101                         #size-cells = <0>;
1102                         reg = <0 0x1100a000 0 0x1000>;
1103                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
1104                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1105                                  <&topckgen CLK_TOP_SPI>,
1106                                  <&infracfg_ao CLK_INFRA_AO_SPI0>;
1107                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1108                         status = "disabled";
1109                 };
1110
1111                 lvts_ap: thermal-sensor@1100b000 {
1112                         compatible = "mediatek,mt8195-lvts-ap";
1113                         reg = <0 0x1100b000 0 0x1000>;
1114                         interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
1115                         clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1116                         resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>;
1117                         nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1118                         nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1119                         #thermal-sensor-cells = <1>;
1120                 };
1121
1122                 disp_pwm0: pwm@1100e000 {
1123                         compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1124                         reg = <0 0x1100e000 0 0x1000>;
1125                         interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0>;
1126                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
1127                         #pwm-cells = <2>;
1128                         clocks = <&topckgen CLK_TOP_DISP_PWM0>,
1129                                  <&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
1130                         clock-names = "main", "mm";
1131                         status = "disabled";
1132                 };
1133
1134                 disp_pwm1: pwm@1100f000 {
1135                         compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1136                         reg = <0 0x1100f000 0 0x1000>;
1137                         interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>;
1138                         #pwm-cells = <2>;
1139                         clocks = <&topckgen CLK_TOP_DISP_PWM1>,
1140                                  <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>;
1141                         clock-names = "main", "mm";
1142                         status = "disabled";
1143                 };
1144
1145                 spi1: spi@11010000 {
1146                         compatible = "mediatek,mt8195-spi",
1147                                      "mediatek,mt6765-spi";
1148                         #address-cells = <1>;
1149                         #size-cells = <0>;
1150                         reg = <0 0x11010000 0 0x1000>;
1151                         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
1152                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1153                                  <&topckgen CLK_TOP_SPI>,
1154                                  <&infracfg_ao CLK_INFRA_AO_SPI1>;
1155                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1156                         status = "disabled";
1157                 };
1158
1159                 spi2: spi@11012000 {
1160                         compatible = "mediatek,mt8195-spi",
1161                                      "mediatek,mt6765-spi";
1162                         #address-cells = <1>;
1163                         #size-cells = <0>;
1164                         reg = <0 0x11012000 0 0x1000>;
1165                         interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
1166                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1167                                  <&topckgen CLK_TOP_SPI>,
1168                                  <&infracfg_ao CLK_INFRA_AO_SPI2>;
1169                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1170                         status = "disabled";
1171                 };
1172
1173                 spi3: spi@11013000 {
1174                         compatible = "mediatek,mt8195-spi",
1175                                      "mediatek,mt6765-spi";
1176                         #address-cells = <1>;
1177                         #size-cells = <0>;
1178                         reg = <0 0x11013000 0 0x1000>;
1179                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
1180                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1181                                  <&topckgen CLK_TOP_SPI>,
1182                                  <&infracfg_ao CLK_INFRA_AO_SPI3>;
1183                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1184                         status = "disabled";
1185                 };
1186
1187                 spi4: spi@11018000 {
1188                         compatible = "mediatek,mt8195-spi",
1189                                      "mediatek,mt6765-spi";
1190                         #address-cells = <1>;
1191                         #size-cells = <0>;
1192                         reg = <0 0x11018000 0 0x1000>;
1193                         interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
1194                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1195                                  <&topckgen CLK_TOP_SPI>,
1196                                  <&infracfg_ao CLK_INFRA_AO_SPI4>;
1197                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1198                         status = "disabled";
1199                 };
1200
1201                 spi5: spi@11019000 {
1202                         compatible = "mediatek,mt8195-spi",
1203                                      "mediatek,mt6765-spi";
1204                         #address-cells = <1>;
1205                         #size-cells = <0>;
1206                         reg = <0 0x11019000 0 0x1000>;
1207                         interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
1208                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1209                                  <&topckgen CLK_TOP_SPI>,
1210                                  <&infracfg_ao CLK_INFRA_AO_SPI5>;
1211                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1212                         status = "disabled";
1213                 };
1214
1215                 spis0: spi@1101d000 {
1216                         compatible = "mediatek,mt8195-spi-slave";
1217                         reg = <0 0x1101d000 0 0x1000>;
1218                         interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
1219                         clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>;
1220                         clock-names = "spi";
1221                         assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1222                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1223                         status = "disabled";
1224                 };
1225
1226                 spis1: spi@1101e000 {
1227                         compatible = "mediatek,mt8195-spi-slave";
1228                         reg = <0 0x1101e000 0 0x1000>;
1229                         interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
1230                         clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
1231                         clock-names = "spi";
1232                         assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1233                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1234                         status = "disabled";
1235                 };
1236
1237                 eth: ethernet@11021000 {
1238                         compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";
1239                         reg = <0 0x11021000 0 0x4000>;
1240                         interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>;
1241                         interrupt-names = "macirq";
1242                         clock-names = "axi",
1243                                       "apb",
1244                                       "mac_main",
1245                                       "ptp_ref",
1246                                       "rmii_internal",
1247                                       "mac_cg";
1248                         clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>,
1249                                  <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>,
1250                                  <&topckgen CLK_TOP_SNPS_ETH_250M>,
1251                                  <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1252                                  <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>,
1253                                  <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
1254                         assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1255                                           <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1256                                           <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
1257                         assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1258                                                  <&topckgen CLK_TOP_ETHPLL_D8>,
1259                                                  <&topckgen CLK_TOP_ETHPLL_D10>;
1260                         power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
1261                         mediatek,pericfg = <&infracfg_ao>;
1262                         snps,axi-config = <&stmmac_axi_setup>;
1263                         snps,mtl-rx-config = <&mtl_rx_setup>;
1264                         snps,mtl-tx-config = <&mtl_tx_setup>;
1265                         snps,txpbl = <16>;
1266                         snps,rxpbl = <16>;
1267                         snps,clk-csr = <0>;
1268                         status = "disabled";
1269
1270                         mdio {
1271                                 compatible = "snps,dwmac-mdio";
1272                                 #address-cells = <1>;
1273                                 #size-cells = <0>;
1274                         };
1275
1276                         stmmac_axi_setup: stmmac-axi-config {
1277                                 snps,wr_osr_lmt = <0x7>;
1278                                 snps,rd_osr_lmt = <0x7>;
1279                                 snps,blen = <0 0 0 0 16 8 4>;
1280                         };
1281
1282                         mtl_rx_setup: rx-queues-config {
1283                                 snps,rx-queues-to-use = <4>;
1284                                 snps,rx-sched-sp;
1285                                 queue0 {
1286                                         snps,dcb-algorithm;
1287                                         snps,map-to-dma-channel = <0x0>;
1288                                 };
1289                                 queue1 {
1290                                         snps,dcb-algorithm;
1291                                         snps,map-to-dma-channel = <0x0>;
1292                                 };
1293                                 queue2 {
1294                                         snps,dcb-algorithm;
1295                                         snps,map-to-dma-channel = <0x0>;
1296                                 };
1297                                 queue3 {
1298                                         snps,dcb-algorithm;
1299                                         snps,map-to-dma-channel = <0x0>;
1300                                 };
1301                         };
1302
1303                         mtl_tx_setup: tx-queues-config {
1304                                 snps,tx-queues-to-use = <4>;
1305                                 snps,tx-sched-wrr;
1306                                 queue0 {
1307                                         snps,weight = <0x10>;
1308                                         snps,dcb-algorithm;
1309                                         snps,priority = <0x0>;
1310                                 };
1311                                 queue1 {
1312                                         snps,weight = <0x11>;
1313                                         snps,dcb-algorithm;
1314                                         snps,priority = <0x1>;
1315                                 };
1316                                 queue2 {
1317                                         snps,weight = <0x12>;
1318                                         snps,dcb-algorithm;
1319                                         snps,priority = <0x2>;
1320                                 };
1321                                 queue3 {
1322                                         snps,weight = <0x13>;
1323                                         snps,dcb-algorithm;
1324                                         snps,priority = <0x3>;
1325                                 };
1326                         };
1327                 };
1328
1329                 xhci0: usb@11200000 {
1330                         compatible = "mediatek,mt8195-xhci",
1331                                      "mediatek,mtk-xhci";
1332                         reg = <0 0x11200000 0 0x1000>,
1333                               <0 0x11203e00 0 0x0100>;
1334                         reg-names = "mac", "ippc";
1335                         interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
1336                         phys = <&u2port0 PHY_TYPE_USB2>,
1337                                <&u3port0 PHY_TYPE_USB3>;
1338                         assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
1339                                           <&topckgen CLK_TOP_SSUSB_XHCI>;
1340                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1341                                                  <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1342                         clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
1343                                  <&topckgen CLK_TOP_SSUSB_REF>,
1344                                  <&apmixedsys CLK_APMIXED_USB1PLL>,
1345                                  <&clk26m>,
1346                                  <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
1347                         clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1348                                       "xhci_ck";
1349                         mediatek,syscon-wakeup = <&pericfg 0x400 103>;
1350                         wakeup-source;
1351                         status = "disabled";
1352                 };
1353
1354                 mmc0: mmc@11230000 {
1355                         compatible = "mediatek,mt8195-mmc",
1356                                      "mediatek,mt8183-mmc";
1357                         reg = <0 0x11230000 0 0x10000>,
1358                               <0 0x11f50000 0 0x1000>;
1359                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
1360                         clocks = <&topckgen CLK_TOP_MSDC50_0>,
1361                                  <&infracfg_ao CLK_INFRA_AO_MSDC0>,
1362                                  <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
1363                         clock-names = "source", "hclk", "source_cg";
1364                         status = "disabled";
1365                 };
1366
1367                 mmc1: mmc@11240000 {
1368                         compatible = "mediatek,mt8195-mmc",
1369                                      "mediatek,mt8183-mmc";
1370                         reg = <0 0x11240000 0 0x1000>,
1371                               <0 0x11c70000 0 0x1000>;
1372                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
1373                         clocks = <&topckgen CLK_TOP_MSDC30_1>,
1374                                  <&infracfg_ao CLK_INFRA_AO_MSDC1>,
1375                                  <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
1376                         clock-names = "source", "hclk", "source_cg";
1377                         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1378                         assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1379                         status = "disabled";
1380                 };
1381
1382                 mmc2: mmc@11250000 {
1383                         compatible = "mediatek,mt8195-mmc",
1384                                      "mediatek,mt8183-mmc";
1385                         reg = <0 0x11250000 0 0x1000>,
1386                               <0 0x11e60000 0 0x1000>;
1387                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
1388                         clocks = <&topckgen CLK_TOP_MSDC30_2>,
1389                                  <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>,
1390                                  <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>;
1391                         clock-names = "source", "hclk", "source_cg";
1392                         assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1393                         assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1394                         status = "disabled";
1395                 };
1396
1397                 lvts_mcu: thermal-sensor@11278000 {
1398                         compatible = "mediatek,mt8195-lvts-mcu";
1399                         reg = <0 0x11278000 0 0x1000>;
1400                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
1401                         clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1402                         resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
1403                         nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1404                         nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1405                         #thermal-sensor-cells = <1>;
1406                 };
1407
1408                 xhci1: usb@11290000 {
1409                         compatible = "mediatek,mt8195-xhci",
1410                                      "mediatek,mtk-xhci";
1411                         reg = <0 0x11290000 0 0x1000>,
1412                               <0 0x11293e00 0 0x0100>;
1413                         reg-names = "mac", "ippc";
1414                         interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
1415                         phys = <&u2port1 PHY_TYPE_USB2>;
1416                         assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1417                                           <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
1418                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1419                                                  <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1420                         clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
1421                                  <&topckgen CLK_TOP_SSUSB_P1_REF>,
1422                                  <&apmixedsys CLK_APMIXED_USB1PLL>,
1423                                  <&clk26m>,
1424                                  <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>;
1425                         clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1426                                       "xhci_ck";
1427                         mediatek,syscon-wakeup = <&pericfg 0x400 104>;
1428                         wakeup-source;
1429                         status = "disabled";
1430                 };
1431
1432                 xhci2: usb@112a0000 {
1433                         compatible = "mediatek,mt8195-xhci",
1434                                      "mediatek,mtk-xhci";
1435                         reg = <0 0x112a0000 0 0x1000>,
1436                               <0 0x112a3e00 0 0x0100>;
1437                         reg-names = "mac", "ippc";
1438                         interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
1439                         phys = <&u2port2 PHY_TYPE_USB2>;
1440                         assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
1441                                           <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
1442                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1443                                                  <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1444                         clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
1445                                  <&topckgen CLK_TOP_SSUSB_P2_REF>,
1446                                  <&clk26m>,
1447                                  <&clk26m>,
1448                                  <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
1449                         clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1450                                       "xhci_ck";
1451                         mediatek,syscon-wakeup = <&pericfg 0x400 105>;
1452                         wakeup-source;
1453                         status = "disabled";
1454                 };
1455
1456                 xhci3: usb@112b0000 {
1457                         compatible = "mediatek,mt8195-xhci",
1458                                      "mediatek,mtk-xhci";
1459                         reg = <0 0x112b0000 0 0x1000>,
1460                               <0 0x112b3e00 0 0x0100>;
1461                         reg-names = "mac", "ippc";
1462                         interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
1463                         phys = <&u2port3 PHY_TYPE_USB2>;
1464                         assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
1465                                           <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
1466                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1467                                                  <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1468                         clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
1469                                  <&topckgen CLK_TOP_SSUSB_P3_REF>,
1470                                  <&clk26m>,
1471                                  <&clk26m>,
1472                                  <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
1473                         clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1474                                       "xhci_ck";
1475                         mediatek,syscon-wakeup = <&pericfg 0x400 106>;
1476                         wakeup-source;
1477                         status = "disabled";
1478                 };
1479
1480                 pcie0: pcie@112f0000 {
1481                         compatible = "mediatek,mt8195-pcie",
1482                                      "mediatek,mt8192-pcie";
1483                         device_type = "pci";
1484                         #address-cells = <3>;
1485                         #size-cells = <2>;
1486                         reg = <0 0x112f0000 0 0x4000>;
1487                         reg-names = "pcie-mac";
1488                         interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>;
1489                         bus-range = <0x00 0xff>;
1490                         ranges = <0x81000000 0 0x20000000
1491                                   0x0 0x20000000 0 0x200000>,
1492                                  <0x82000000 0 0x20200000
1493                                   0x0 0x20200000 0 0x3e00000>;
1494
1495                         iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>;
1496                         iommu-map-mask = <0x0>;
1497
1498                         clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>,
1499                                  <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>,
1500                                  <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
1501                                  <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>,
1502                                  <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
1503                                  <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
1504                         clock-names = "pl_250m", "tl_26m", "tl_96m",
1505                                       "tl_32k", "peri_26m", "peri_mem";
1506                         assigned-clocks = <&topckgen CLK_TOP_TL>;
1507                         assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1508
1509                         phys = <&pciephy>;
1510                         phy-names = "pcie-phy";
1511
1512                         power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
1513
1514                         resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>;
1515                         reset-names = "mac";
1516
1517                         #interrupt-cells = <1>;
1518                         interrupt-map-mask = <0 0 0 7>;
1519                         interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1520                                         <0 0 0 2 &pcie_intc0 1>,
1521                                         <0 0 0 3 &pcie_intc0 2>,
1522                                         <0 0 0 4 &pcie_intc0 3>;
1523                         status = "disabled";
1524
1525                         pcie_intc0: interrupt-controller {
1526                                 interrupt-controller;
1527                                 #address-cells = <0>;
1528                                 #interrupt-cells = <1>;
1529                         };
1530                 };
1531
1532                 pcie1: pcie@112f8000 {
1533                         compatible = "mediatek,mt8195-pcie",
1534                                      "mediatek,mt8192-pcie";
1535                         device_type = "pci";
1536                         #address-cells = <3>;
1537                         #size-cells = <2>;
1538                         reg = <0 0x112f8000 0 0x4000>;
1539                         reg-names = "pcie-mac";
1540                         interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>;
1541                         bus-range = <0x00 0xff>;
1542                         ranges = <0x81000000 0 0x24000000
1543                                   0x0 0x24000000 0 0x200000>,
1544                                  <0x82000000 0 0x24200000
1545                                   0x0 0x24200000 0 0x3e00000>;
1546
1547                         iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
1548                         iommu-map-mask = <0x0>;
1549
1550                         clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>,
1551                                  <&clk26m>,
1552                                  <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>,
1553                                  <&clk26m>,
1554                                  <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>,
1555                                  /* Designer has connect pcie1 with peri_mem_p0 clock */
1556                                  <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
1557                         clock-names = "pl_250m", "tl_26m", "tl_96m",
1558                                       "tl_32k", "peri_26m", "peri_mem";
1559                         assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
1560                         assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1561
1562                         phys = <&u3port1 PHY_TYPE_PCIE>;
1563                         phy-names = "pcie-phy";
1564                         power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
1565
1566                         resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>;
1567                         reset-names = "mac";
1568
1569                         #interrupt-cells = <1>;
1570                         interrupt-map-mask = <0 0 0 7>;
1571                         interrupt-map = <0 0 0 1 &pcie_intc1 0>,
1572                                         <0 0 0 2 &pcie_intc1 1>,
1573                                         <0 0 0 3 &pcie_intc1 2>,
1574                                         <0 0 0 4 &pcie_intc1 3>;
1575                         status = "disabled";
1576
1577                         pcie_intc1: interrupt-controller {
1578                                 interrupt-controller;
1579                                 #address-cells = <0>;
1580                                 #interrupt-cells = <1>;
1581                         };
1582                 };
1583
1584                 nor_flash: spi@1132c000 {
1585                         compatible = "mediatek,mt8195-nor",
1586                                      "mediatek,mt8173-nor";
1587                         reg = <0 0x1132c000 0 0x1000>;
1588                         interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
1589                         clocks = <&topckgen CLK_TOP_SPINOR>,
1590                                  <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>,
1591                                  <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
1592                         clock-names = "spi", "sf", "axi";
1593                         #address-cells = <1>;
1594                         #size-cells = <0>;
1595                         status = "disabled";
1596                 };
1597
1598                 efuse: efuse@11c10000 {
1599                         compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
1600                         reg = <0 0x11c10000 0 0x1000>;
1601                         #address-cells = <1>;
1602                         #size-cells = <1>;
1603                         u3_tx_imp_p0: usb3-tx-imp@184,1 {
1604                                 reg = <0x184 0x1>;
1605                                 bits = <0 5>;
1606                         };
1607                         u3_rx_imp_p0: usb3-rx-imp@184,2 {
1608                                 reg = <0x184 0x2>;
1609                                 bits = <5 5>;
1610                         };
1611                         u3_intr_p0: usb3-intr@185 {
1612                                 reg = <0x185 0x1>;
1613                                 bits = <2 6>;
1614                         };
1615                         comb_tx_imp_p1: usb3-tx-imp@186,1 {
1616                                 reg = <0x186 0x1>;
1617                                 bits = <0 5>;
1618                         };
1619                         comb_rx_imp_p1: usb3-rx-imp@186,2 {
1620                                 reg = <0x186 0x2>;
1621                                 bits = <5 5>;
1622                         };
1623                         comb_intr_p1: usb3-intr@187 {
1624                                 reg = <0x187 0x1>;
1625                                 bits = <2 6>;
1626                         };
1627                         u2_intr_p0: usb2-intr-p0@188,1 {
1628                                 reg = <0x188 0x1>;
1629                                 bits = <0 5>;
1630                         };
1631                         u2_intr_p1: usb2-intr-p1@188,2 {
1632                                 reg = <0x188 0x2>;
1633                                 bits = <5 5>;
1634                         };
1635                         u2_intr_p2: usb2-intr-p2@189,1 {
1636                                 reg = <0x189 0x1>;
1637                                 bits = <2 5>;
1638                         };
1639                         u2_intr_p3: usb2-intr-p3@189,2 {
1640                                 reg = <0x189 0x2>;
1641                                 bits = <7 5>;
1642                         };
1643                         pciephy_rx_ln1: pciephy-rx-ln1@190,1 {
1644                                 reg = <0x190 0x1>;
1645                                 bits = <0 4>;
1646                         };
1647                         pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 {
1648                                 reg = <0x190 0x1>;
1649                                 bits = <4 4>;
1650                         };
1651                         pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {
1652                                 reg = <0x191 0x1>;
1653                                 bits = <0 4>;
1654                         };
1655                         pciephy_rx_ln0: pciephy-rx-ln0@191,2 {
1656                                 reg = <0x191 0x1>;
1657                                 bits = <4 4>;
1658                         };
1659                         pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {
1660                                 reg = <0x192 0x1>;
1661                                 bits = <0 4>;
1662                         };
1663                         pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 {
1664                                 reg = <0x192 0x1>;
1665                                 bits = <4 4>;
1666                         };
1667                         pciephy_glb_intr: pciephy-glb-intr@193 {
1668                                 reg = <0x193 0x1>;
1669                                 bits = <0 4>;
1670                         };
1671                         dp_calibration: dp-data@1ac {
1672                                 reg = <0x1ac 0x10>;
1673                         };
1674                         lvts_efuse_data1: lvts1-calib@1bc {
1675                                 reg = <0x1bc 0x14>;
1676                         };
1677                         lvts_efuse_data2: lvts2-calib@1d0 {
1678                                 reg = <0x1d0 0x38>;
1679                         };
1680                 };
1681
1682                 u3phy2: t-phy@11c40000 {
1683                         compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1684                         #address-cells = <1>;
1685                         #size-cells = <1>;
1686                         ranges = <0 0 0x11c40000 0x700>;
1687                         status = "disabled";
1688
1689                         u2port2: usb-phy@0 {
1690                                 reg = <0x0 0x700>;
1691                                 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>;
1692                                 clock-names = "ref";
1693                                 #phy-cells = <1>;
1694                         };
1695                 };
1696
1697                 u3phy3: t-phy@11c50000 {
1698                         compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1699                         #address-cells = <1>;
1700                         #size-cells = <1>;
1701                         ranges = <0 0 0x11c50000 0x700>;
1702                         status = "disabled";
1703
1704                         u2port3: usb-phy@0 {
1705                                 reg = <0x0 0x700>;
1706                                 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>;
1707                                 clock-names = "ref";
1708                                 #phy-cells = <1>;
1709                         };
1710                 };
1711
1712                 i2c5: i2c@11d00000 {
1713                         compatible = "mediatek,mt8195-i2c",
1714                                      "mediatek,mt8192-i2c";
1715                         reg = <0 0x11d00000 0 0x1000>,
1716                               <0 0x10220580 0 0x80>;
1717                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>;
1718                         clock-div = <1>;
1719                         clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>,
1720                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1721                         clock-names = "main", "dma";
1722                         #address-cells = <1>;
1723                         #size-cells = <0>;
1724                         status = "disabled";
1725                 };
1726
1727                 i2c6: i2c@11d01000 {
1728                         compatible = "mediatek,mt8195-i2c",
1729                                      "mediatek,mt8192-i2c";
1730                         reg = <0 0x11d01000 0 0x1000>,
1731                               <0 0x10220600 0 0x80>;
1732                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
1733                         clock-div = <1>;
1734                         clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>,
1735                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1736                         clock-names = "main", "dma";
1737                         #address-cells = <1>;
1738                         #size-cells = <0>;
1739                         status = "disabled";
1740                 };
1741
1742                 i2c7: i2c@11d02000 {
1743                         compatible = "mediatek,mt8195-i2c",
1744                                      "mediatek,mt8192-i2c";
1745                         reg = <0 0x11d02000 0 0x1000>,
1746                               <0 0x10220680 0 0x80>;
1747                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
1748                         clock-div = <1>;
1749                         clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
1750                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1751                         clock-names = "main", "dma";
1752                         #address-cells = <1>;
1753                         #size-cells = <0>;
1754                         status = "disabled";
1755                 };
1756
1757                 imp_iic_wrap_s: clock-controller@11d03000 {
1758                         compatible = "mediatek,mt8195-imp_iic_wrap_s";
1759                         reg = <0 0x11d03000 0 0x1000>;
1760                         #clock-cells = <1>;
1761                 };
1762
1763                 i2c0: i2c@11e00000 {
1764                         compatible = "mediatek,mt8195-i2c",
1765                                      "mediatek,mt8192-i2c";
1766                         reg = <0 0x11e00000 0 0x1000>,
1767                               <0 0x10220080 0 0x80>;
1768                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>;
1769                         clock-div = <1>;
1770                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>,
1771                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1772                         clock-names = "main", "dma";
1773                         #address-cells = <1>;
1774                         #size-cells = <0>;
1775                         status = "disabled";
1776                 };
1777
1778                 i2c1: i2c@11e01000 {
1779                         compatible = "mediatek,mt8195-i2c",
1780                                      "mediatek,mt8192-i2c";
1781                         reg = <0 0x11e01000 0 0x1000>,
1782                               <0 0x10220200 0 0x80>;
1783                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
1784                         clock-div = <1>;
1785                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>,
1786                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1787                         clock-names = "main", "dma";
1788                         #address-cells = <1>;
1789                         #size-cells = <0>;
1790                         status = "disabled";
1791                 };
1792
1793                 i2c2: i2c@11e02000 {
1794                         compatible = "mediatek,mt8195-i2c",
1795                                      "mediatek,mt8192-i2c";
1796                         reg = <0 0x11e02000 0 0x1000>,
1797                               <0 0x10220380 0 0x80>;
1798                         interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
1799                         clock-div = <1>;
1800                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>,
1801                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1802                         clock-names = "main", "dma";
1803                         #address-cells = <1>;
1804                         #size-cells = <0>;
1805                         status = "disabled";
1806                 };
1807
1808                 i2c3: i2c@11e03000 {
1809                         compatible = "mediatek,mt8195-i2c",
1810                                      "mediatek,mt8192-i2c";
1811                         reg = <0 0x11e03000 0 0x1000>,
1812                               <0 0x10220480 0 0x80>;
1813                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
1814                         clock-div = <1>;
1815                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>,
1816                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1817                         clock-names = "main", "dma";
1818                         #address-cells = <1>;
1819                         #size-cells = <0>;
1820                         status = "disabled";
1821                 };
1822
1823                 i2c4: i2c@11e04000 {
1824                         compatible = "mediatek,mt8195-i2c",
1825                                      "mediatek,mt8192-i2c";
1826                         reg = <0 0x11e04000 0 0x1000>,
1827                               <0 0x10220500 0 0x80>;
1828                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>;
1829                         clock-div = <1>;
1830                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>,
1831                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1832                         clock-names = "main", "dma";
1833                         #address-cells = <1>;
1834                         #size-cells = <0>;
1835                         status = "disabled";
1836                 };
1837
1838                 imp_iic_wrap_w: clock-controller@11e05000 {
1839                         compatible = "mediatek,mt8195-imp_iic_wrap_w";
1840                         reg = <0 0x11e05000 0 0x1000>;
1841                         #clock-cells = <1>;
1842                 };
1843
1844                 u3phy1: t-phy@11e30000 {
1845                         compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1846                         #address-cells = <1>;
1847                         #size-cells = <1>;
1848                         ranges = <0 0 0x11e30000 0xe00>;
1849                         power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
1850                         status = "disabled";
1851
1852                         u2port1: usb-phy@0 {
1853                                 reg = <0x0 0x700>;
1854                                 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
1855                                          <&clk26m>;
1856                                 clock-names = "ref", "da_ref";
1857                                 #phy-cells = <1>;
1858                         };
1859
1860                         u3port1: usb-phy@700 {
1861                                 reg = <0x700 0x700>;
1862                                 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
1863                                          <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
1864                                 clock-names = "ref", "da_ref";
1865                                 nvmem-cells = <&comb_intr_p1>,
1866                                               <&comb_rx_imp_p1>,
1867                                               <&comb_tx_imp_p1>;
1868                                 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1869                                 #phy-cells = <1>;
1870                         };
1871                 };
1872
1873                 u3phy0: t-phy@11e40000 {
1874                         compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1875                         #address-cells = <1>;
1876                         #size-cells = <1>;
1877                         ranges = <0 0 0x11e40000 0xe00>;
1878                         status = "disabled";
1879
1880                         u2port0: usb-phy@0 {
1881                                 reg = <0x0 0x700>;
1882                                 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
1883                                          <&clk26m>;
1884                                 clock-names = "ref", "da_ref";
1885                                 #phy-cells = <1>;
1886                         };
1887
1888                         u3port0: usb-phy@700 {
1889                                 reg = <0x700 0x700>;
1890                                 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
1891                                          <&topckgen CLK_TOP_SSUSB_PHY_REF>;
1892                                 clock-names = "ref", "da_ref";
1893                                 nvmem-cells = <&u3_intr_p0>,
1894                                               <&u3_rx_imp_p0>,
1895                                               <&u3_tx_imp_p0>;
1896                                 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1897                                 #phy-cells = <1>;
1898                         };
1899                 };
1900
1901                 pciephy: phy@11e80000 {
1902                         compatible = "mediatek,mt8195-pcie-phy";
1903                         reg = <0 0x11e80000 0 0x10000>;
1904                         reg-names = "sif";
1905                         nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>,
1906                                       <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>,
1907                                       <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>,
1908                                       <&pciephy_rx_ln1>;
1909                         nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
1910                                            "tx_ln0_nmos", "rx_ln0",
1911                                            "tx_ln1_pmos", "tx_ln1_nmos",
1912                                            "rx_ln1";
1913                         power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>;
1914                         #phy-cells = <0>;
1915                         status = "disabled";
1916                 };
1917
1918                 ufsphy: ufs-phy@11fa0000 {
1919                         compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
1920                         reg = <0 0x11fa0000 0 0xc000>;
1921                         clocks = <&clk26m>, <&clk26m>;
1922                         clock-names = "unipro", "mp";
1923                         #phy-cells = <0>;
1924                         status = "disabled";
1925                 };
1926
1927                 gpu: gpu@13000000 {
1928                         compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali",
1929                                      "arm,mali-valhall-jm";
1930                         reg = <0 0x13000000 0 0x4000>;
1931
1932                         clocks = <&mfgcfg CLK_MFG_BG3D>;
1933                         interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>,
1934                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>,
1935                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>;
1936                         interrupt-names = "job", "mmu", "gpu";
1937                         operating-points-v2 = <&gpu_opp_table>;
1938                         power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>,
1939                                         <&spm MT8195_POWER_DOMAIN_MFG3>,
1940                                         <&spm MT8195_POWER_DOMAIN_MFG4>,
1941                                         <&spm MT8195_POWER_DOMAIN_MFG5>,
1942                                         <&spm MT8195_POWER_DOMAIN_MFG6>;
1943                         power-domain-names = "core0", "core1", "core2", "core3", "core4";
1944                         status = "disabled";
1945                 };
1946
1947                 mfgcfg: clock-controller@13fbf000 {
1948                         compatible = "mediatek,mt8195-mfgcfg";
1949                         reg = <0 0x13fbf000 0 0x1000>;
1950                         #clock-cells = <1>;
1951                 };
1952
1953                 vppsys0: syscon@14000000 {
1954                         compatible = "mediatek,mt8195-vppsys0", "syscon";
1955                         reg = <0 0x14000000 0 0x1000>;
1956                         #clock-cells = <1>;
1957                 };
1958
1959                 mutex@1400f000 {
1960                         compatible = "mediatek,mt8195-vpp-mutex";
1961                         reg = <0 0x1400f000 0 0x1000>;
1962                         interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>;
1963                         mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
1964                         clocks = <&vppsys0 CLK_VPP0_MUTEX>;
1965                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1966                 };
1967
1968                 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
1969                         compatible = "mediatek,mt8195-smi-sub-common";
1970                         reg = <0 0x14010000 0 0x1000>;
1971                         clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
1972                                <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
1973                                <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
1974                         clock-names = "apb", "smi", "gals0";
1975                         mediatek,smi = <&smi_common_vpp>;
1976                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1977                 };
1978
1979                 smi_sub_common_vdec_vpp0_2x1: smi@14011000 {
1980                         compatible = "mediatek,mt8195-smi-sub-common";
1981                         reg = <0 0x14011000 0 0x1000>;
1982                         clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
1983                                  <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
1984                                  <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>;
1985                         clock-names = "apb", "smi", "gals0";
1986                         mediatek,smi = <&smi_common_vpp>;
1987                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1988                 };
1989
1990                 smi_common_vpp: smi@14012000 {
1991                         compatible = "mediatek,mt8195-smi-common-vpp";
1992                         reg = <0 0x14012000 0 0x1000>;
1993                         clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
1994                                <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
1995                                <&vppsys0 CLK_VPP0_SMI_RSI>,
1996                                <&vppsys0 CLK_VPP0_SMI_RSI>;
1997                         clock-names = "apb", "smi", "gals0", "gals1";
1998                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1999                 };
2000
2001                 larb4: larb@14013000 {
2002                         compatible = "mediatek,mt8195-smi-larb";
2003                         reg = <0 0x14013000 0 0x1000>;
2004                         mediatek,larb-id = <4>;
2005                         mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
2006                         clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2007                                <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>;
2008                         clock-names = "apb", "smi";
2009                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2010                 };
2011
2012                 iommu_vpp: iommu@14018000 {
2013                         compatible = "mediatek,mt8195-iommu-vpp";
2014                         reg = <0 0x14018000 0 0x1000>;
2015                         mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8
2016                                           &larb12 &larb14 &larb16 &larb18
2017                                           &larb20 &larb22 &larb23 &larb26
2018                                           &larb27>;
2019                         interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>;
2020                         clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>;
2021                         clock-names = "bclk";
2022                         #iommu-cells = <1>;
2023                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2024                 };
2025
2026                 wpesys: clock-controller@14e00000 {
2027                         compatible = "mediatek,mt8195-wpesys";
2028                         reg = <0 0x14e00000 0 0x1000>;
2029                         #clock-cells = <1>;
2030                 };
2031
2032                 wpesys_vpp0: clock-controller@14e02000 {
2033                         compatible = "mediatek,mt8195-wpesys_vpp0";
2034                         reg = <0 0x14e02000 0 0x1000>;
2035                         #clock-cells = <1>;
2036                 };
2037
2038                 wpesys_vpp1: clock-controller@14e03000 {
2039                         compatible = "mediatek,mt8195-wpesys_vpp1";
2040                         reg = <0 0x14e03000 0 0x1000>;
2041                         #clock-cells = <1>;
2042                 };
2043
2044                 larb7: larb@14e04000 {
2045                         compatible = "mediatek,mt8195-smi-larb";
2046                         reg = <0 0x14e04000 0 0x1000>;
2047                         mediatek,larb-id = <7>;
2048                         mediatek,smi = <&smi_common_vdo>;
2049                         clocks = <&wpesys CLK_WPE_SMI_LARB7>,
2050                                  <&wpesys CLK_WPE_SMI_LARB7>;
2051                         clock-names = "apb", "smi";
2052                         power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2053                 };
2054
2055                 larb8: larb@14e05000 {
2056                         compatible = "mediatek,mt8195-smi-larb";
2057                         reg = <0 0x14e05000 0 0x1000>;
2058                         mediatek,larb-id = <8>;
2059                         mediatek,smi = <&smi_common_vpp>;
2060                         clocks = <&wpesys CLK_WPE_SMI_LARB8>,
2061                                <&wpesys CLK_WPE_SMI_LARB8>,
2062                                <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
2063                         clock-names = "apb", "smi", "gals";
2064                         power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2065                 };
2066
2067                 vppsys1: syscon@14f00000 {
2068                         compatible = "mediatek,mt8195-vppsys1", "syscon";
2069                         reg = <0 0x14f00000 0 0x1000>;
2070                         #clock-cells = <1>;
2071                 };
2072
2073                 mutex@14f01000 {
2074                         compatible = "mediatek,mt8195-vpp-mutex";
2075                         reg = <0 0x14f01000 0 0x1000>;
2076                         interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
2077                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
2078                         clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
2079                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2080                 };
2081
2082                 larb5: larb@14f02000 {
2083                         compatible = "mediatek,mt8195-smi-larb";
2084                         reg = <0 0x14f02000 0 0x1000>;
2085                         mediatek,larb-id = <5>;
2086                         mediatek,smi = <&smi_common_vdo>;
2087                         clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
2088                                <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
2089                                <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>;
2090                         clock-names = "apb", "smi", "gals";
2091                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2092                 };
2093
2094                 larb6: larb@14f03000 {
2095                         compatible = "mediatek,mt8195-smi-larb";
2096                         reg = <0 0x14f03000 0 0x1000>;
2097                         mediatek,larb-id = <6>;
2098                         mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
2099                         clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
2100                                <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
2101                                <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>;
2102                         clock-names = "apb", "smi", "gals";
2103                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2104                 };
2105
2106                 imgsys: clock-controller@15000000 {
2107                         compatible = "mediatek,mt8195-imgsys";
2108                         reg = <0 0x15000000 0 0x1000>;
2109                         #clock-cells = <1>;
2110                 };
2111
2112                 larb9: larb@15001000 {
2113                         compatible = "mediatek,mt8195-smi-larb";
2114                         reg = <0 0x15001000 0 0x1000>;
2115                         mediatek,larb-id = <9>;
2116                         mediatek,smi = <&smi_sub_common_img1_3x1>;
2117                         clocks = <&imgsys CLK_IMG_LARB9>,
2118                                  <&imgsys CLK_IMG_LARB9>,
2119                                  <&imgsys CLK_IMG_GALS>;
2120                         clock-names = "apb", "smi", "gals";
2121                         power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2122                 };
2123
2124                 smi_sub_common_img0_3x1: smi@15002000 {
2125                         compatible = "mediatek,mt8195-smi-sub-common";
2126                         reg = <0 0x15002000 0 0x1000>;
2127                         clocks = <&imgsys CLK_IMG_IPE>,
2128                                  <&imgsys CLK_IMG_IPE>,
2129                                  <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
2130                         clock-names = "apb", "smi", "gals0";
2131                         mediatek,smi = <&smi_common_vpp>;
2132                         power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2133                 };
2134
2135                 smi_sub_common_img1_3x1: smi@15003000 {
2136                         compatible = "mediatek,mt8195-smi-sub-common";
2137                         reg = <0 0x15003000 0 0x1000>;
2138                         clocks = <&imgsys CLK_IMG_LARB9>,
2139                                  <&imgsys CLK_IMG_LARB9>,
2140                                  <&imgsys CLK_IMG_GALS>;
2141                         clock-names = "apb", "smi", "gals0";
2142                         mediatek,smi = <&smi_common_vdo>;
2143                         power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2144                 };
2145
2146                 imgsys1_dip_top: clock-controller@15110000 {
2147                         compatible = "mediatek,mt8195-imgsys1_dip_top";
2148                         reg = <0 0x15110000 0 0x1000>;
2149                         #clock-cells = <1>;
2150                 };
2151
2152                 larb10: larb@15120000 {
2153                         compatible = "mediatek,mt8195-smi-larb";
2154                         reg = <0 0x15120000 0 0x1000>;
2155                         mediatek,larb-id = <10>;
2156                         mediatek,smi = <&smi_sub_common_img1_3x1>;
2157                         clocks = <&imgsys CLK_IMG_DIP0>,
2158                                <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>;
2159                         clock-names = "apb", "smi";
2160                         power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2161                 };
2162
2163                 imgsys1_dip_nr: clock-controller@15130000 {
2164                         compatible = "mediatek,mt8195-imgsys1_dip_nr";
2165                         reg = <0 0x15130000 0 0x1000>;
2166                         #clock-cells = <1>;
2167                 };
2168
2169                 imgsys1_wpe: clock-controller@15220000 {
2170                         compatible = "mediatek,mt8195-imgsys1_wpe";
2171                         reg = <0 0x15220000 0 0x1000>;
2172                         #clock-cells = <1>;
2173                 };
2174
2175                 larb11: larb@15230000 {
2176                         compatible = "mediatek,mt8195-smi-larb";
2177                         reg = <0 0x15230000 0 0x1000>;
2178                         mediatek,larb-id = <11>;
2179                         mediatek,smi = <&smi_sub_common_img1_3x1>;
2180                         clocks = <&imgsys CLK_IMG_WPE0>,
2181                                <&imgsys1_wpe CLK_IMG1_WPE_LARB11>;
2182                         clock-names = "apb", "smi";
2183                         power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2184                 };
2185
2186                 ipesys: clock-controller@15330000 {
2187                         compatible = "mediatek,mt8195-ipesys";
2188                         reg = <0 0x15330000 0 0x1000>;
2189                         #clock-cells = <1>;
2190                 };
2191
2192                 larb12: larb@15340000 {
2193                         compatible = "mediatek,mt8195-smi-larb";
2194                         reg = <0 0x15340000 0 0x1000>;
2195                         mediatek,larb-id = <12>;
2196                         mediatek,smi = <&smi_sub_common_img0_3x1>;
2197                         clocks = <&ipesys CLK_IPE_SMI_LARB12>,
2198                                  <&ipesys CLK_IPE_SMI_LARB12>;
2199                         clock-names = "apb", "smi";
2200                         power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
2201                 };
2202
2203                 camsys: clock-controller@16000000 {
2204                         compatible = "mediatek,mt8195-camsys";
2205                         reg = <0 0x16000000 0 0x1000>;
2206                         #clock-cells = <1>;
2207                 };
2208
2209                 larb13: larb@16001000 {
2210                         compatible = "mediatek,mt8195-smi-larb";
2211                         reg = <0 0x16001000 0 0x1000>;
2212                         mediatek,larb-id = <13>;
2213                         mediatek,smi = <&smi_sub_common_cam_4x1>;
2214                         clocks = <&camsys CLK_CAM_LARB13>,
2215                                <&camsys CLK_CAM_LARB13>,
2216                                <&camsys CLK_CAM_CAM2MM0_GALS>;
2217                         clock-names = "apb", "smi", "gals";
2218                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2219                 };
2220
2221                 larb14: larb@16002000 {
2222                         compatible = "mediatek,mt8195-smi-larb";
2223                         reg = <0 0x16002000 0 0x1000>;
2224                         mediatek,larb-id = <14>;
2225                         mediatek,smi = <&smi_sub_common_cam_7x1>;
2226                         clocks = <&camsys CLK_CAM_LARB14>,
2227                                  <&camsys CLK_CAM_LARB14>;
2228                         clock-names = "apb", "smi";
2229                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2230                 };
2231
2232                 smi_sub_common_cam_4x1: smi@16004000 {
2233                         compatible = "mediatek,mt8195-smi-sub-common";
2234                         reg = <0 0x16004000 0 0x1000>;
2235                         clocks = <&camsys CLK_CAM_LARB13>,
2236                                  <&camsys CLK_CAM_LARB13>,
2237                                  <&camsys CLK_CAM_CAM2MM0_GALS>;
2238                         clock-names = "apb", "smi", "gals0";
2239                         mediatek,smi = <&smi_common_vdo>;
2240                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2241                 };
2242
2243                 smi_sub_common_cam_7x1: smi@16005000 {
2244                         compatible = "mediatek,mt8195-smi-sub-common";
2245                         reg = <0 0x16005000 0 0x1000>;
2246                         clocks = <&camsys CLK_CAM_LARB14>,
2247                                  <&camsys CLK_CAM_CAM2MM1_GALS>,
2248                                  <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
2249                         clock-names = "apb", "smi", "gals0";
2250                         mediatek,smi = <&smi_common_vpp>;
2251                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2252                 };
2253
2254                 larb16: larb@16012000 {
2255                         compatible = "mediatek,mt8195-smi-larb";
2256                         reg = <0 0x16012000 0 0x1000>;
2257                         mediatek,larb-id = <16>;
2258                         mediatek,smi = <&smi_sub_common_cam_7x1>;
2259                         clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>,
2260                                  <&camsys_rawa CLK_CAM_RAWA_LARBX>;
2261                         clock-names = "apb", "smi";
2262                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2263                 };
2264
2265                 larb17: larb@16013000 {
2266                         compatible = "mediatek,mt8195-smi-larb";
2267                         reg = <0 0x16013000 0 0x1000>;
2268                         mediatek,larb-id = <17>;
2269                         mediatek,smi = <&smi_sub_common_cam_4x1>;
2270                         clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>,
2271                                  <&camsys_yuva CLK_CAM_YUVA_LARBX>;
2272                         clock-names = "apb", "smi";
2273                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2274                 };
2275
2276                 larb27: larb@16014000 {
2277                         compatible = "mediatek,mt8195-smi-larb";
2278                         reg = <0 0x16014000 0 0x1000>;
2279                         mediatek,larb-id = <27>;
2280                         mediatek,smi = <&smi_sub_common_cam_7x1>;
2281                         clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>,
2282                                  <&camsys_rawb CLK_CAM_RAWB_LARBX>;
2283                         clock-names = "apb", "smi";
2284                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2285                 };
2286
2287                 larb28: larb@16015000 {
2288                         compatible = "mediatek,mt8195-smi-larb";
2289                         reg = <0 0x16015000 0 0x1000>;
2290                         mediatek,larb-id = <28>;
2291                         mediatek,smi = <&smi_sub_common_cam_4x1>;
2292                         clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>,
2293                                  <&camsys_yuvb CLK_CAM_YUVB_LARBX>;
2294                         clock-names = "apb", "smi";
2295                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2296                 };
2297
2298                 camsys_rawa: clock-controller@1604f000 {
2299                         compatible = "mediatek,mt8195-camsys_rawa";
2300                         reg = <0 0x1604f000 0 0x1000>;
2301                         #clock-cells = <1>;
2302                 };
2303
2304                 camsys_yuva: clock-controller@1606f000 {
2305                         compatible = "mediatek,mt8195-camsys_yuva";
2306                         reg = <0 0x1606f000 0 0x1000>;
2307                         #clock-cells = <1>;
2308                 };
2309
2310                 camsys_rawb: clock-controller@1608f000 {
2311                         compatible = "mediatek,mt8195-camsys_rawb";
2312                         reg = <0 0x1608f000 0 0x1000>;
2313                         #clock-cells = <1>;
2314                 };
2315
2316                 camsys_yuvb: clock-controller@160af000 {
2317                         compatible = "mediatek,mt8195-camsys_yuvb";
2318                         reg = <0 0x160af000 0 0x1000>;
2319                         #clock-cells = <1>;
2320                 };
2321
2322                 camsys_mraw: clock-controller@16140000 {
2323                         compatible = "mediatek,mt8195-camsys_mraw";
2324                         reg = <0 0x16140000 0 0x1000>;
2325                         #clock-cells = <1>;
2326                 };
2327
2328                 larb25: larb@16141000 {
2329                         compatible = "mediatek,mt8195-smi-larb";
2330                         reg = <0 0x16141000 0 0x1000>;
2331                         mediatek,larb-id = <25>;
2332                         mediatek,smi = <&smi_sub_common_cam_4x1>;
2333                         clocks = <&camsys CLK_CAM_LARB13>,
2334                                  <&camsys_mraw CLK_CAM_MRAW_LARBX>,
2335                                  <&camsys CLK_CAM_CAM2MM0_GALS>;
2336                         clock-names = "apb", "smi", "gals";
2337                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2338                 };
2339
2340                 larb26: larb@16142000 {
2341                         compatible = "mediatek,mt8195-smi-larb";
2342                         reg = <0 0x16142000 0 0x1000>;
2343                         mediatek,larb-id = <26>;
2344                         mediatek,smi = <&smi_sub_common_cam_7x1>;
2345                         clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>,
2346                                  <&camsys_mraw CLK_CAM_MRAW_LARBX>;
2347                         clock-names = "apb", "smi";
2348                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2349
2350                 };
2351
2352                 ccusys: clock-controller@17200000 {
2353                         compatible = "mediatek,mt8195-ccusys";
2354                         reg = <0 0x17200000 0 0x1000>;
2355                         #clock-cells = <1>;
2356                 };
2357
2358                 larb18: larb@17201000 {
2359                         compatible = "mediatek,mt8195-smi-larb";
2360                         reg = <0 0x17201000 0 0x1000>;
2361                         mediatek,larb-id = <18>;
2362                         mediatek,smi = <&smi_sub_common_cam_7x1>;
2363                         clocks = <&ccusys CLK_CCU_LARB18>,
2364                                  <&ccusys CLK_CCU_LARB18>;
2365                         clock-names = "apb", "smi";
2366                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2367                 };
2368
2369                 larb24: larb@1800d000 {
2370                         compatible = "mediatek,mt8195-smi-larb";
2371                         reg = <0 0x1800d000 0 0x1000>;
2372                         mediatek,larb-id = <24>;
2373                         mediatek,smi = <&smi_common_vdo>;
2374                         clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
2375                                  <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
2376                         clock-names = "apb", "smi";
2377                         power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2378                 };
2379
2380                 larb23: larb@1800e000 {
2381                         compatible = "mediatek,mt8195-smi-larb";
2382                         reg = <0 0x1800e000 0 0x1000>;
2383                         mediatek,larb-id = <23>;
2384                         mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
2385                         clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2386                                  <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
2387                         clock-names = "apb", "smi";
2388                         power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2389                 };
2390
2391                 vdecsys_soc: clock-controller@1800f000 {
2392                         compatible = "mediatek,mt8195-vdecsys_soc";
2393                         reg = <0 0x1800f000 0 0x1000>;
2394                         #clock-cells = <1>;
2395                 };
2396
2397                 larb21: larb@1802e000 {
2398                         compatible = "mediatek,mt8195-smi-larb";
2399                         reg = <0 0x1802e000 0 0x1000>;
2400                         mediatek,larb-id = <21>;
2401                         mediatek,smi = <&smi_common_vdo>;
2402                         clocks = <&vdecsys CLK_VDEC_LARB1>,
2403                                  <&vdecsys CLK_VDEC_LARB1>;
2404                         clock-names = "apb", "smi";
2405                         power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2406                 };
2407
2408                 vdecsys: clock-controller@1802f000 {
2409                         compatible = "mediatek,mt8195-vdecsys";
2410                         reg = <0 0x1802f000 0 0x1000>;
2411                         #clock-cells = <1>;
2412                 };
2413
2414                 larb22: larb@1803e000 {
2415                         compatible = "mediatek,mt8195-smi-larb";
2416                         reg = <0 0x1803e000 0 0x1000>;
2417                         mediatek,larb-id = <22>;
2418                         mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
2419                         clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2420                                  <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
2421                         clock-names = "apb", "smi";
2422                         power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
2423                 };
2424
2425                 vdecsys_core1: clock-controller@1803f000 {
2426                         compatible = "mediatek,mt8195-vdecsys_core1";
2427                         reg = <0 0x1803f000 0 0x1000>;
2428                         #clock-cells = <1>;
2429                 };
2430
2431                 apusys_pll: clock-controller@190f3000 {
2432                         compatible = "mediatek,mt8195-apusys_pll";
2433                         reg = <0 0x190f3000 0 0x1000>;
2434                         #clock-cells = <1>;
2435                 };
2436
2437                 vencsys: clock-controller@1a000000 {
2438                         compatible = "mediatek,mt8195-vencsys";
2439                         reg = <0 0x1a000000 0 0x1000>;
2440                         #clock-cells = <1>;
2441                 };
2442
2443                 larb19: larb@1a010000 {
2444                         compatible = "mediatek,mt8195-smi-larb";
2445                         reg = <0 0x1a010000 0 0x1000>;
2446                         mediatek,larb-id = <19>;
2447                         mediatek,smi = <&smi_common_vdo>;
2448                         clocks = <&vencsys CLK_VENC_VENC>,
2449                                  <&vencsys CLK_VENC_GALS>;
2450                         clock-names = "apb", "smi";
2451                         power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2452                 };
2453
2454                 venc: video-codec@1a020000 {
2455                         compatible = "mediatek,mt8195-vcodec-enc";
2456                         reg = <0 0x1a020000 0 0x10000>;
2457                         iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>,
2458                                  <&iommu_vdo M4U_PORT_L19_VENC_REC>,
2459                                  <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>,
2460                                  <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>,
2461                                  <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>,
2462                                  <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>,
2463                                  <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>,
2464                                  <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>,
2465                                  <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>;
2466                         interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>;
2467                         mediatek,scp = <&scp>;
2468                         clocks = <&vencsys CLK_VENC_VENC>;
2469                         clock-names = "venc_sel";
2470                         assigned-clocks = <&topckgen CLK_TOP_VENC>;
2471                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2472                         power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2473                         #address-cells = <2>;
2474                         #size-cells = <2>;
2475                 };
2476
2477                 jpgdec-master {
2478                         compatible = "mediatek,mt8195-jpgdec";
2479                         power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2480                         iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
2481                                  <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
2482                                  <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
2483                                  <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
2484                                  <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
2485                                  <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
2486                         #address-cells = <2>;
2487                         #size-cells = <2>;
2488                         ranges;
2489
2490                         jpgdec@1a040000 {
2491                                 compatible = "mediatek,mt8195-jpgdec-hw";
2492                                 reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
2493                                 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
2494                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
2495                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
2496                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
2497                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
2498                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
2499                                 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
2500                                 clocks = <&vencsys CLK_VENC_JPGDEC>;
2501                                 clock-names = "jpgdec";
2502                                 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2503                         };
2504
2505                         jpgdec@1a050000 {
2506                                 compatible = "mediatek,mt8195-jpgdec-hw";
2507                                 reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
2508                                 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
2509                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
2510                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
2511                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
2512                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
2513                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
2514                                 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;
2515                                 clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
2516                                 clock-names = "jpgdec";
2517                                 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2518                         };
2519
2520                         jpgdec@1b040000 {
2521                                 compatible = "mediatek,mt8195-jpgdec-hw";
2522                                 reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
2523                                 iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,
2524                                          <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
2525                                          <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
2526                                          <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
2527                                          <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
2528                                          <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
2529                                 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;
2530                                 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;
2531                                 clock-names = "jpgdec";
2532                                 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
2533                         };
2534                 };
2535
2536                 vencsys_core1: clock-controller@1b000000 {
2537                         compatible = "mediatek,mt8195-vencsys_core1";
2538                         reg = <0 0x1b000000 0 0x1000>;
2539                         #clock-cells = <1>;
2540                 };
2541
2542                 vdosys0: syscon@1c01a000 {
2543                         compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
2544                         reg = <0 0x1c01a000 0 0x1000>;
2545                         mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
2546                         #clock-cells = <1>;
2547                 };
2548
2549
2550                 jpgenc-master {
2551                         compatible = "mediatek,mt8195-jpgenc";
2552                         power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
2553                         iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
2554                                         <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
2555                                         <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
2556                                         <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
2557                         #address-cells = <2>;
2558                         #size-cells = <2>;
2559                         ranges;
2560
2561                         jpgenc@1a030000 {
2562                                 compatible = "mediatek,mt8195-jpgenc-hw";
2563                                 reg = <0 0x1a030000 0 0x10000>;
2564                                 iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>,
2565                                                 <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>,
2566                                                 <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>,
2567                                                 <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>;
2568                                 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>;
2569                                 clocks = <&vencsys CLK_VENC_JPGENC>;
2570                                 clock-names = "jpgenc";
2571                                 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2572                         };
2573
2574                         jpgenc@1b030000 {
2575                                 compatible = "mediatek,mt8195-jpgenc-hw";
2576                                 reg = <0 0x1b030000 0 0x10000>;
2577                                 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
2578                                                 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
2579                                                 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
2580                                                 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
2581                                 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>;
2582                                 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>;
2583                                 clock-names = "jpgenc";
2584                                 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
2585                         };
2586                 };
2587
2588                 larb20: larb@1b010000 {
2589                         compatible = "mediatek,mt8195-smi-larb";
2590                         reg = <0 0x1b010000 0 0x1000>;
2591                         mediatek,larb-id = <20>;
2592                         mediatek,smi = <&smi_common_vpp>;
2593                         clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>,
2594                                  <&vencsys_core1 CLK_VENC_CORE1_GALS>,
2595                                  <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
2596                         clock-names = "apb", "smi", "gals";
2597                         power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
2598                 };
2599
2600                 ovl0: ovl@1c000000 {
2601                         compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";
2602                         reg = <0 0x1c000000 0 0x1000>;
2603                         interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
2604                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2605                         clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
2606                         iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
2607                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
2608                 };
2609
2610                 rdma0: rdma@1c002000 {
2611                         compatible = "mediatek,mt8195-disp-rdma";
2612                         reg = <0 0x1c002000 0 0x1000>;
2613                         interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
2614                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2615                         clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
2616                         iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
2617                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
2618                 };
2619
2620                 color0: color@1c003000 {
2621                         compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";
2622                         reg = <0 0x1c003000 0 0x1000>;
2623                         interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
2624                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2625                         clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
2626                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
2627                 };
2628
2629                 ccorr0: ccorr@1c004000 {
2630                         compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";
2631                         reg = <0 0x1c004000 0 0x1000>;
2632                         interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
2633                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2634                         clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
2635                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
2636                 };
2637
2638                 aal0: aal@1c005000 {
2639                         compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";
2640                         reg = <0 0x1c005000 0 0x1000>;
2641                         interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
2642                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2643                         clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
2644                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
2645                 };
2646
2647                 gamma0: gamma@1c006000 {
2648                         compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";
2649                         reg = <0 0x1c006000 0 0x1000>;
2650                         interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
2651                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2652                         clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
2653                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
2654                 };
2655
2656                 dither0: dither@1c007000 {
2657                         compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";
2658                         reg = <0 0x1c007000 0 0x1000>;
2659                         interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
2660                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2661                         clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
2662                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
2663                 };
2664
2665                 dsc0: dsc@1c009000 {
2666                         compatible = "mediatek,mt8195-disp-dsc";
2667                         reg = <0 0x1c009000 0 0x1000>;
2668                         interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
2669                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2670                         clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
2671                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
2672                 };
2673
2674                 merge0: merge@1c014000 {
2675                         compatible = "mediatek,mt8195-disp-merge";
2676                         reg = <0 0x1c014000 0 0x1000>;
2677                         interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
2678                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2679                         clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
2680                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
2681                 };
2682
2683                 dp_intf0: dp-intf@1c015000 {
2684                         compatible = "mediatek,mt8195-dp-intf";
2685                         reg = <0 0x1c015000 0 0x1000>;
2686                         interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
2687                         clocks = <&vdosys0  CLK_VDO0_DP_INTF0>,
2688                                  <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
2689                                  <&apmixedsys CLK_APMIXED_TVDPLL1>;
2690                         clock-names = "engine", "pixel", "pll";
2691                         status = "disabled";
2692                 };
2693
2694                 mutex: mutex@1c016000 {
2695                         compatible = "mediatek,mt8195-disp-mutex";
2696                         reg = <0 0x1c016000 0 0x1000>;
2697                         interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
2698                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2699                         clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
2700                         mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
2701                 };
2702
2703                 larb0: larb@1c018000 {
2704                         compatible = "mediatek,mt8195-smi-larb";
2705                         reg = <0 0x1c018000 0 0x1000>;
2706                         mediatek,larb-id = <0>;
2707                         mediatek,smi = <&smi_common_vdo>;
2708                         clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
2709                                  <&vdosys0 CLK_VDO0_SMI_LARB>,
2710                                  <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>;
2711                         clock-names = "apb", "smi", "gals";
2712                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2713                 };
2714
2715                 larb1: larb@1c019000 {
2716                         compatible = "mediatek,mt8195-smi-larb";
2717                         reg = <0 0x1c019000 0 0x1000>;
2718                         mediatek,larb-id = <1>;
2719                         mediatek,smi = <&smi_common_vpp>;
2720                         clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
2721                                  <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
2722                                  <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>;
2723                         clock-names = "apb", "smi", "gals";
2724                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2725                 };
2726
2727                 vdosys1: syscon@1c100000 {
2728                         compatible = "mediatek,mt8195-vdosys1", "syscon";
2729                         reg = <0 0x1c100000 0 0x1000>;
2730                         mboxes = <&gce0 1 CMDQ_THR_PRIO_4>;
2731                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>;
2732                         #clock-cells = <1>;
2733                         #reset-cells = <1>;
2734                 };
2735
2736                 smi_common_vdo: smi@1c01b000 {
2737                         compatible = "mediatek,mt8195-smi-common-vdo";
2738                         reg = <0 0x1c01b000 0 0x1000>;
2739                         clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>,
2740                                  <&vdosys0 CLK_VDO0_SMI_EMI>,
2741                                  <&vdosys0 CLK_VDO0_SMI_RSI>,
2742                                  <&vdosys0 CLK_VDO0_SMI_GALS>;
2743                         clock-names = "apb", "smi", "gals0", "gals1";
2744                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2745
2746                 };
2747
2748                 iommu_vdo: iommu@1c01f000 {
2749                         compatible = "mediatek,mt8195-iommu-vdo";
2750                         reg = <0 0x1c01f000 0 0x1000>;
2751                         mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9
2752                                           &larb10 &larb11 &larb13 &larb17
2753                                           &larb19 &larb21 &larb24 &larb25
2754                                           &larb28>;
2755                         interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>;
2756                         #iommu-cells = <1>;
2757                         clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>;
2758                         clock-names = "bclk";
2759                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2760                 };
2761
2762                 mutex1: mutex@1c101000 {
2763                         compatible = "mediatek,mt8195-disp-mutex";
2764                         reg = <0 0x1c101000 0 0x1000>;
2765                         reg-names = "vdo1_mutex";
2766                         interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
2767                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2768                         clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
2769                         clock-names = "vdo1_mutex";
2770                         mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
2771                 };
2772
2773                 larb2: larb@1c102000 {
2774                         compatible = "mediatek,mt8195-smi-larb";
2775                         reg = <0 0x1c102000 0 0x1000>;
2776                         mediatek,larb-id = <2>;
2777                         mediatek,smi = <&smi_common_vdo>;
2778                         clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>,
2779                                  <&vdosys1 CLK_VDO1_SMI_LARB2>,
2780                                  <&vdosys1 CLK_VDO1_GALS>;
2781                         clock-names = "apb", "smi", "gals";
2782                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2783                 };
2784
2785                 larb3: larb@1c103000 {
2786                         compatible = "mediatek,mt8195-smi-larb";
2787                         reg = <0 0x1c103000 0 0x1000>;
2788                         mediatek,larb-id = <3>;
2789                         mediatek,smi = <&smi_common_vpp>;
2790                         clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
2791                                  <&vdosys1 CLK_VDO1_GALS>,
2792                                  <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
2793                         clock-names = "apb", "smi", "gals";
2794                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2795                 };
2796
2797                 vdo1_rdma0: rdma@1c104000 {
2798                         compatible = "mediatek,mt8195-vdo1-rdma";
2799                         reg = <0 0x1c104000 0 0x1000>;
2800                         interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
2801                         clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
2802                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2803                         iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
2804                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
2805                 };
2806
2807                 vdo1_rdma1: rdma@1c105000 {
2808                         compatible = "mediatek,mt8195-vdo1-rdma";
2809                         reg = <0 0x1c105000 0 0x1000>;
2810                         interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
2811                         clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
2812                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2813                         iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
2814                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
2815                 };
2816
2817                 vdo1_rdma2: rdma@1c106000 {
2818                         compatible = "mediatek,mt8195-vdo1-rdma";
2819                         reg = <0 0x1c106000 0 0x1000>;
2820                         interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
2821                         clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
2822                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2823                         iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
2824                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
2825                 };
2826
2827                 vdo1_rdma3: rdma@1c107000 {
2828                         compatible = "mediatek,mt8195-vdo1-rdma";
2829                         reg = <0 0x1c107000 0 0x1000>;
2830                         interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
2831                         clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
2832                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2833                         iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
2834                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
2835                 };
2836
2837                 vdo1_rdma4: rdma@1c108000 {
2838                         compatible = "mediatek,mt8195-vdo1-rdma";
2839                         reg = <0 0x1c108000 0 0x1000>;
2840                         interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
2841                         clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
2842                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2843                         iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
2844                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
2845                 };
2846
2847                 vdo1_rdma5: rdma@1c109000 {
2848                         compatible = "mediatek,mt8195-vdo1-rdma";
2849                         reg = <0 0x1c109000 0 0x1000>;
2850                         interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
2851                         clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
2852                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2853                         iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
2854                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
2855                 };
2856
2857                 vdo1_rdma6: rdma@1c10a000 {
2858                         compatible = "mediatek,mt8195-vdo1-rdma";
2859                         reg = <0 0x1c10a000 0 0x1000>;
2860                         interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
2861                         clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
2862                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2863                         iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
2864                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
2865                 };
2866
2867                 vdo1_rdma7: rdma@1c10b000 {
2868                         compatible = "mediatek,mt8195-vdo1-rdma";
2869                         reg = <0 0x1c10b000 0 0x1000>;
2870                         interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
2871                         clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
2872                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2873                         iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
2874                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
2875                 };
2876
2877                 merge1: vpp-merge@1c10c000 {
2878                         compatible = "mediatek,mt8195-disp-merge";
2879                         reg = <0 0x1c10c000 0 0x1000>;
2880                         interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
2881                         clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
2882                                  <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
2883                         clock-names = "merge","merge_async";
2884                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2885                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;
2886                         mediatek,merge-mute = <1>;
2887                         resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
2888                 };
2889
2890                 merge2: vpp-merge@1c10d000 {
2891                         compatible = "mediatek,mt8195-disp-merge";
2892                         reg = <0 0x1c10d000 0 0x1000>;
2893                         interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
2894                         clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
2895                                  <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
2896                         clock-names = "merge","merge_async";
2897                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2898                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;
2899                         mediatek,merge-mute = <1>;
2900                         resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>;
2901                 };
2902
2903                 merge3: vpp-merge@1c10e000 {
2904                         compatible = "mediatek,mt8195-disp-merge";
2905                         reg = <0 0x1c10e000 0 0x1000>;
2906                         interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
2907                         clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
2908                                  <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
2909                         clock-names = "merge","merge_async";
2910                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2911                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;
2912                         mediatek,merge-mute = <1>;
2913                         resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>;
2914                 };
2915
2916                 merge4: vpp-merge@1c10f000 {
2917                         compatible = "mediatek,mt8195-disp-merge";
2918                         reg = <0 0x1c10f000 0 0x1000>;
2919                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
2920                         clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
2921                                  <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
2922                         clock-names = "merge","merge_async";
2923                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2924                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;
2925                         mediatek,merge-mute = <1>;
2926                         resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>;
2927                 };
2928
2929                 merge5: vpp-merge@1c110000 {
2930                         compatible = "mediatek,mt8195-disp-merge";
2931                         reg = <0 0x1c110000 0 0x1000>;
2932                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
2933                         clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
2934                                  <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
2935                         clock-names = "merge","merge_async";
2936                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2937                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;
2938                         mediatek,merge-fifo-en = <1>;
2939                         resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
2940                 };
2941
2942                 dp_intf1: dp-intf@1c113000 {
2943                         compatible = "mediatek,mt8195-dp-intf";
2944                         reg = <0 0x1c113000 0 0x1000>;
2945                         interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
2946                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2947                         clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
2948                                  <&vdosys1 CLK_VDO1_DPINTF>,
2949                                  <&apmixedsys CLK_APMIXED_TVDPLL2>;
2950                         clock-names = "engine", "pixel", "pll";
2951                         status = "disabled";
2952                 };
2953
2954                 ethdr0: hdr-engine@1c114000 {
2955                         compatible = "mediatek,mt8195-disp-ethdr";
2956                         reg = <0 0x1c114000 0 0x1000>,
2957                               <0 0x1c115000 0 0x1000>,
2958                               <0 0x1c117000 0 0x1000>,
2959                               <0 0x1c119000 0 0x1000>,
2960                               <0 0x1c11a000 0 0x1000>,
2961                               <0 0x1c11b000 0 0x1000>,
2962                               <0 0x1c11c000 0 0x1000>;
2963                         reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
2964                                     "vdo_be", "adl_ds";
2965                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
2966                                                   <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,
2967                                                   <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,
2968                                                   <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,
2969                                                   <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>,
2970                                                   <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>,
2971                                                   <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>;
2972                         clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
2973                                  <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
2974                                  <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
2975                                  <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
2976                                  <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
2977                                  <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
2978                                  <&vdosys1 CLK_VDO1_26M_SLOW>,
2979                                  <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
2980                                  <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
2981                                  <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
2982                                  <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
2983                                  <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
2984                                  <&topckgen CLK_TOP_ETHDR>;
2985                         clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
2986                                       "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
2987                                       "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
2988                                       "ethdr_top";
2989                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2990                         iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
2991                                  <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
2992                         interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
2993                         resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
2994                                  <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
2995                                  <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
2996                                  <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
2997                                  <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
2998                         reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",
2999                                       "gfx_fe1_async", "vdo_be_async";
3000                 };
3001
3002                 edp_tx: edp-tx@1c500000 {
3003                         compatible = "mediatek,mt8195-edp-tx";
3004                         reg = <0 0x1c500000 0 0x8000>;
3005                         nvmem-cells = <&dp_calibration>;
3006                         nvmem-cell-names = "dp_calibration_data";
3007                         power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
3008                         interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
3009                         max-linkrate-mhz = <8100>;
3010                         status = "disabled";
3011                 };
3012
3013                 dp_tx: dp-tx@1c600000 {
3014                         compatible = "mediatek,mt8195-dp-tx";
3015                         reg = <0 0x1c600000 0 0x8000>;
3016                         nvmem-cells = <&dp_calibration>;
3017                         nvmem-cell-names = "dp_calibration_data";
3018                         power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
3019                         interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
3020                         max-linkrate-mhz = <8100>;
3021                         status = "disabled";
3022                 };
3023         };
3024
3025         thermal_zones: thermal-zones {
3026                 cpu0-thermal {
3027                         polling-delay = <1000>;
3028                         polling-delay-passive = <250>;
3029                         thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
3030
3031                         trips {
3032                                 cpu0_alert: trip-alert {
3033                                         temperature = <85000>;
3034                                         hysteresis = <2000>;
3035                                         type = "passive";
3036                                 };
3037
3038                                 cpu0_crit: trip-crit {
3039                                         temperature = <100000>;
3040                                         hysteresis = <2000>;
3041                                         type = "critical";
3042                                 };
3043                         };
3044
3045                         cooling-maps {
3046                                 map0 {
3047                                         trip = <&cpu0_alert>;
3048                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3049                                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3050                                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3051                                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3052                                 };
3053                         };
3054                 };
3055
3056                 cpu1-thermal {
3057                         polling-delay = <1000>;
3058                         polling-delay-passive = <250>;
3059                         thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>;
3060
3061                         trips {
3062                                 cpu1_alert: trip-alert {
3063                                         temperature = <85000>;
3064                                         hysteresis = <2000>;
3065                                         type = "passive";
3066                                 };
3067
3068                                 cpu1_crit: trip-crit {
3069                                         temperature = <100000>;
3070                                         hysteresis = <2000>;
3071                                         type = "critical";
3072                                 };
3073                         };
3074
3075                         cooling-maps {
3076                                 map0 {
3077                                         trip = <&cpu1_alert>;
3078                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3079                                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3080                                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3081                                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3082                                 };
3083                         };
3084                 };
3085
3086                 cpu2-thermal {
3087                         polling-delay = <1000>;
3088                         polling-delay-passive = <250>;
3089                         thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>;
3090
3091                         trips {
3092                                 cpu2_alert: trip-alert {
3093                                         temperature = <85000>;
3094                                         hysteresis = <2000>;
3095                                         type = "passive";
3096                                 };
3097
3098                                 cpu2_crit: trip-crit {
3099                                         temperature = <100000>;
3100                                         hysteresis = <2000>;
3101                                         type = "critical";
3102                                 };
3103                         };
3104
3105                         cooling-maps {
3106                                 map0 {
3107                                         trip = <&cpu2_alert>;
3108                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3109                                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3110                                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3111                                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3112                                 };
3113                         };
3114                 };
3115
3116                 cpu3-thermal {
3117                         polling-delay = <1000>;
3118                         polling-delay-passive = <250>;
3119                         thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>;
3120
3121                         trips {
3122                                 cpu3_alert: trip-alert {
3123                                         temperature = <85000>;
3124                                         hysteresis = <2000>;
3125                                         type = "passive";
3126                                 };
3127
3128                                 cpu3_crit: trip-crit {
3129                                         temperature = <100000>;
3130                                         hysteresis = <2000>;
3131                                         type = "critical";
3132                                 };
3133                         };
3134
3135                         cooling-maps {
3136                                 map0 {
3137                                         trip = <&cpu3_alert>;
3138                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3139                                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3140                                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3141                                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3142                                 };
3143                         };
3144                 };
3145
3146                 cpu4-thermal {
3147                         polling-delay = <1000>;
3148                         polling-delay-passive = <250>;
3149                         thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>;
3150
3151                         trips {
3152                                 cpu4_alert: trip-alert {
3153                                         temperature = <85000>;
3154                                         hysteresis = <2000>;
3155                                         type = "passive";
3156                                 };
3157
3158                                 cpu4_crit: trip-crit {
3159                                         temperature = <100000>;
3160                                         hysteresis = <2000>;
3161                                         type = "critical";
3162                                 };
3163                         };
3164
3165                         cooling-maps {
3166                                 map0 {
3167                                         trip = <&cpu4_alert>;
3168                                         cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3169                                                                 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3170                                                                 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3171                                                                 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3172                                 };
3173                         };
3174                 };
3175
3176                 cpu5-thermal {
3177                         polling-delay = <1000>;
3178                         polling-delay-passive = <250>;
3179                         thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>;
3180
3181                         trips {
3182                                 cpu5_alert: trip-alert {
3183                                         temperature = <85000>;
3184                                         hysteresis = <2000>;
3185                                         type = "passive";
3186                                 };
3187
3188                                 cpu5_crit: trip-crit {
3189                                         temperature = <100000>;
3190                                         hysteresis = <2000>;
3191                                         type = "critical";
3192                                 };
3193                         };
3194
3195                         cooling-maps {
3196                                 map0 {
3197                                         trip = <&cpu5_alert>;
3198                                         cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3199                                                                 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3200                                                                 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3201                                                                 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3202                                 };
3203                         };
3204                 };
3205
3206                 cpu6-thermal {
3207                         polling-delay = <1000>;
3208                         polling-delay-passive = <250>;
3209                         thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>;
3210
3211                         trips {
3212                                 cpu6_alert: trip-alert {
3213                                         temperature = <85000>;
3214                                         hysteresis = <2000>;
3215                                         type = "passive";
3216                                 };
3217
3218                                 cpu6_crit: trip-crit {
3219                                         temperature = <100000>;
3220                                         hysteresis = <2000>;
3221                                         type = "critical";
3222                                 };
3223                         };
3224
3225                         cooling-maps {
3226                                 map0 {
3227                                         trip = <&cpu6_alert>;
3228                                         cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3229                                                                 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3230                                                                 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3231                                                                 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3232                                 };
3233                         };
3234                 };
3235
3236                 cpu7-thermal {
3237                         polling-delay = <1000>;
3238                         polling-delay-passive = <250>;
3239                         thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>;
3240
3241                         trips {
3242                                 cpu7_alert: trip-alert {
3243                                         temperature = <85000>;
3244                                         hysteresis = <2000>;
3245                                         type = "passive";
3246                                 };
3247
3248                                 cpu7_crit: trip-crit {
3249                                         temperature = <100000>;
3250                                         hysteresis = <2000>;
3251                                         type = "critical";
3252                                 };
3253                         };
3254
3255                         cooling-maps {
3256                                 map0 {
3257                                         trip = <&cpu7_alert>;
3258                                         cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3259                                                                 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3260                                                                 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3261                                                                 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3262                                 };
3263                         };
3264                 };
3265         };
3266 };