src/arm64/qcom/msm8994.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
   8 #include <dt-bindings/clock/qcom,mmcc-msm8994.h>
   9 #include <dt-bindings/clock/qcom,rpmcc.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/power/qcom-rpmpd.h>
  12
  13 / {
  14         interrupt-parent = <&intc>;
  15
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 mmc1 = &sdhc1;
  21                 mmc2 = &sdhc2;
  22         };
  23
  24         chosen { };
  25
  26         clocks {
  27                 xo_board: xo-board {
  28                         compatible = "fixed-clock";
  29                         #clock-cells = <0>;
  30                         clock-frequency = <19200000>;
  31                         clock-output-names = "xo_board";
  32                 };
  33
  34                 sleep_clk: sleep-clk {
  35                         compatible = "fixed-clock";
  36                         #clock-cells = <0>;
  37                         clock-frequency = <32768>;
  38                         clock-output-names = "sleep_clk";
  39                 };
  40         };
  41
  42         cpus {
  43                 #address-cells = <2>;
  44                 #size-cells = <0>;
  45
  46                 CPU0: cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a53";
  49                         reg = <0x0 0x0>;
  50                         enable-method = "psci";
  51                         next-level-cache = <&L2_0>;
  52                         L2_0: l2-cache {
  53                                 compatible = "cache";
  54                                 cache-level = <2>;
  55                         };
  56                 };
  57
  58                 CPU1: cpu@1 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a53";
  61                         reg = <0x0 0x1>;
  62                         enable-method = "psci";
  63                         next-level-cache = <&L2_0>;
  64                 };
  65
  66                 CPU2: cpu@2 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a53";
  69                         reg = <0x0 0x2>;
  70                         enable-method = "psci";
  71                         next-level-cache = <&L2_0>;
  72                 };
  73
  74                 CPU3: cpu@3 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a53";
  77                         reg = <0x0 0x3>;
  78                         enable-method = "psci";
  79                         next-level-cache = <&L2_0>;
  80                 };
  81
  82                 CPU4: cpu@100 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a57";
  85                         reg = <0x0 0x100>;
  86                         enable-method = "psci";
  87                         next-level-cache = <&L2_1>;
  88                         L2_1: l2-cache {
  89                                 compatible = "cache";
  90                                 cache-level = <2>;
  91                         };
  92                 };
  93
  94                 CPU5: cpu@101 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a57";
  97                         reg = <0x0 0x101>;
  98                         enable-method = "psci";
  99                         next-level-cache = <&L2_1>;
 100                 };
 101
 102                 CPU6: cpu@102 {
 103                         device_type = "cpu";
 104                         compatible = "arm,cortex-a57";
 105                         reg = <0x0 0x102>;
 106                         enable-method = "psci";
 107                         next-level-cache = <&L2_1>;
 108                 };
 109
 110                 CPU7: cpu@103 {
 111                         device_type = "cpu";
 112                         compatible = "arm,cortex-a57";
 113                         reg = <0x0 0x103>;
 114                         enable-method = "psci";
 115                         next-level-cache = <&L2_1>;
 116                 };
 117
 118                 cpu-map {
 119                         cluster0 {
 120                                 core0 {
 121                                         cpu = <&CPU0>;
 122                                 };
 123
 124                                 core1 {
 125                                         cpu = <&CPU1>;
 126                                 };
 127
 128                                 core2 {
 129                                         cpu = <&CPU2>;
 130                                 };
 131
 132                                 core3 {
 133                                         cpu = <&CPU3>;
 134                                 };
 135                         };
 136
 137                         cluster1 {
 138                                 core0 {
 139                                         cpu = <&CPU4>;
 140                                 };
 141
 142                                 core1 {
 143                                         cpu = <&CPU5>;
 144                                 };
 145
 146                                 cpu6_map: core2 {
 147                                         cpu = <&CPU6>;
 148                                 };
 149
 150                                 cpu7_map: core3 {
 151                                         cpu = <&CPU7>;
 152                                 };
 153                         };
 154                 };
 155         };
 156
 157         firmware {
 158                 scm {
 159                         compatible = "qcom,scm-msm8994", "qcom,scm";
 160                 };
 161         };
 162
 163         memory@80000000 {
 164                 device_type = "memory";
 165                 /* We expect the bootloader to fill in the reg */
 166                 reg = <0 0x80000000 0 0>;
 167         };
 168
 169         pmu {
 170                 compatible = "arm,cortex-a53-pmu";
 171                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
 172         };
 173
 174         psci {
 175                 compatible = "arm,psci-0.2";
 176                 method = "hvc";
 177         };
 178
 179         reserved-memory {
 180                 #address-cells = <2>;
 181                 #size-cells = <2>;
 182                 ranges;
 183
 184                 dfps_data_mem: dfps_data_mem@3400000 {
 185                         reg = <0 0x03400000 0 0x1000>;
 186                         no-map;
 187                 };
 188
 189                 cont_splash_mem: memory@3401000 {
 190                         reg = <0 0x03401000 0 0x2200000>;
 191                         no-map;
 192                 };
 193
 194                 smem_mem: smem_region@6a00000 {
 195                         reg = <0 0x06a00000 0 0x200000>;
 196                         no-map;
 197                 };
 198
 199                 mpss_mem: memory@7000000 {
 200                         reg = <0 0x07000000 0 0x5a00000>;
 201                         no-map;
 202                 };
 203
 204                 peripheral_region: memory@ca00000 {
 205                         reg = <0 0x0ca00000 0 0x1f00000>;
 206                         no-map;
 207                 };
 208
 209                 rmtfs_mem: memory@c6400000 {
 210                         compatible = "qcom,rmtfs-mem";
 211                         reg = <0 0xc6400000 0 0x180000>;
 212                         no-map;
 213
 214                         qcom,client-id = <1>;
 215                 };
 216
 217                 mba_mem: memory@c6700000 {
 218                         reg = <0 0xc6700000 0 0x100000>;
 219                         no-map;
 220                 };
 221
 222                 audio_mem: memory@c7000000 {
 223                         reg = <0 0xc7000000 0 0x800000>;
 224                         no-map;
 225                 };
 226
 227                 adsp_mem: memory@c9400000 {
 228                         reg = <0 0xc9400000 0 0x3f00000>;
 229                         no-map;
 230                 };
 231         };
 232
 233         smd {
 234                 compatible = "qcom,smd";
 235                 rpm {
 236                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 237                         qcom,ipc = <&apcs 8 0>;
 238                         qcom,smd-edge = <15>;
 239                         qcom,remote-pid = <6>;
 240
 241                         rpm_requests: rpm-requests {
 242                                 compatible = "qcom,rpm-msm8994";
 243                                 qcom,smd-channels = "rpm_requests";
 244
 245                                 rpmcc: rpmcc {
 246                                         compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc";
 247                                         #clock-cells = <1>;
 248                                 };
 249
 250                                 rpmpd: power-controller {
 251                                         compatible = "qcom,msm8994-rpmpd";
 252                                         #power-domain-cells = <1>;
 253                                         operating-points-v2 = <&rpmpd_opp_table>;
 254
 255                                         rpmpd_opp_table: opp-table {
 256                                                 compatible = "operating-points-v2";
 257
 258                                                 rpmpd_opp_ret: opp1 {
 259                                                         opp-level = <1>;
 260                                                 };
 261                                                 rpmpd_opp_svs_krait: opp2 {
 262                                                         opp-level = <2>;
 263                                                 };
 264                                                 rpmpd_opp_svs_soc: opp3 {
 265                                                         opp-level = <3>;
 266                                                 };
 267                                                 rpmpd_opp_nom: opp4 {
 268                                                         opp-level = <4>;
 269                                                 };
 270                                                 rpmpd_opp_turbo: opp5 {
 271                                                         opp-level = <5>;
 272                                                 };
 273                                                 rpmpd_opp_super_turbo: opp6 {
 274                                                         opp-level = <6>;
 275                                                 };
 276                                         };
 277                                 };
 278                         };
 279                 };
 280         };
 281
 282         smem {
 283                 compatible = "qcom,smem";
 284                 memory-region = <&smem_mem>;
 285                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 286                 hwlocks = <&tcsr_mutex 3>;
 287         };
 288
 289         smp2p-lpass {
 290                 compatible = "qcom,smp2p";
 291                 qcom,smem = <443>, <429>;
 292
 293                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 294
 295                 qcom,ipc = <&apcs 8 10>;
 296
 297                 qcom,local-pid = <0>;
 298                 qcom,remote-pid = <2>;
 299
 300                 adsp_smp2p_out: master-kernel {
 301                         qcom,entry-name = "master-kernel";
 302                         #qcom,smem-state-cells = <1>;
 303                 };
 304
 305                 adsp_smp2p_in: slave-kernel {
 306                         qcom,entry-name = "slave-kernel";
 307
 308                         interrupt-controller;
 309                         #interrupt-cells = <2>;
 310                 };
 311         };
 312
 313         smp2p-modem {
 314                 compatible = "qcom,smp2p";
 315                 qcom,smem = <435>, <428>;
 316
 317                 interrupt-parent = <&intc>;
 318                 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
 319
 320                 qcom,ipc = <&apcs 8 14>;
 321
 322                 qcom,local-pid = <0>;
 323                 qcom,remote-pid = <1>;
 324
 325                 modem_smp2p_out: master-kernel {
 326                         qcom,entry-name = "master-kernel";
 327                         #qcom,smem-state-cells = <1>;
 328                 };
 329
 330                 modem_smp2p_in: slave-kernel {
 331                         qcom,entry-name = "slave-kernel";
 332
 333                         interrupt-controller;
 334                         #interrupt-cells = <2>;
 335                 };
 336         };
 337
 338         soc: soc {
 339
 340                 #address-cells = <1>;
 341                 #size-cells = <1>;
 342                 ranges = <0 0 0 0xffffffff>;
 343                 compatible = "simple-bus";
 344
 345                 intc: interrupt-controller@f9000000 {
 346                         compatible = "qcom,msm-qgic2";
 347                         interrupt-controller;
 348                         #interrupt-cells = <3>;
 349                         reg = <0xf9000000 0x1000>,
 350                               <0xf9002000 0x1000>;
 351                 };
 352
 353                 apcs: mailbox@f900d000 {
 354                         compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
 355                         reg = <0xf900d000 0x2000>;
 356                         #mbox-cells = <1>;
 357                 };
 358
 359                 watchdog@f9017000 {
 360                         compatible = "qcom,apss-wdt-msm8994", "qcom,kpss-wdt";
 361                         reg = <0xf9017000 0x1000>;
 362                         interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
 363                                      <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
 364                         clocks = <&sleep_clk>;
 365                         timeout-sec = <10>;
 366                 };
 367
 368                 timer@f9020000 {
 369                         #address-cells = <1>;
 370                         #size-cells = <1>;
 371                         ranges;
 372                         compatible = "arm,armv7-timer-mem";
 373                         reg = <0xf9020000 0x1000>;
 374
 375                         frame@f9021000 {
 376                                 frame-number = <0>;
 377                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 378                                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 379                                 reg = <0xf9021000 0x1000>,
 380                                       <0xf9022000 0x1000>;
 381                         };
 382
 383                         frame@f9023000 {
 384                                 frame-number = <1>;
 385                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 386                                 reg = <0xf9023000 0x1000>;
 387                                 status = "disabled";
 388                         };
 389
 390                         frame@f9024000 {
 391                                 frame-number = <2>;
 392                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 393                                 reg = <0xf9024000 0x1000>;
 394                                 status = "disabled";
 395                         };
 396
 397                         frame@f9025000 {
 398                                 frame-number = <3>;
 399                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 400                                 reg = <0xf9025000 0x1000>;
 401                                 status = "disabled";
 402                         };
 403
 404                         frame@f9026000 {
 405                                 frame-number = <4>;
 406                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 407                                 reg = <0xf9026000 0x1000>;
 408                                 status = "disabled";
 409                         };
 410
 411                         frame@f9027000 {
 412                                 frame-number = <5>;
 413                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 414                                 reg = <0xf9027000 0x1000>;
 415                                 status = "disabled";
 416                         };
 417
 418                         frame@f9028000 {
 419                                 frame-number = <6>;
 420                                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 421                                 reg = <0xf9028000 0x1000>;
 422                                 status = "disabled";
 423                         };
 424                 };
 425
 426                 usb3: usb@f92f8800 {
 427                         compatible = "qcom,msm8994-dwc3", "qcom,dwc3";
 428                         reg = <0xf92f8800 0x400>;
 429                         #address-cells = <1>;
 430                         #size-cells = <1>;
 431                         ranges;
 432
 433                         clocks = <&gcc GCC_USB30_MASTER_CLK>,
 434                                  <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
 435                                  <&gcc GCC_USB30_SLEEP_CLK>,
 436                                  <&gcc GCC_USB30_MOCK_UTMI_CLK>;
 437                         clock-names = "core",
 438                                       "iface",
 439                                       "sleep",
 440                                       "mock_utmi";
 441
 442                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
 443                                           <&gcc GCC_USB30_MASTER_CLK>;
 444                         assigned-clock-rates = <19200000>, <120000000>;
 445
 446                         power-domains = <&gcc USB30_GDSC>;
 447                         qcom,select-utmi-as-pipe-clk;
 448
 449                         usb@f9200000 {
 450                                 compatible = "snps,dwc3";
 451                                 reg = <0xf9200000 0xcc00>;
 452                                 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
 453                                 snps,dis_u2_susphy_quirk;
 454                                 snps,dis_enblslpm_quirk;
 455                                 maximum-speed = "high-speed";
 456                                 dr_mode = "peripheral";
 457                         };
 458                 };
 459
 460                 sdhc1: mmc@f9824900 {
 461                         compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
 462                         reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
 463                         reg-names = "hc", "core";
 464
 465                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 466                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 467                         interrupt-names = "hc_irq", "pwr_irq";
 468
 469                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 470                                  <&gcc GCC_SDCC1_APPS_CLK>,
 471                                  <&xo_board>;
 472                         clock-names = "iface", "core", "xo";
 473
 474                         pinctrl-names = "default", "sleep";
 475                         pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
 476                         pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
 477
 478                         bus-width = <8>;
 479                         non-removable;
 480                         status = "disabled";
 481                 };
 482
 483                 sdhc2: mmc@f98a4900 {
 484                         compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
 485                         reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 486                         reg-names = "hc", "core";
 487
 488                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 489                                 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 490                         interrupt-names = "hc_irq", "pwr_irq";
 491
 492                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
 493                                  <&gcc GCC_SDCC2_APPS_CLK>,
 494                                  <&xo_board>;
 495                         clock-names = "iface", "core", "xo";
 496
 497                         pinctrl-names = "default", "sleep";
 498                         pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
 499                         pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
 500
 501                         cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
 502                         bus-width = <4>;
 503                         status = "disabled";
 504                 };
 505
 506                 blsp1_dma: dma-controller@f9904000 {
 507                         compatible = "qcom,bam-v1.7.0";
 508                         reg = <0xf9904000 0x19000>;
 509                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 510                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 511                         clock-names = "bam_clk";
 512                         #dma-cells = <1>;
 513                         qcom,ee = <0>;
 514                         qcom,controlled-remotely;
 515                         num-channels = <24>;
 516                         qcom,num-ees = <4>;
 517                 };
 518
 519                 blsp1_uart2: serial@f991e000 {
 520                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 521                         reg = <0xf991e000 0x1000>;
 522                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 523                         clock-names = "core", "iface";
 524                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
 525                                  <&gcc GCC_BLSP1_AHB_CLK>;
 526                         pinctrl-names = "default", "sleep";
 527                         pinctrl-0 = <&blsp1_uart2_default>;
 528                         pinctrl-1 = <&blsp1_uart2_sleep>;
 529                         status = "disabled";
 530                 };
 531
 532                 blsp1_i2c1: i2c@f9923000 {
 533                         compatible = "qcom,i2c-qup-v2.2.1";
 534                         reg = <0xf9923000 0x500>;
 535                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 536                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
 537                                  <&gcc GCC_BLSP1_AHB_CLK>;
 538                         clock-names = "core", "iface";
 539                         clock-frequency = <400000>;
 540                         dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
 541                         dma-names = "tx", "rx";
 542                         pinctrl-names = "default", "sleep";
 543                         pinctrl-0 = <&i2c1_default>;
 544                         pinctrl-1 = <&i2c1_sleep>;
 545                         #address-cells = <1>;
 546                         #size-cells = <0>;
 547                         status = "disabled";
 548                 };
 549
 550                 blsp1_spi1: spi@f9923000 {
 551                         compatible = "qcom,spi-qup-v2.2.1";
 552                         reg = <0xf9923000 0x500>;
 553                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 554                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 555                                  <&gcc GCC_BLSP1_AHB_CLK>;
 556                         clock-names = "core", "iface";
 557                         dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
 558                         dma-names = "tx", "rx";
 559                         pinctrl-names = "default", "sleep";
 560                         pinctrl-0 = <&blsp1_spi1_default>;
 561                         pinctrl-1 = <&blsp1_spi1_sleep>;
 562                         #address-cells = <1>;
 563                         #size-cells = <0>;
 564                         status = "disabled";
 565                 };
 566
 567                 blsp1_i2c2: i2c@f9924000 {
 568                         compatible = "qcom,i2c-qup-v2.2.1";
 569                         reg = <0xf9924000 0x500>;
 570                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 571                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
 572                                  <&gcc GCC_BLSP1_AHB_CLK>;
 573                         clock-names = "core", "iface";
 574                         clock-frequency = <400000>;
 575                         dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
 576                         dma-names = "tx", "rx";
 577                         pinctrl-names = "default", "sleep";
 578                         pinctrl-0 = <&i2c2_default>;
 579                         pinctrl-1 = <&i2c2_sleep>;
 580                         #address-cells = <1>;
 581                         #size-cells = <0>;
 582                         status = "disabled";
 583                 };
 584
 585                 /* I2C3 doesn't exist */
 586
 587                 blsp1_i2c4: i2c@f9926000 {
 588                         compatible = "qcom,i2c-qup-v2.2.1";
 589                         reg = <0xf9926000 0x500>;
 590                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 591                         clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
 592                                  <&gcc GCC_BLSP1_AHB_CLK>;
 593                         clock-names = "core", "iface";
 594                         clock-frequency = <400000>;
 595                         dmas = <&blsp1_dma 18>, <&blsp1_dma 19>;
 596                         dma-names = "tx", "rx";
 597                         pinctrl-names = "default", "sleep";
 598                         pinctrl-0 = <&i2c4_default>;
 599                         pinctrl-1 = <&i2c4_sleep>;
 600                         #address-cells = <1>;
 601                         #size-cells = <0>;
 602                         status = "disabled";
 603                 };
 604
 605                 blsp1_i2c5: i2c@f9927000 {
 606                         compatible = "qcom,i2c-qup-v2.2.1";
 607                         reg = <0xf9927000 0x500>;
 608                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 609                         clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
 610                                  <&gcc GCC_BLSP1_AHB_CLK>;
 611                         clock-names = "core", "iface";
 612                         clock-frequency = <400000>;
 613                         dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
 614                         dma-names = "tx", "rx";
 615                         pinctrl-names = "default", "sleep";
 616                         pinctrl-0 = <&i2c5_default>;
 617                         pinctrl-1 = <&i2c5_sleep>;
 618                         #address-cells = <1>;
 619                         #size-cells = <0>;
 620                         status = "disabled";
 621                 };
 622
 623                 blsp1_i2c6: i2c@f9928000 {
 624                         compatible = "qcom,i2c-qup-v2.2.1";
 625                         reg = <0xf9928000 0x500>;
 626                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 627                         clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
 628                                  <&gcc GCC_BLSP1_AHB_CLK>;
 629                         clock-names = "core", "iface";
 630                         clock-frequency = <400000>;
 631                         dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
 632                         dma-names = "tx", "rx";
 633                         pinctrl-names = "default", "sleep";
 634                         pinctrl-0 = <&i2c6_default>;
 635                         pinctrl-1 = <&i2c6_sleep>;
 636                         #address-cells = <1>;
 637                         #size-cells = <0>;
 638                         status = "disabled";
 639                 };
 640
 641                 blsp2_dma: dma-controller@f9944000 {
 642                         compatible = "qcom,bam-v1.7.0";
 643                         reg = <0xf9944000 0x19000>;
 644                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 645                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
 646                         clock-names = "bam_clk";
 647                         #dma-cells = <1>;
 648                         qcom,ee = <0>;
 649                         qcom,controlled-remotely;
 650                         num-channels = <24>;
 651                         qcom,num-ees = <4>;
 652                 };
 653
 654                 blsp2_uart2: serial@f995e000 {
 655                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 656                         reg = <0xf995e000 0x1000>;
 657                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 658                         clock-names = "core", "iface";
 659                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
 660                                         <&gcc GCC_BLSP2_AHB_CLK>;
 661                         dmas = <&blsp2_dma 2>, <&blsp2_dma 3>;
 662                         dma-names = "tx", "rx";
 663                         pinctrl-names = "default", "sleep";
 664                         pinctrl-0 = <&blsp2_uart2_default>;
 665                         pinctrl-1 = <&blsp2_uart2_sleep>;
 666                         status = "disabled";
 667                 };
 668
 669                 blsp2_i2c1: i2c@f9963000 {
 670                         compatible = "qcom,i2c-qup-v2.2.1";
 671                         reg = <0xf9963000 0x500>;
 672                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 673                         clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
 674                                  <&gcc GCC_BLSP2_AHB_CLK>;
 675                         clock-names = "core", "iface";
 676                         clock-frequency = <400000>;
 677                         dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
 678                         dma-names = "tx", "rx";
 679                         pinctrl-names = "default", "sleep";
 680                         pinctrl-0 = <&i2c7_default>;
 681                         pinctrl-1 = <&i2c7_sleep>;
 682                         #address-cells = <1>;
 683                         #size-cells = <0>;
 684                         status = "disabled";
 685                 };
 686
 687                 blsp2_spi4: spi@f9966000 {
 688                         compatible = "qcom,spi-qup-v2.2.1";
 689                         reg = <0xf9966000 0x500>;
 690                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 691                         clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
 692                                  <&gcc GCC_BLSP2_AHB_CLK>;
 693                         clock-names = "core", "iface";
 694                         dmas = <&blsp2_dma 18>, <&blsp2_dma 19>;
 695                         dma-names = "tx", "rx";
 696                         pinctrl-names = "default", "sleep";
 697                         pinctrl-0 = <&blsp2_spi10_default>;
 698                         pinctrl-1 = <&blsp2_spi10_sleep>;
 699                         #address-cells = <1>;
 700                         #size-cells = <0>;
 701                         status = "disabled";
 702                 };
 703
 704                 blsp2_i2c5: i2c@f9967000 {
 705                         compatible = "qcom,i2c-qup-v2.2.1";
 706                         reg = <0xf9967000 0x500>;
 707                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 708                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
 709                                  <&gcc GCC_BLSP2_AHB_CLK>;
 710                         clock-names = "core", "iface";
 711                         clock-frequency = <355000>;
 712                         dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
 713                         dma-names = "tx", "rx";
 714                         pinctrl-names = "default", "sleep";
 715                         pinctrl-0 = <&i2c11_default>;
 716                         pinctrl-1 = <&i2c11_sleep>;
 717                         #address-cells = <1>;
 718                         #size-cells = <0>;
 719                         status = "disabled";
 720                 };
 721
 722                 gcc: clock-controller@fc400000 {
 723                         compatible = "qcom,gcc-msm8994";
 724                         #clock-cells = <1>;
 725                         #reset-cells = <1>;
 726                         #power-domain-cells = <1>;
 727                         reg = <0xfc400000 0x2000>;
 728
 729                         clock-names = "xo", "sleep";
 730                         clocks = <&xo_board>, <&sleep_clk>;
 731                 };
 732
 733                 rpm_msg_ram: sram@fc428000 {
 734                         compatible = "qcom,rpm-msg-ram";
 735                         reg = <0xfc428000 0x4000>;
 736                 };
 737
 738                 restart@fc4ab000 {
 739                         compatible = "qcom,pshold";
 740                         reg = <0xfc4ab000 0x4>;
 741                 };
 742
 743                 spmi_bus: spmi@fc4c0000 {
 744                         compatible = "qcom,spmi-pmic-arb";
 745                         reg = <0xfc4cf000 0x1000>,
 746                               <0xfc4cb000 0x1000>,
 747                               <0xfc4ca000 0x1000>;
 748                         reg-names = "core", "intr", "cnfg";
 749                         interrupt-names = "periph_irq";
 750                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 751                         qcom,ee = <0>;
 752                         qcom,channel = <0>;
 753                         #address-cells = <2>;
 754                         #size-cells = <0>;
 755                         interrupt-controller;
 756                         #interrupt-cells = <4>;
 757                 };
 758
 759                 tcsr_mutex: hwlock@fd484000 {
 760                         compatible = "qcom,msm8994-tcsr-mutex", "qcom,tcsr-mutex";
 761                         reg = <0xfd484000 0x1000>;
 762                         #hwlock-cells = <1>;
 763                 };
 764
 765                 tlmm: pinctrl@fd510000 {
 766                         compatible = "qcom,msm8994-pinctrl";
 767                         reg = <0xfd510000 0x4000>;
 768                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 769                         gpio-controller;
 770                         gpio-ranges = <&tlmm 0 0 146>;
 771                         #gpio-cells = <2>;
 772                         interrupt-controller;
 773                         #interrupt-cells = <2>;
 774
 775                         blsp1_uart2_default: blsp1-uart2-default-state {
 776                                 pins = "gpio4", "gpio5";
 777                                 function = "blsp_uart2";
 778                                 drive-strength = <16>;
 779                                 bias-disable;
 780                         };
 781
 782                         blsp1_uart2_sleep: blsp1-uart2-sleep-state {
 783                                 pins = "gpio4", "gpio5";
 784                                 function = "gpio";
 785                                 drive-strength = <2>;
 786                                 bias-pull-down;
 787                         };
 788
 789                         blsp2_uart2_default: blsp2-uart2-default-state {
 790                                 pins = "gpio45", "gpio46", "gpio47", "gpio48";
 791                                 function = "blsp_uart8";
 792                                 drive-strength = <16>;
 793                                 bias-disable;
 794                         };
 795
 796                         blsp2_uart2_sleep: blsp2-uart2-sleep-state {
 797                                 pins = "gpio45", "gpio46", "gpio47", "gpio48";
 798                                 function = "gpio";
 799                                 drive-strength = <2>;
 800                                 bias-disable;
 801                         };
 802
 803                         i2c1_default: i2c1-default-state {
 804                                 pins = "gpio2", "gpio3";
 805                                 function = "blsp_i2c1";
 806                                 drive-strength = <2>;
 807                                 bias-disable;
 808                         };
 809
 810                         i2c1_sleep: i2c1-sleep-state {
 811                                 pins = "gpio2", "gpio3";
 812                                 function = "gpio";
 813                                 drive-strength = <2>;
 814                                 bias-disable;
 815                         };
 816
 817                         i2c2_default: i2c2-default-state {
 818                                 pins = "gpio6", "gpio7";
 819                                 function = "blsp_i2c2";
 820                                 drive-strength = <2>;
 821                                 bias-disable;
 822                         };
 823
 824                         i2c2_sleep: i2c2-sleep-state {
 825                                 pins = "gpio6", "gpio7";
 826                                 function = "gpio";
 827                                 drive-strength = <2>;
 828                                 bias-disable;
 829                         };
 830
 831                         i2c4_default: i2c4-default-state {
 832                                 pins = "gpio19", "gpio20";
 833                                 function = "blsp_i2c4";
 834                                 drive-strength = <2>;
 835                                 bias-disable;
 836                         };
 837
 838                         i2c4_sleep: i2c4-sleep-state {
 839                                 pins = "gpio19", "gpio20";
 840                                 function = "gpio";
 841                                 drive-strength = <2>;
 842                                 bias-pull-down;
 843                                 input-enable;
 844                         };
 845
 846                         i2c5_default: i2c5-default-state {
 847                                 pins = "gpio23", "gpio24";
 848                                 function = "blsp_i2c5";
 849                                 drive-strength = <2>;
 850                                 bias-disable;
 851                         };
 852
 853                         i2c5_sleep: i2c5-sleep-state {
 854                                 pins = "gpio23", "gpio24";
 855                                 function = "gpio";
 856                                 drive-strength = <2>;
 857                                 bias-disable;
 858                         };
 859
 860                         i2c6_default: i2c6-default-state {
 861                                 pins = "gpio28", "gpio27";
 862                                 function = "blsp_i2c6";
 863                                 drive-strength = <2>;
 864                                 bias-disable;
 865                         };
 866
 867                         i2c6_sleep: i2c6-sleep-state {
 868                                 pins = "gpio28", "gpio27";
 869                                 function = "gpio";
 870                                 drive-strength = <2>;
 871                                 bias-disable;
 872                         };
 873
 874                         i2c7_default: i2c7-default-state {
 875                                 pins = "gpio44", "gpio43";
 876                                 function = "blsp_i2c7";
 877                                 drive-strength = <2>;
 878                                 bias-disable;
 879                         };
 880
 881                         i2c7_sleep: i2c7-sleep-state {
 882                                 pins = "gpio44", "gpio43";
 883                                 function = "gpio";
 884                                 drive-strength = <2>;
 885                                 bias-disable;
 886                         };
 887
 888                         blsp2_spi10_default: blsp2-spi10-default-state {
 889                                 default-pins {
 890                                         pins = "gpio53", "gpio54", "gpio55";
 891                                         function = "blsp_spi10";
 892                                         drive-strength = <10>;
 893                                         bias-pull-down;
 894                                 };
 895
 896                                 cs-pins {
 897                                         pins = "gpio67";
 898                                         function = "gpio";
 899                                         drive-strength = <2>;
 900                                         bias-disable;
 901                                 };
 902                         };
 903
 904                         blsp2_spi10_sleep: blsp2-spi10-sleep-state {
 905                                 pins = "gpio53", "gpio54", "gpio55";
 906                                 function = "gpio";
 907                                 drive-strength = <2>;
 908                                 bias-disable;
 909                         };
 910
 911                         i2c11_default: i2c11-default-state {
 912                                 pins = "gpio83", "gpio84";
 913                                 function = "blsp_i2c11";
 914                                 drive-strength = <2>;
 915                                 bias-disable;
 916                         };
 917
 918                         i2c11_sleep: i2c11-sleep-state {
 919                                 pins = "gpio83", "gpio84";
 920                                 function = "gpio";
 921                                 drive-strength = <2>;
 922                                 bias-disable;
 923                         };
 924
 925                         blsp1_spi1_default: blsp1-spi1-default-state {
 926                                 default-pins {
 927                                         pins = "gpio0", "gpio1", "gpio3";
 928                                         function = "blsp_spi1";
 929                                         drive-strength = <10>;
 930                                         bias-pull-down;
 931                                 };
 932
 933                                 cs-pins {
 934                                         pins = "gpio8";
 935                                         function = "gpio";
 936                                         drive-strength = <2>;
 937                                         bias-disable;
 938                                 };
 939                         };
 940
 941                         blsp1_spi1_sleep: blsp1-spi1-sleep-state {
 942                                 pins = "gpio0", "gpio1", "gpio3";
 943                                 function = "gpio";
 944                                 drive-strength = <2>;
 945                                 bias-disable;
 946                         };
 947
 948                         sdc1_clk_on: clk-on-state {
 949                                 pins = "sdc1_clk";
 950                                 bias-disable;
 951                                 drive-strength = <16>;
 952                         };
 953
 954                         sdc1_clk_off: clk-off-state {
 955                                 pins = "sdc1_clk";
 956                                 bias-disable;
 957                                 drive-strength = <2>;
 958                         };
 959
 960                         sdc1_cmd_on: cmd-on-state {
 961                                 pins = "sdc1_cmd";
 962                                 bias-pull-up;
 963                                 drive-strength = <8>;
 964                         };
 965
 966                         sdc1_cmd_off: cmd-off-state {
 967                                 pins = "sdc1_cmd";
 968                                 bias-pull-up;
 969                                 drive-strength = <2>;
 970                         };
 971
 972                         sdc1_data_on: data-on-state {
 973                                 pins = "sdc1_data";
 974                                 bias-pull-up;
 975                                 drive-strength = <8>;
 976                         };
 977
 978                         sdc1_data_off: data-off-state {
 979                                 pins = "sdc1_data";
 980                                 bias-pull-up;
 981                                 drive-strength = <2>;
 982                         };
 983
 984                         sdc1_rclk_on: rclk-on-state {
 985                                 pins = "sdc1_rclk";
 986                                 bias-pull-down;
 987                         };
 988
 989                         sdc1_rclk_off: rclk-off-state {
 990                                 pins = "sdc1_rclk";
 991                                 bias-pull-down;
 992                         };
 993
 994                         sdc2_clk_on: sdc2-clk-on-state {
 995                                 pins = "sdc2_clk";
 996                                 bias-disable;
 997                                 drive-strength = <10>;
 998                         };
 999
1000                         sdc2_clk_off: sdc2-clk-off-state {
1001                                 pins = "sdc2_clk";
1002                                 bias-disable;
1003                                 drive-strength = <2>;
1004                         };
1005
1006                         sdc2_cmd_on: sdc2-cmd-on-state {
1007                                 pins = "sdc2_cmd";
1008                                 bias-pull-up;
1009                                 drive-strength = <10>;
1010                         };
1011
1012                         sdc2_cmd_off: sdc2-cmd-off-state {
1013                                 pins = "sdc2_cmd";
1014                                 bias-pull-up;
1015                                 drive-strength = <2>;
1016                         };
1017
1018                         sdc2_data_on: sdc2-data-on-state {
1019                                 pins = "sdc2_data";
1020                                 bias-pull-up;
1021                                 drive-strength = <10>;
1022                         };
1023
1024                         sdc2_data_off: sdc2-data-off-state {
1025                                 pins = "sdc2_data";
1026                                 bias-pull-up;
1027                                 drive-strength = <2>;
1028                         };
1029                 };
1030
1031                 mmcc: clock-controller@fd8c0000 {
1032                         compatible = "qcom,mmcc-msm8994";
1033                         reg = <0xfd8c0000 0x5200>;
1034                         #clock-cells = <1>;
1035                         #reset-cells = <1>;
1036                         #power-domain-cells = <1>;
1037
1038                         clock-names = "xo",
1039                                       "gpll0",
1040                                       "mmssnoc_ahb",
1041                                       "oxili_gfx3d_clk_src",
1042                                       "dsi0pll",
1043                                       "dsi0pllbyte",
1044                                       "dsi1pll",
1045                                       "dsi1pllbyte",
1046                                       "hdmipll";
1047                         clocks = <&xo_board>,
1048                                  <&gcc GPLL0_OUT_MMSSCC>,
1049                                  <&rpmcc RPM_SMD_MMSSNOC_AHB_CLK>,
1050                                  <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
1051                                  <0>,
1052                                  <0>,
1053                                  <0>,
1054                                  <0>,
1055                                  <0>;
1056
1057                         assigned-clocks = <&mmcc MMPLL0_PLL>,
1058                                           <&mmcc MMPLL1_PLL>,
1059                                           <&mmcc MMPLL3_PLL>,
1060                                           <&mmcc MMPLL4_PLL>,
1061                                           <&mmcc MMPLL5_PLL>;
1062                         assigned-clock-rates = <800000000>,
1063                                                <1167000000>,
1064                                                <1020000000>,
1065                                                <960000000>,
1066                                                <600000000>;
1067                 };
1068
1069                 ocmem: sram@fdd00000 {
1070                         compatible = "qcom,msm8974-ocmem";
1071                         reg = <0xfdd00000 0x2000>,
1072                               <0xfec00000 0x200000>;
1073                         reg-names = "ctrl", "mem";
1074                         ranges = <0 0xfec00000 0x200000>;
1075                         clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1076                                  <&mmcc OCMEMCX_OCMEMNOC_CLK>;
1077                         clock-names = "core", "iface";
1078
1079                         #address-cells = <1>;
1080                         #size-cells = <1>;
1081
1082                         gmu_sram: gmu-sram@0 {
1083                                 reg = <0x0 0x180000>;
1084                         };
1085                 };
1086         };
1087
1088         timer: timer {
1089                 compatible = "arm,armv8-timer";
1090                 interrupts = <GIC_PPI 2 0xff08>,
1091                              <GIC_PPI 3 0xff08>,
1092                              <GIC_PPI 4 0xff08>,
1093                              <GIC_PPI 1 0xff08>;
1094         };
1095
1096         vph_pwr: vph-pwr-regulator {
1097                 compatible = "regulator-fixed";
1098                 regulator-name = "vph_pwr";
1099
1100                 regulator-min-microvolt = <3600000>;
1101                 regulator-max-microvolt = <3600000>;
1102
1103                 regulator-always-on;
1104         };
1105 };
1106