src/arm64/qcom/msm8998.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
   3
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
   6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
   7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
   8 #include <dt-bindings/clock/qcom,rpmcc.h>
   9 #include <dt-bindings/power/qcom-rpmpd.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11
  12 / {
  13         interrupt-parent = <&intc>;
  14
  15         qcom,msm-id = <292 0x0>;
  16
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         chosen { };
  21
  22         memory@80000000 {
  23                 device_type = "memory";
  24                 /* We expect the bootloader to fill in the reg */
  25                 reg = <0x0 0x80000000 0x0 0x0>;
  26         };
  27
  28         reserved-memory {
  29                 #address-cells = <2>;
  30                 #size-cells = <2>;
  31                 ranges;
  32
  33                 hyp_mem: memory@85800000 {
  34                         reg = <0x0 0x85800000 0x0 0x600000>;
  35                         no-map;
  36                 };
  37
  38                 xbl_mem: memory@85e00000 {
  39                         reg = <0x0 0x85e00000 0x0 0x100000>;
  40                         no-map;
  41                 };
  42
  43                 smem_mem: smem-mem@86000000 {
  44                         reg = <0x0 0x86000000 0x0 0x200000>;
  45                         no-map;
  46                 };
  47
  48                 tz_mem: memory@86200000 {
  49                         reg = <0x0 0x86200000 0x0 0x2d00000>;
  50                         no-map;
  51                 };
  52
  53                 rmtfs_mem: memory@88f00000 {
  54                         compatible = "qcom,rmtfs-mem";
  55                         reg = <0x0 0x88f00000 0x0 0x200000>;
  56                         no-map;
  57
  58                         qcom,client-id = <1>;
  59                         qcom,vmid = <15>;
  60                 };
  61
  62                 spss_mem: memory@8ab00000 {
  63                         reg = <0x0 0x8ab00000 0x0 0x700000>;
  64                         no-map;
  65                 };
  66
  67                 adsp_mem: memory@8b200000 {
  68                         reg = <0x0 0x8b200000 0x0 0x1a00000>;
  69                         no-map;
  70                 };
  71
  72                 mpss_mem: memory@8cc00000 {
  73                         reg = <0x0 0x8cc00000 0x0 0x7000000>;
  74                         no-map;
  75                 };
  76
  77                 venus_mem: memory@93c00000 {
  78                         reg = <0x0 0x93c00000 0x0 0x500000>;
  79                         no-map;
  80                 };
  81
  82                 mba_mem: memory@94100000 {
  83                         reg = <0x0 0x94100000 0x0 0x200000>;
  84                         no-map;
  85                 };
  86
  87                 slpi_mem: memory@94300000 {
  88                         reg = <0x0 0x94300000 0x0 0xf00000>;
  89                         no-map;
  90                 };
  91
  92                 ipa_fw_mem: memory@95200000 {
  93                         reg = <0x0 0x95200000 0x0 0x10000>;
  94                         no-map;
  95                 };
  96
  97                 ipa_gsi_mem: memory@95210000 {
  98                         reg = <0x0 0x95210000 0x0 0x5000>;
  99                         no-map;
 100                 };
 101
 102                 gpu_mem: memory@95600000 {
 103                         reg = <0x0 0x95600000 0x0 0x100000>;
 104                         no-map;
 105                 };
 106
 107                 wlan_msa_mem: memory@95700000 {
 108                         reg = <0x0 0x95700000 0x0 0x100000>;
 109                         no-map;
 110                 };
 111         };
 112
 113         clocks {
 114                 xo: xo-board {
 115                         compatible = "fixed-clock";
 116                         #clock-cells = <0>;
 117                         clock-frequency = <19200000>;
 118                         clock-output-names = "xo_board";
 119                 };
 120
 121                 sleep_clk: sleep-clk {
 122                         compatible = "fixed-clock";
 123                         #clock-cells = <0>;
 124                         clock-frequency = <32764>;
 125                 };
 126         };
 127
 128         cpus {
 129                 #address-cells = <2>;
 130                 #size-cells = <0>;
 131
 132                 CPU0: cpu@0 {
 133                         device_type = "cpu";
 134                         compatible = "qcom,kryo280";
 135                         reg = <0x0 0x0>;
 136                         enable-method = "psci";
 137                         capacity-dmips-mhz = <1024>;
 138                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 139                         next-level-cache = <&L2_0>;
 140                         L2_0: l2-cache {
 141                                 compatible = "cache";
 142                                 cache-level = <2>;
 143                         };
 144                 };
 145
 146                 CPU1: cpu@1 {
 147                         device_type = "cpu";
 148                         compatible = "qcom,kryo280";
 149                         reg = <0x0 0x1>;
 150                         enable-method = "psci";
 151                         capacity-dmips-mhz = <1024>;
 152                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 153                         next-level-cache = <&L2_0>;
 154                 };
 155
 156                 CPU2: cpu@2 {
 157                         device_type = "cpu";
 158                         compatible = "qcom,kryo280";
 159                         reg = <0x0 0x2>;
 160                         enable-method = "psci";
 161                         capacity-dmips-mhz = <1024>;
 162                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 163                         next-level-cache = <&L2_0>;
 164                 };
 165
 166                 CPU3: cpu@3 {
 167                         device_type = "cpu";
 168                         compatible = "qcom,kryo280";
 169                         reg = <0x0 0x3>;
 170                         enable-method = "psci";
 171                         capacity-dmips-mhz = <1024>;
 172                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 173                         next-level-cache = <&L2_0>;
 174                 };
 175
 176                 CPU4: cpu@100 {
 177                         device_type = "cpu";
 178                         compatible = "qcom,kryo280";
 179                         reg = <0x0 0x100>;
 180                         enable-method = "psci";
 181                         capacity-dmips-mhz = <1536>;
 182                         cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 183                         next-level-cache = <&L2_1>;
 184                         L2_1: l2-cache {
 185                                 compatible = "cache";
 186                                 cache-level = <2>;
 187                         };
 188                 };
 189
 190                 CPU5: cpu@101 {
 191                         device_type = "cpu";
 192                         compatible = "qcom,kryo280";
 193                         reg = <0x0 0x101>;
 194                         enable-method = "psci";
 195                         capacity-dmips-mhz = <1536>;
 196                         cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 197                         next-level-cache = <&L2_1>;
 198                 };
 199
 200                 CPU6: cpu@102 {
 201                         device_type = "cpu";
 202                         compatible = "qcom,kryo280";
 203                         reg = <0x0 0x102>;
 204                         enable-method = "psci";
 205                         capacity-dmips-mhz = <1536>;
 206                         cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 207                         next-level-cache = <&L2_1>;
 208                 };
 209
 210                 CPU7: cpu@103 {
 211                         device_type = "cpu";
 212                         compatible = "qcom,kryo280";
 213                         reg = <0x0 0x103>;
 214                         enable-method = "psci";
 215                         capacity-dmips-mhz = <1536>;
 216                         cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 217                         next-level-cache = <&L2_1>;
 218                 };
 219
 220                 cpu-map {
 221                         cluster0 {
 222                                 core0 {
 223                                         cpu = <&CPU0>;
 224                                 };
 225
 226                                 core1 {
 227                                         cpu = <&CPU1>;
 228                                 };
 229
 230                                 core2 {
 231                                         cpu = <&CPU2>;
 232                                 };
 233
 234                                 core3 {
 235                                         cpu = <&CPU3>;
 236                                 };
 237                         };
 238
 239                         cluster1 {
 240                                 core0 {
 241                                         cpu = <&CPU4>;
 242                                 };
 243
 244                                 core1 {
 245                                         cpu = <&CPU5>;
 246                                 };
 247
 248                                 core2 {
 249                                         cpu = <&CPU6>;
 250                                 };
 251
 252                                 core3 {
 253                                         cpu = <&CPU7>;
 254                                 };
 255                         };
 256                 };
 257
 258                 idle-states {
 259                         entry-method = "psci";
 260
 261                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 262                                 compatible = "arm,idle-state";
 263                                 idle-state-name = "little-retention";
 264                                 /* CPU Retention (C2D), L2 Active */
 265                                 arm,psci-suspend-param = <0x00000002>;
 266                                 entry-latency-us = <81>;
 267                                 exit-latency-us = <86>;
 268                                 min-residency-us = <504>;
 269                         };
 270
 271                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 272                                 compatible = "arm,idle-state";
 273                                 idle-state-name = "little-power-collapse";
 274                                 /* CPU + L2 Power Collapse (C3, D4) */
 275                                 arm,psci-suspend-param = <0x40000003>;
 276                                 entry-latency-us = <814>;
 277                                 exit-latency-us = <4562>;
 278                                 min-residency-us = <9183>;
 279                                 local-timer-stop;
 280                         };
 281
 282                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 283                                 compatible = "arm,idle-state";
 284                                 idle-state-name = "big-retention";
 285                                 /* CPU Retention (C2D), L2 Active */
 286                                 arm,psci-suspend-param = <0x00000002>;
 287                                 entry-latency-us = <79>;
 288                                 exit-latency-us = <82>;
 289                                 min-residency-us = <1302>;
 290                         };
 291
 292                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 293                                 compatible = "arm,idle-state";
 294                                 idle-state-name = "big-power-collapse";
 295                                 /* CPU + L2 Power Collapse (C3, D4) */
 296                                 arm,psci-suspend-param = <0x40000003>;
 297                                 entry-latency-us = <724>;
 298                                 exit-latency-us = <2027>;
 299                                 min-residency-us = <9419>;
 300                                 local-timer-stop;
 301                         };
 302                 };
 303         };
 304
 305         firmware {
 306                 scm {
 307                         compatible = "qcom,scm-msm8998", "qcom,scm";
 308                 };
 309         };
 310
 311         psci {
 312                 compatible = "arm,psci-1.0";
 313                 method = "smc";
 314         };
 315
 316         rpm-glink {
 317                 compatible = "qcom,glink-rpm";
 318
 319                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 320                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 321                 mboxes = <&apcs_glb 0>;
 322
 323                 rpm_requests: rpm-requests {
 324                         compatible = "qcom,rpm-msm8998";
 325                         qcom,glink-channels = "rpm_requests";
 326
 327                         rpmcc: clock-controller {
 328                                 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
 329                                 #clock-cells = <1>;
 330                         };
 331
 332                         rpmpd: power-controller {
 333                                 compatible = "qcom,msm8998-rpmpd";
 334                                 #power-domain-cells = <1>;
 335                                 operating-points-v2 = <&rpmpd_opp_table>;
 336
 337                                 rpmpd_opp_table: opp-table {
 338                                         compatible = "operating-points-v2";
 339
 340                                         rpmpd_opp_ret: opp1 {
 341                                                 opp-level = <RPM_SMD_LEVEL_RETENTION>;
 342                                         };
 343
 344                                         rpmpd_opp_ret_plus: opp2 {
 345                                                 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
 346                                         };
 347
 348                                         rpmpd_opp_min_svs: opp3 {
 349                                                 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
 350                                         };
 351
 352                                         rpmpd_opp_low_svs: opp4 {
 353                                                 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
 354                                         };
 355
 356                                         rpmpd_opp_svs: opp5 {
 357                                                 opp-level = <RPM_SMD_LEVEL_SVS>;
 358                                         };
 359
 360                                         rpmpd_opp_svs_plus: opp6 {
 361                                                 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
 362                                         };
 363
 364                                         rpmpd_opp_nom: opp7 {
 365                                                 opp-level = <RPM_SMD_LEVEL_NOM>;
 366                                         };
 367
 368                                         rpmpd_opp_nom_plus: opp8 {
 369                                                 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
 370                                         };
 371
 372                                         rpmpd_opp_turbo: opp9 {
 373                                                 opp-level = <RPM_SMD_LEVEL_TURBO>;
 374                                         };
 375
 376                                         rpmpd_opp_turbo_plus: opp10 {
 377                                                 opp-level = <RPM_SMD_LEVEL_BINNING>;
 378                                         };
 379                                 };
 380                         };
 381                 };
 382         };
 383
 384         smem {
 385                 compatible = "qcom,smem";
 386                 memory-region = <&smem_mem>;
 387                 hwlocks = <&tcsr_mutex 3>;
 388         };
 389
 390         smp2p-lpass {
 391                 compatible = "qcom,smp2p";
 392                 qcom,smem = <443>, <429>;
 393
 394                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 395
 396                 mboxes = <&apcs_glb 10>;
 397
 398                 qcom,local-pid = <0>;
 399                 qcom,remote-pid = <2>;
 400
 401                 adsp_smp2p_out: master-kernel {
 402                         qcom,entry-name = "master-kernel";
 403                         #qcom,smem-state-cells = <1>;
 404                 };
 405
 406                 adsp_smp2p_in: slave-kernel {
 407                         qcom,entry-name = "slave-kernel";
 408
 409                         interrupt-controller;
 410                         #interrupt-cells = <2>;
 411                 };
 412         };
 413
 414         smp2p-mpss {
 415                 compatible = "qcom,smp2p";
 416                 qcom,smem = <435>, <428>;
 417                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 418                 mboxes = <&apcs_glb 14>;
 419                 qcom,local-pid = <0>;
 420                 qcom,remote-pid = <1>;
 421
 422                 modem_smp2p_out: master-kernel {
 423                         qcom,entry-name = "master-kernel";
 424                         #qcom,smem-state-cells = <1>;
 425                 };
 426
 427                 modem_smp2p_in: slave-kernel {
 428                         qcom,entry-name = "slave-kernel";
 429                         interrupt-controller;
 430                         #interrupt-cells = <2>;
 431                 };
 432         };
 433
 434         smp2p-slpi {
 435                 compatible = "qcom,smp2p";
 436                 qcom,smem = <481>, <430>;
 437                 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
 438                 mboxes = <&apcs_glb 26>;
 439                 qcom,local-pid = <0>;
 440                 qcom,remote-pid = <3>;
 441
 442                 slpi_smp2p_out: master-kernel {
 443                         qcom,entry-name = "master-kernel";
 444                         #qcom,smem-state-cells = <1>;
 445                 };
 446
 447                 slpi_smp2p_in: slave-kernel {
 448                         qcom,entry-name = "slave-kernel";
 449                         interrupt-controller;
 450                         #interrupt-cells = <2>;
 451                 };
 452         };
 453
 454         thermal-zones {
 455                 cpu0-thermal {
 456                         polling-delay-passive = <250>;
 457                         polling-delay = <1000>;
 458
 459                         thermal-sensors = <&tsens0 1>;
 460
 461                         trips {
 462                                 cpu0_alert0: trip-point0 {
 463                                         temperature = <75000>;
 464                                         hysteresis = <2000>;
 465                                         type = "passive";
 466                                 };
 467
 468                                 cpu0_crit: cpu_crit {
 469                                         temperature = <110000>;
 470                                         hysteresis = <2000>;
 471                                         type = "critical";
 472                                 };
 473                         };
 474                 };
 475
 476                 cpu1-thermal {
 477                         polling-delay-passive = <250>;
 478                         polling-delay = <1000>;
 479
 480                         thermal-sensors = <&tsens0 2>;
 481
 482                         trips {
 483                                 cpu1_alert0: trip-point0 {
 484                                         temperature = <75000>;
 485                                         hysteresis = <2000>;
 486                                         type = "passive";
 487                                 };
 488
 489                                 cpu1_crit: cpu_crit {
 490                                         temperature = <110000>;
 491                                         hysteresis = <2000>;
 492                                         type = "critical";
 493                                 };
 494                         };
 495                 };
 496
 497                 cpu2-thermal {
 498                         polling-delay-passive = <250>;
 499                         polling-delay = <1000>;
 500
 501                         thermal-sensors = <&tsens0 3>;
 502
 503                         trips {
 504                                 cpu2_alert0: trip-point0 {
 505                                         temperature = <75000>;
 506                                         hysteresis = <2000>;
 507                                         type = "passive";
 508                                 };
 509
 510                                 cpu2_crit: cpu_crit {
 511                                         temperature = <110000>;
 512                                         hysteresis = <2000>;
 513                                         type = "critical";
 514                                 };
 515                         };
 516                 };
 517
 518                 cpu3-thermal {
 519                         polling-delay-passive = <250>;
 520                         polling-delay = <1000>;
 521
 522                         thermal-sensors = <&tsens0 4>;
 523
 524                         trips {
 525                                 cpu3_alert0: trip-point0 {
 526                                         temperature = <75000>;
 527                                         hysteresis = <2000>;
 528                                         type = "passive";
 529                                 };
 530
 531                                 cpu3_crit: cpu_crit {
 532                                         temperature = <110000>;
 533                                         hysteresis = <2000>;
 534                                         type = "critical";
 535                                 };
 536                         };
 537                 };
 538
 539                 cpu4-thermal {
 540                         polling-delay-passive = <250>;
 541                         polling-delay = <1000>;
 542
 543                         thermal-sensors = <&tsens0 7>;
 544
 545                         trips {
 546                                 cpu4_alert0: trip-point0 {
 547                                         temperature = <75000>;
 548                                         hysteresis = <2000>;
 549                                         type = "passive";
 550                                 };
 551
 552                                 cpu4_crit: cpu_crit {
 553                                         temperature = <110000>;
 554                                         hysteresis = <2000>;
 555                                         type = "critical";
 556                                 };
 557                         };
 558                 };
 559
 560                 cpu5-thermal {
 561                         polling-delay-passive = <250>;
 562                         polling-delay = <1000>;
 563
 564                         thermal-sensors = <&tsens0 8>;
 565
 566                         trips {
 567                                 cpu5_alert0: trip-point0 {
 568                                         temperature = <75000>;
 569                                         hysteresis = <2000>;
 570                                         type = "passive";
 571                                 };
 572
 573                                 cpu5_crit: cpu_crit {
 574                                         temperature = <110000>;
 575                                         hysteresis = <2000>;
 576                                         type = "critical";
 577                                 };
 578                         };
 579                 };
 580
 581                 cpu6-thermal {
 582                         polling-delay-passive = <250>;
 583                         polling-delay = <1000>;
 584
 585                         thermal-sensors = <&tsens0 9>;
 586
 587                         trips {
 588                                 cpu6_alert0: trip-point0 {
 589                                         temperature = <75000>;
 590                                         hysteresis = <2000>;
 591                                         type = "passive";
 592                                 };
 593
 594                                 cpu6_crit: cpu_crit {
 595                                         temperature = <110000>;
 596                                         hysteresis = <2000>;
 597                                         type = "critical";
 598                                 };
 599                         };
 600                 };
 601
 602                 cpu7-thermal {
 603                         polling-delay-passive = <250>;
 604                         polling-delay = <1000>;
 605
 606                         thermal-sensors = <&tsens0 10>;
 607
 608                         trips {
 609                                 cpu7_alert0: trip-point0 {
 610                                         temperature = <75000>;
 611                                         hysteresis = <2000>;
 612                                         type = "passive";
 613                                 };
 614
 615                                 cpu7_crit: cpu_crit {
 616                                         temperature = <110000>;
 617                                         hysteresis = <2000>;
 618                                         type = "critical";
 619                                 };
 620                         };
 621                 };
 622
 623                 gpu-bottom-thermal {
 624                         polling-delay-passive = <250>;
 625                         polling-delay = <1000>;
 626
 627                         thermal-sensors = <&tsens0 12>;
 628
 629                         trips {
 630                                 gpu1_alert0: trip-point0 {
 631                                         temperature = <90000>;
 632                                         hysteresis = <2000>;
 633                                         type = "hot";
 634                                 };
 635                         };
 636                 };
 637
 638                 gpu-top-thermal {
 639                         polling-delay-passive = <250>;
 640                         polling-delay = <1000>;
 641
 642                         thermal-sensors = <&tsens0 13>;
 643
 644                         trips {
 645                                 gpu2_alert0: trip-point0 {
 646                                         temperature = <90000>;
 647                                         hysteresis = <2000>;
 648                                         type = "hot";
 649                                 };
 650                         };
 651                 };
 652
 653                 clust0-mhm-thermal {
 654                         polling-delay-passive = <250>;
 655                         polling-delay = <1000>;
 656
 657                         thermal-sensors = <&tsens0 5>;
 658
 659                         trips {
 660                                 cluster0_mhm_alert0: trip-point0 {
 661                                         temperature = <90000>;
 662                                         hysteresis = <2000>;
 663                                         type = "hot";
 664                                 };
 665                         };
 666                 };
 667
 668                 clust1-mhm-thermal {
 669                         polling-delay-passive = <250>;
 670                         polling-delay = <1000>;
 671
 672                         thermal-sensors = <&tsens0 6>;
 673
 674                         trips {
 675                                 cluster1_mhm_alert0: trip-point0 {
 676                                         temperature = <90000>;
 677                                         hysteresis = <2000>;
 678                                         type = "hot";
 679                                 };
 680                         };
 681                 };
 682
 683                 cluster1-l2-thermal {
 684                         polling-delay-passive = <250>;
 685                         polling-delay = <1000>;
 686
 687                         thermal-sensors = <&tsens0 11>;
 688
 689                         trips {
 690                                 cluster1_l2_alert0: trip-point0 {
 691                                         temperature = <90000>;
 692                                         hysteresis = <2000>;
 693                                         type = "hot";
 694                                 };
 695                         };
 696                 };
 697
 698                 modem-thermal {
 699                         polling-delay-passive = <250>;
 700                         polling-delay = <1000>;
 701
 702                         thermal-sensors = <&tsens1 1>;
 703
 704                         trips {
 705                                 modem_alert0: trip-point0 {
 706                                         temperature = <90000>;
 707                                         hysteresis = <2000>;
 708                                         type = "hot";
 709                                 };
 710                         };
 711                 };
 712
 713                 mem-thermal {
 714                         polling-delay-passive = <250>;
 715                         polling-delay = <1000>;
 716
 717                         thermal-sensors = <&tsens1 2>;
 718
 719                         trips {
 720                                 mem_alert0: trip-point0 {
 721                                         temperature = <90000>;
 722                                         hysteresis = <2000>;
 723                                         type = "hot";
 724                                 };
 725                         };
 726                 };
 727
 728                 wlan-thermal {
 729                         polling-delay-passive = <250>;
 730                         polling-delay = <1000>;
 731
 732                         thermal-sensors = <&tsens1 3>;
 733
 734                         trips {
 735                                 wlan_alert0: trip-point0 {
 736                                         temperature = <90000>;
 737                                         hysteresis = <2000>;
 738                                         type = "hot";
 739                                 };
 740                         };
 741                 };
 742
 743                 q6-dsp-thermal {
 744                         polling-delay-passive = <250>;
 745                         polling-delay = <1000>;
 746
 747                         thermal-sensors = <&tsens1 4>;
 748
 749                         trips {
 750                                 q6_dsp_alert0: trip-point0 {
 751                                         temperature = <90000>;
 752                                         hysteresis = <2000>;
 753                                         type = "hot";
 754                                 };
 755                         };
 756                 };
 757
 758                 camera-thermal {
 759                         polling-delay-passive = <250>;
 760                         polling-delay = <1000>;
 761
 762                         thermal-sensors = <&tsens1 5>;
 763
 764                         trips {
 765                                 camera_alert0: trip-point0 {
 766                                         temperature = <90000>;
 767                                         hysteresis = <2000>;
 768                                         type = "hot";
 769                                 };
 770                         };
 771                 };
 772
 773                 multimedia-thermal {
 774                         polling-delay-passive = <250>;
 775                         polling-delay = <1000>;
 776
 777                         thermal-sensors = <&tsens1 6>;
 778
 779                         trips {
 780                                 multimedia_alert0: trip-point0 {
 781                                         temperature = <90000>;
 782                                         hysteresis = <2000>;
 783                                         type = "hot";
 784                                 };
 785                         };
 786                 };
 787         };
 788
 789         timer {
 790                 compatible = "arm,armv8-timer";
 791                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
 792                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
 793                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
 794                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
 795         };
 796
 797         soc: soc {
 798                 #address-cells = <1>;
 799                 #size-cells = <1>;
 800                 ranges = <0 0 0 0xffffffff>;
 801                 compatible = "simple-bus";
 802
 803                 gcc: clock-controller@100000 {
 804                         compatible = "qcom,gcc-msm8998";
 805                         #clock-cells = <1>;
 806                         #reset-cells = <1>;
 807                         #power-domain-cells = <1>;
 808                         reg = <0x00100000 0xb0000>;
 809
 810                         clock-names = "xo", "sleep_clk";
 811                         clocks = <&xo>, <&sleep_clk>;
 812
 813                         /*
 814                          * The hypervisor typically configures the memory region where these clocks
 815                          * reside as read-only for the HLOS. If the HLOS tried to enable or disable
 816                          * these clocks on a device with such configuration (e.g. because they are
 817                          * enabled but unused during boot-up), the device will most likely decide
 818                          * to reboot.
 819                          * In light of that, we are conservative here and we list all such clocks
 820                          * as protected. The board dts (or a user-supplied dts) can override the
 821                          * list of protected clocks if it differs from the norm, and it is in fact
 822                          * desired for the HLOS to manage these clocks
 823                          */
 824                         protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
 825                                            <SSC_XO>,
 826                                            <SSC_CNOC_AHBS_CLK>;
 827                 };
 828
 829                 rpm_msg_ram: sram@778000 {
 830                         compatible = "qcom,rpm-msg-ram";
 831                         reg = <0x00778000 0x7000>;
 832                 };
 833
 834                 qfprom: qfprom@784000 {
 835                         compatible = "qcom,msm8998-qfprom", "qcom,qfprom";
 836                         reg = <0x00784000 0x621c>;
 837                         #address-cells = <1>;
 838                         #size-cells = <1>;
 839
 840                         qusb2_hstx_trim: hstx-trim@23a {
 841                                 reg = <0x23a 0x1>;
 842                                 bits = <0 4>;
 843                         };
 844                 };
 845
 846                 tsens0: thermal@10ab000 {
 847                         compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
 848                         reg = <0x010ab000 0x1000>, /* TM */
 849                               <0x010aa000 0x1000>; /* SROT */
 850                         #qcom,sensors = <14>;
 851                         interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
 852                                      <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
 853                         interrupt-names = "uplow", "critical";
 854                         #thermal-sensor-cells = <1>;
 855                 };
 856
 857                 tsens1: thermal@10ae000 {
 858                         compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
 859                         reg = <0x010ae000 0x1000>, /* TM */
 860                               <0x010ad000 0x1000>; /* SROT */
 861                         #qcom,sensors = <8>;
 862                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 863                                      <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
 864                         interrupt-names = "uplow", "critical";
 865                         #thermal-sensor-cells = <1>;
 866                 };
 867
 868                 anoc1_smmu: iommu@1680000 {
 869                         compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
 870                         reg = <0x01680000 0x10000>;
 871                         #iommu-cells = <1>;
 872
 873                         #global-interrupts = <0>;
 874                         interrupts =
 875                                 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
 876                                 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
 877                                 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
 878                                 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
 879                                 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
 880                                 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
 881                 };
 882
 883                 anoc2_smmu: iommu@16c0000 {
 884                         compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
 885                         reg = <0x016c0000 0x40000>;
 886                         #iommu-cells = <1>;
 887
 888                         #global-interrupts = <0>;
 889                         interrupts =
 890                                 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
 891                                 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
 892                                 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
 893                                 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
 894                                 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
 895                                 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
 896                                 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
 897                                 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
 898                                 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
 899                                 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
 900                 };
 901
 902                 pcie0: pci@1c00000 {
 903                         compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
 904                         reg =   <0x01c00000 0x2000>,
 905                                 <0x1b000000 0xf1d>,
 906                                 <0x1b000f20 0xa8>,
 907                                 <0x1b100000 0x100000>;
 908                         reg-names = "parf", "dbi", "elbi", "config";
 909                         device_type = "pci";
 910                         linux,pci-domain = <0>;
 911                         bus-range = <0x00 0xff>;
 912                         #address-cells = <3>;
 913                         #size-cells = <2>;
 914                         num-lanes = <1>;
 915                         phys = <&pciephy>;
 916                         phy-names = "pciephy";
 917                         status = "disabled";
 918
 919                         ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
 920                                  <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
 921
 922                         #interrupt-cells = <1>;
 923                         interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
 924                         interrupt-names = "msi";
 925                         interrupt-map-mask = <0 0 0 0x7>;
 926                         interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
 927                                         <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
 928                                         <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
 929                                         <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
 930
 931                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
 932                                  <&gcc GCC_PCIE_0_AUX_CLK>,
 933                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 934                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
 935                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
 936                         clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave";
 937
 938                         power-domains = <&gcc PCIE_0_GDSC>;
 939                         iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
 940                         perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
 941                 };
 942
 943                 pcie_phy: phy@1c06000 {
 944                         compatible = "qcom,msm8998-qmp-pcie-phy";
 945                         reg = <0x01c06000 0x18c>;
 946                         #address-cells = <1>;
 947                         #size-cells = <1>;
 948                         status = "disabled";
 949                         ranges;
 950
 951                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
 952                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 953                                  <&gcc GCC_PCIE_CLKREF_CLK>;
 954                         clock-names = "aux", "cfg_ahb", "ref";
 955
 956                         resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
 957                         reset-names = "phy", "common";
 958
 959                         vdda-phy-supply = <&vreg_l1a_0p875>;
 960                         vdda-pll-supply = <&vreg_l2a_1p2>;
 961
 962                         pciephy: phy@1c06800 {
 963                                 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
 964                                 #phy-cells = <0>;
 965
 966                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
 967                                 clock-names = "pipe0";
 968                                 clock-output-names = "pcie_0_pipe_clk_src";
 969                                 #clock-cells = <0>;
 970                         };
 971                 };
 972
 973                 ufshc: ufshc@1da4000 {
 974                         compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
 975                         reg = <0x01da4000 0x2500>;
 976                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
 977                         phys = <&ufsphy_lanes>;
 978                         phy-names = "ufsphy";
 979                         lanes-per-direction = <2>;
 980                         power-domains = <&gcc UFS_GDSC>;
 981                         status = "disabled";
 982                         #reset-cells = <1>;
 983
 984                         clock-names =
 985                                 "core_clk",
 986                                 "bus_aggr_clk",
 987                                 "iface_clk",
 988                                 "core_clk_unipro",
 989                                 "ref_clk",
 990                                 "tx_lane0_sync_clk",
 991                                 "rx_lane0_sync_clk",
 992                                 "rx_lane1_sync_clk";
 993                         clocks =
 994                                 <&gcc GCC_UFS_AXI_CLK>,
 995                                 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
 996                                 <&gcc GCC_UFS_AHB_CLK>,
 997                                 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
 998                                 <&rpmcc RPM_SMD_LN_BB_CLK1>,
 999                                 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1000                                 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1001                                 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1002                         freq-table-hz =
1003                                 <50000000 200000000>,
1004                                 <0 0>,
1005                                 <0 0>,
1006                                 <37500000 150000000>,
1007                                 <0 0>,
1008                                 <0 0>,
1009                                 <0 0>,
1010                                 <0 0>;
1011
1012                         resets = <&gcc GCC_UFS_BCR>;
1013                         reset-names = "rst";
1014                 };
1015
1016                 ufsphy: phy@1da7000 {
1017                         compatible = "qcom,msm8998-qmp-ufs-phy";
1018                         reg = <0x01da7000 0x18c>;
1019                         #address-cells = <1>;
1020                         #size-cells = <1>;
1021                         status = "disabled";
1022                         ranges;
1023
1024                         clock-names =
1025                                 "ref",
1026                                 "ref_aux";
1027                         clocks =
1028                                 <&gcc GCC_UFS_CLKREF_CLK>,
1029                                 <&gcc GCC_UFS_PHY_AUX_CLK>;
1030
1031                         reset-names = "ufsphy";
1032                         resets = <&ufshc 0>;
1033
1034                         ufsphy_lanes: phy@1da7400 {
1035                                 reg = <0x01da7400 0x128>,
1036                                       <0x01da7600 0x1fc>,
1037                                       <0x01da7c00 0x1dc>,
1038                                       <0x01da7800 0x128>,
1039                                       <0x01da7a00 0x1fc>;
1040                                 #phy-cells = <0>;
1041                         };
1042                 };
1043
1044                 tcsr_mutex: hwlock@1f40000 {
1045                         compatible = "qcom,tcsr-mutex";
1046                         reg = <0x01f40000 0x20000>;
1047                         #hwlock-cells = <1>;
1048                 };
1049
1050                 tcsr_regs_1: syscon@1f60000 {
1051                         compatible = "qcom,msm8998-tcsr", "syscon";
1052                         reg = <0x01f60000 0x20000>;
1053                 };
1054
1055                 tlmm: pinctrl@3400000 {
1056                         compatible = "qcom,msm8998-pinctrl";
1057                         reg = <0x03400000 0xc00000>;
1058                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1059                         gpio-ranges = <&tlmm 0 0 150>;
1060                         gpio-controller;
1061                         #gpio-cells = <2>;
1062                         interrupt-controller;
1063                         #interrupt-cells = <2>;
1064
1065                         sdc2_on: sdc2-on-state {
1066                                 clk-pins {
1067                                         pins = "sdc2_clk";
1068                                         drive-strength = <16>;
1069                                         bias-disable;
1070                                 };
1071
1072                                 cmd-pins {
1073                                         pins = "sdc2_cmd";
1074                                         drive-strength = <10>;
1075                                         bias-pull-up;
1076                                 };
1077
1078                                 data-pins {
1079                                         pins = "sdc2_data";
1080                                         drive-strength = <10>;
1081                                         bias-pull-up;
1082                                 };
1083                         };
1084
1085                         sdc2_off: sdc2-off-state {
1086                                 clk-pins {
1087                                         pins = "sdc2_clk";
1088                                         drive-strength = <2>;
1089                                         bias-disable;
1090                                 };
1091
1092                                 cmd-pins {
1093                                         pins = "sdc2_cmd";
1094                                         drive-strength = <2>;
1095                                         bias-pull-up;
1096                                 };
1097
1098                                 data-pins {
1099                                         pins = "sdc2_data";
1100                                         drive-strength = <2>;
1101                                         bias-pull-up;
1102                                 };
1103                         };
1104
1105                         sdc2_cd: sdc2-cd-state {
1106                                 pins = "gpio95";
1107                                 function = "gpio";
1108                                 bias-pull-up;
1109                                 drive-strength = <2>;
1110                         };
1111
1112                         blsp1_uart3_on: blsp1-uart3-on-state {
1113                                 tx-pins {
1114                                         pins = "gpio45";
1115                                         function = "blsp_uart3_a";
1116                                         drive-strength = <2>;
1117                                         bias-disable;
1118                                 };
1119
1120                                 rx-pins {
1121                                         pins = "gpio46";
1122                                         function = "blsp_uart3_a";
1123                                         drive-strength = <2>;
1124                                         bias-disable;
1125                                 };
1126
1127                                 cts-pins {
1128                                         pins = "gpio47";
1129                                         function = "blsp_uart3_a";
1130                                         drive-strength = <2>;
1131                                         bias-disable;
1132                                 };
1133
1134                                 rfr-pins {
1135                                         pins = "gpio48";
1136                                         function = "blsp_uart3_a";
1137                                         drive-strength = <2>;
1138                                         bias-disable;
1139                                 };
1140                         };
1141
1142                         blsp1_i2c1_default: blsp1-i2c1-default-state {
1143                                 pins = "gpio2", "gpio3";
1144                                 function = "blsp_i2c1";
1145                                 drive-strength = <2>;
1146                                 bias-disable;
1147                         };
1148
1149                         blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state {
1150                                 pins = "gpio2", "gpio3";
1151                                 function = "blsp_i2c1";
1152                                 drive-strength = <2>;
1153                                 bias-pull-up;
1154                         };
1155
1156                         blsp1_i2c2_default: blsp1-i2c2-default-state {
1157                                 pins = "gpio32", "gpio33";
1158                                 function = "blsp_i2c2";
1159                                 drive-strength = <2>;
1160                                 bias-disable;
1161                         };
1162
1163                         blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state {
1164                                 pins = "gpio32", "gpio33";
1165                                 function = "blsp_i2c2";
1166                                 drive-strength = <2>;
1167                                 bias-pull-up;
1168                         };
1169
1170                         blsp1_i2c3_default: blsp1-i2c3-default-state {
1171                                 pins = "gpio47", "gpio48";
1172                                 function = "blsp_i2c3";
1173                                 drive-strength = <2>;
1174                                 bias-disable;
1175                         };
1176
1177                         blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1178                                 pins = "gpio47", "gpio48";
1179                                 function = "blsp_i2c3";
1180                                 drive-strength = <2>;
1181                                 bias-pull-up;
1182                         };
1183
1184                         blsp1_i2c4_default: blsp1-i2c4-default-state {
1185                                 pins = "gpio10", "gpio11";
1186                                 function = "blsp_i2c4";
1187                                 drive-strength = <2>;
1188                                 bias-disable;
1189                         };
1190
1191                         blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
1192                                 pins = "gpio10", "gpio11";
1193                                 function = "blsp_i2c4";
1194                                 drive-strength = <2>;
1195                                 bias-pull-up;
1196                         };
1197
1198                         blsp1_i2c5_default: blsp1-i2c5-default-state {
1199                                 pins = "gpio87", "gpio88";
1200                                 function = "blsp_i2c5";
1201                                 drive-strength = <2>;
1202                                 bias-disable;
1203                         };
1204
1205                         blsp1_i2c5_sleep: blsp1-i2c5-sleep-state {
1206                                 pins = "gpio87", "gpio88";
1207                                 function = "blsp_i2c5";
1208                                 drive-strength = <2>;
1209                                 bias-pull-up;
1210                         };
1211
1212                         blsp1_i2c6_default: blsp1-i2c6-default-state {
1213                                 pins = "gpio43", "gpio44";
1214                                 function = "blsp_i2c6";
1215                                 drive-strength = <2>;
1216                                 bias-disable;
1217                         };
1218
1219                         blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1220                                 pins = "gpio43", "gpio44";
1221                                 function = "blsp_i2c6";
1222                                 drive-strength = <2>;
1223                                 bias-pull-up;
1224                         };
1225                         /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1226                         blsp2_i2c1_default: blsp2-i2c1-default-state {
1227                                 pins = "gpio55", "gpio56";
1228                                 function = "blsp_i2c7";
1229                                 drive-strength = <2>;
1230                                 bias-disable;
1231                         };
1232
1233                         blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1234                                 pins = "gpio55", "gpio56";
1235                                 function = "blsp_i2c7";
1236                                 drive-strength = <2>;
1237                                 bias-pull-up;
1238                         };
1239
1240                         blsp2_i2c2_default: blsp2-i2c2-default-state {
1241                                 pins = "gpio6", "gpio7";
1242                                 function = "blsp_i2c8";
1243                                 drive-strength = <2>;
1244                                 bias-disable;
1245                         };
1246
1247                         blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1248                                 pins = "gpio6", "gpio7";
1249                                 function = "blsp_i2c8";
1250                                 drive-strength = <2>;
1251                                 bias-pull-up;
1252                         };
1253
1254                         blsp2_i2c3_default: blsp2-i2c3-default-state {
1255                                 pins = "gpio51", "gpio52";
1256                                 function = "blsp_i2c9";
1257                                 drive-strength = <2>;
1258                                 bias-disable;
1259                         };
1260
1261                         blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1262                                 pins = "gpio51", "gpio52";
1263                                 function = "blsp_i2c9";
1264                                 drive-strength = <2>;
1265                                 bias-pull-up;
1266                         };
1267
1268                         blsp2_i2c4_default: blsp2-i2c4-default-state {
1269                                 pins = "gpio67", "gpio68";
1270                                 function = "blsp_i2c10";
1271                                 drive-strength = <2>;
1272                                 bias-disable;
1273                         };
1274
1275                         blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
1276                                 pins = "gpio67", "gpio68";
1277                                 function = "blsp_i2c10";
1278                                 drive-strength = <2>;
1279                                 bias-pull-up;
1280                         };
1281
1282                         blsp2_i2c5_default: blsp2-i2c5-default-state {
1283                                 pins = "gpio60", "gpio61";
1284                                 function = "blsp_i2c11";
1285                                 drive-strength = <2>;
1286                                 bias-disable;
1287                         };
1288
1289                         blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1290                                 pins = "gpio60", "gpio61";
1291                                 function = "blsp_i2c11";
1292                                 drive-strength = <2>;
1293                                 bias-pull-up;
1294                         };
1295
1296                         blsp2_i2c6_default: blsp2-i2c6-default-state {
1297                                 pins = "gpio83", "gpio84";
1298                                 function = "blsp_i2c12";
1299                                 drive-strength = <2>;
1300                                 bias-disable;
1301                         };
1302
1303                         blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1304                                 pins = "gpio83", "gpio84";
1305                                 function = "blsp_i2c12";
1306                                 drive-strength = <2>;
1307                                 bias-pull-up;
1308                         };
1309                 };
1310
1311                 remoteproc_mss: remoteproc@4080000 {
1312                         compatible = "qcom,msm8998-mss-pil";
1313                         reg = <0x04080000 0x100>, <0x04180000 0x20>;
1314                         reg-names = "qdsp6", "rmb";
1315
1316                         interrupts-extended =
1317                                 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1318                                 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1319                                 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1320                                 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1321                                 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1322                                 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1323                         interrupt-names = "wdog", "fatal", "ready",
1324                                           "handover", "stop-ack",
1325                                           "shutdown-ack";
1326
1327                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1328                                  <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1329                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
1330                                  <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1331                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
1332                                  <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1333                                  <&rpmcc RPM_SMD_QDSS_CLK>,
1334                                  <&rpmcc RPM_SMD_XO_CLK_SRC>;
1335                         clock-names = "iface", "bus", "mem", "gpll0_mss",
1336                                       "snoc_axi", "mnoc_axi", "qdss", "xo";
1337
1338                         qcom,smem-states = <&modem_smp2p_out 0>;
1339                         qcom,smem-state-names = "stop";
1340
1341                         resets = <&gcc GCC_MSS_RESTART>;
1342                         reset-names = "mss_restart";
1343
1344                         qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1345
1346                         power-domains = <&rpmpd MSM8998_VDDCX>,
1347                                         <&rpmpd MSM8998_VDDMX>;
1348                         power-domain-names = "cx", "mx";
1349
1350                         status = "disabled";
1351
1352                         mba {
1353                                 memory-region = <&mba_mem>;
1354                         };
1355
1356                         mpss {
1357                                 memory-region = <&mpss_mem>;
1358                         };
1359
1360                         glink-edge {
1361                                 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1362                                 label = "modem";
1363                                 qcom,remote-pid = <1>;
1364                                 mboxes = <&apcs_glb 15>;
1365                         };
1366                 };
1367
1368                 adreno_gpu: gpu@5000000 {
1369                         compatible = "qcom,adreno-540.1", "qcom,adreno";
1370                         reg = <0x05000000 0x40000>;
1371                         reg-names = "kgsl_3d0_reg_memory";
1372
1373                         clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1374                                 <&gpucc RBBMTIMER_CLK>,
1375                                 <&gcc GCC_BIMC_GFX_CLK>,
1376                                 <&gcc GCC_GPU_BIMC_GFX_CLK>,
1377                                 <&gpucc RBCPR_CLK>,
1378                                 <&gpucc GFX3D_CLK>;
1379                         clock-names = "iface",
1380                                 "rbbmtimer",
1381                                 "mem",
1382                                 "mem_iface",
1383                                 "rbcpr",
1384                                 "core";
1385
1386                         interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1387                         iommus = <&adreno_smmu 0>;
1388                         operating-points-v2 = <&gpu_opp_table>;
1389                         power-domains = <&rpmpd MSM8998_VDDMX>;
1390                         status = "disabled";
1391
1392                         gpu_opp_table: opp-table {
1393                                 compatible = "operating-points-v2";
1394                                 opp-710000097 {
1395                                         opp-hz = /bits/ 64 <710000097>;
1396                                         opp-level = <RPM_SMD_LEVEL_TURBO>;
1397                                         opp-supported-hw = <0xFF>;
1398                                 };
1399
1400                                 opp-670000048 {
1401                                         opp-hz = /bits/ 64 <670000048>;
1402                                         opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1403                                         opp-supported-hw = <0xFF>;
1404                                 };
1405
1406                                 opp-596000097 {
1407                                         opp-hz = /bits/ 64 <596000097>;
1408                                         opp-level = <RPM_SMD_LEVEL_NOM>;
1409                                         opp-supported-hw = <0xFF>;
1410                                 };
1411
1412                                 opp-515000097 {
1413                                         opp-hz = /bits/ 64 <515000097>;
1414                                         opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1415                                         opp-supported-hw = <0xFF>;
1416                                 };
1417
1418                                 opp-414000000 {
1419                                         opp-hz = /bits/ 64 <414000000>;
1420                                         opp-level = <RPM_SMD_LEVEL_SVS>;
1421                                         opp-supported-hw = <0xFF>;
1422                                 };
1423
1424                                 opp-342000000 {
1425                                         opp-hz = /bits/ 64 <342000000>;
1426                                         opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1427                                         opp-supported-hw = <0xFF>;
1428                                 };
1429
1430                                 opp-257000000 {
1431                                         opp-hz = /bits/ 64 <257000000>;
1432                                         opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1433                                         opp-supported-hw = <0xFF>;
1434                                 };
1435                         };
1436                 };
1437
1438                 adreno_smmu: iommu@5040000 {
1439                         compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1440                         reg = <0x05040000 0x10000>;
1441                         clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1442                                  <&gcc GCC_BIMC_GFX_CLK>,
1443                                  <&gcc GCC_GPU_BIMC_GFX_CLK>;
1444                         clock-names = "iface", "mem", "mem_iface";
1445
1446                         #global-interrupts = <0>;
1447                         #iommu-cells = <1>;
1448                         interrupts =
1449                                 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1450                                 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1451                                 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1452                         /*
1453                          * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
1454                          * GPU-CX for SMMU but we need both of them up for Adreno.
1455                          * Contemporarily, we also need to manage the VDDMX rpmpd
1456                          * domain in the Adreno driver.
1457                          * Enable GPU CX/GX GDSCs here so that we can manage the
1458                          * SoC VDDMX RPM Power Domain in the Adreno driver.
1459                          */
1460                         power-domains = <&gpucc GPU_GX_GDSC>;
1461                         status = "disabled";
1462                 };
1463
1464                 gpucc: clock-controller@5065000 {
1465                         compatible = "qcom,msm8998-gpucc";
1466                         #clock-cells = <1>;
1467                         #reset-cells = <1>;
1468                         #power-domain-cells = <1>;
1469                         reg = <0x05065000 0x9000>;
1470
1471                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1472                                  <&gcc GPLL0_OUT_MAIN>;
1473                         clock-names = "xo",
1474                                       "gpll0";
1475                 };
1476
1477                 remoteproc_slpi: remoteproc@5800000 {
1478                         compatible = "qcom,msm8998-slpi-pas";
1479                         reg = <0x05800000 0x4040>;
1480
1481                         interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1482                                               <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1483                                               <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1484                                               <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1485                                               <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1486                         interrupt-names = "wdog", "fatal", "ready",
1487                                           "handover", "stop-ack";
1488
1489                         px-supply = <&vreg_lvs2a_1p8>;
1490
1491                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1492                                  <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
1493                         clock-names = "xo", "aggre2";
1494
1495                         memory-region = <&slpi_mem>;
1496
1497                         qcom,smem-states = <&slpi_smp2p_out 0>;
1498                         qcom,smem-state-names = "stop";
1499
1500                         power-domains = <&rpmpd MSM8998_SSCCX>;
1501                         power-domain-names = "ssc_cx";
1502
1503                         status = "disabled";
1504
1505                         glink-edge {
1506                                 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
1507                                 label = "dsps";
1508                                 qcom,remote-pid = <3>;
1509                                 mboxes = <&apcs_glb 27>;
1510                         };
1511                 };
1512
1513                 stm: stm@6002000 {
1514                         compatible = "arm,coresight-stm", "arm,primecell";
1515                         reg = <0x06002000 0x1000>,
1516                               <0x16280000 0x180000>;
1517                         reg-names = "stm-base", "stm-data-base";
1518                         status = "disabled";
1519
1520                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1521                         clock-names = "apb_pclk", "atclk";
1522
1523                         out-ports {
1524                                 port {
1525                                         stm_out: endpoint {
1526                                                 remote-endpoint = <&funnel0_in7>;
1527                                         };
1528                                 };
1529                         };
1530                 };
1531
1532                 funnel1: funnel@6041000 {
1533                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1534                         reg = <0x06041000 0x1000>;
1535                         status = "disabled";
1536
1537                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1538                         clock-names = "apb_pclk", "atclk";
1539
1540                         out-ports {
1541                                 port {
1542                                         funnel0_out: endpoint {
1543                                                 remote-endpoint =
1544                                                   <&merge_funnel_in0>;
1545                                         };
1546                                 };
1547                         };
1548
1549                         in-ports {
1550                                 #address-cells = <1>;
1551                                 #size-cells = <0>;
1552
1553                                 port@7 {
1554                                         reg = <7>;
1555                                         funnel0_in7: endpoint {
1556                                                 remote-endpoint = <&stm_out>;
1557                                         };
1558                                 };
1559                         };
1560                 };
1561
1562                 funnel2: funnel@6042000 {
1563                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1564                         reg = <0x06042000 0x1000>;
1565                         status = "disabled";
1566
1567                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1568                         clock-names = "apb_pclk", "atclk";
1569
1570                         out-ports {
1571                                 port {
1572                                         funnel1_out: endpoint {
1573                                                 remote-endpoint =
1574                                                   <&merge_funnel_in1>;
1575                                         };
1576                                 };
1577                         };
1578
1579                         in-ports {
1580                                 #address-cells = <1>;
1581                                 #size-cells = <0>;
1582
1583                                 port@6 {
1584                                         reg = <6>;
1585                                         funnel1_in6: endpoint {
1586                                                 remote-endpoint =
1587                                                   <&apss_merge_funnel_out>;
1588                                         };
1589                                 };
1590                         };
1591                 };
1592
1593                 funnel3: funnel@6045000 {
1594                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1595                         reg = <0x06045000 0x1000>;
1596                         status = "disabled";
1597
1598                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1599                         clock-names = "apb_pclk", "atclk";
1600
1601                         out-ports {
1602                                 port {
1603                                         merge_funnel_out: endpoint {
1604                                                 remote-endpoint =
1605                                                   <&etf_in>;
1606                                         };
1607                                 };
1608                         };
1609
1610                         in-ports {
1611                                 #address-cells = <1>;
1612                                 #size-cells = <0>;
1613
1614                                 port@0 {
1615                                         reg = <0>;
1616                                         merge_funnel_in0: endpoint {
1617                                                 remote-endpoint =
1618                                                   <&funnel0_out>;
1619                                         };
1620                                 };
1621
1622                                 port@1 {
1623                                         reg = <1>;
1624                                         merge_funnel_in1: endpoint {
1625                                                 remote-endpoint =
1626                                                   <&funnel1_out>;
1627                                         };
1628                                 };
1629                         };
1630                 };
1631
1632                 replicator1: replicator@6046000 {
1633                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1634                         reg = <0x06046000 0x1000>;
1635                         status = "disabled";
1636
1637                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1638                         clock-names = "apb_pclk", "atclk";
1639
1640                         out-ports {
1641                                 port {
1642                                         replicator_out: endpoint {
1643                                                 remote-endpoint = <&etr_in>;
1644                                         };
1645                                 };
1646                         };
1647
1648                         in-ports {
1649                                 port {
1650                                         replicator_in: endpoint {
1651                                                 remote-endpoint = <&etf_out>;
1652                                         };
1653                                 };
1654                         };
1655                 };
1656
1657                 etf: etf@6047000 {
1658                         compatible = "arm,coresight-tmc", "arm,primecell";
1659                         reg = <0x06047000 0x1000>;
1660                         status = "disabled";
1661
1662                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1663                         clock-names = "apb_pclk", "atclk";
1664
1665                         out-ports {
1666                                 port {
1667                                         etf_out: endpoint {
1668                                                 remote-endpoint =
1669                                                   <&replicator_in>;
1670                                         };
1671                                 };
1672                         };
1673
1674                         in-ports {
1675                                 port {
1676                                         etf_in: endpoint {
1677                                                 remote-endpoint =
1678                                                   <&merge_funnel_out>;
1679                                         };
1680                                 };
1681                         };
1682                 };
1683
1684                 etr: etr@6048000 {
1685                         compatible = "arm,coresight-tmc", "arm,primecell";
1686                         reg = <0x06048000 0x1000>;
1687                         status = "disabled";
1688
1689                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1690                         clock-names = "apb_pclk", "atclk";
1691                         arm,scatter-gather;
1692
1693                         in-ports {
1694                                 port {
1695                                         etr_in: endpoint {
1696                                                 remote-endpoint =
1697                                                   <&replicator_out>;
1698                                         };
1699                                 };
1700                         };
1701                 };
1702
1703                 etm1: etm@7840000 {
1704                         compatible = "arm,coresight-etm4x", "arm,primecell";
1705                         reg = <0x07840000 0x1000>;
1706                         status = "disabled";
1707
1708                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1709                         clock-names = "apb_pclk", "atclk";
1710
1711                         cpu = <&CPU0>;
1712
1713                         out-ports {
1714                                 port {
1715                                         etm0_out: endpoint {
1716                                                 remote-endpoint =
1717                                                   <&apss_funnel_in0>;
1718                                         };
1719                                 };
1720                         };
1721                 };
1722
1723                 etm2: etm@7940000 {
1724                         compatible = "arm,coresight-etm4x", "arm,primecell";
1725                         reg = <0x07940000 0x1000>;
1726                         status = "disabled";
1727
1728                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1729                         clock-names = "apb_pclk", "atclk";
1730
1731                         cpu = <&CPU1>;
1732
1733                         out-ports {
1734                                 port {
1735                                         etm1_out: endpoint {
1736                                                 remote-endpoint =
1737                                                   <&apss_funnel_in1>;
1738                                         };
1739                                 };
1740                         };
1741                 };
1742
1743                 etm3: etm@7a40000 {
1744                         compatible = "arm,coresight-etm4x", "arm,primecell";
1745                         reg = <0x07a40000 0x1000>;
1746                         status = "disabled";
1747
1748                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1749                         clock-names = "apb_pclk", "atclk";
1750
1751                         cpu = <&CPU2>;
1752
1753                         out-ports {
1754                                 port {
1755                                         etm2_out: endpoint {
1756                                                 remote-endpoint =
1757                                                   <&apss_funnel_in2>;
1758                                         };
1759                                 };
1760                         };
1761                 };
1762
1763                 etm4: etm@7b40000 {
1764                         compatible = "arm,coresight-etm4x", "arm,primecell";
1765                         reg = <0x07b40000 0x1000>;
1766                         status = "disabled";
1767
1768                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1769                         clock-names = "apb_pclk", "atclk";
1770
1771                         cpu = <&CPU3>;
1772
1773                         out-ports {
1774                                 port {
1775                                         etm3_out: endpoint {
1776                                                 remote-endpoint =
1777                                                   <&apss_funnel_in3>;
1778                                         };
1779                                 };
1780                         };
1781                 };
1782
1783                 funnel4: funnel@7b60000 { /* APSS Funnel */
1784                         compatible = "arm,coresight-etm4x", "arm,primecell";
1785                         reg = <0x07b60000 0x1000>;
1786                         status = "disabled";
1787
1788                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1789                         clock-names = "apb_pclk", "atclk";
1790
1791                         out-ports {
1792                                 port {
1793                                         apss_funnel_out: endpoint {
1794                                                 remote-endpoint =
1795                                                   <&apss_merge_funnel_in>;
1796                                         };
1797                                 };
1798                         };
1799
1800                         in-ports {
1801                                 #address-cells = <1>;
1802                                 #size-cells = <0>;
1803
1804                                 port@0 {
1805                                         reg = <0>;
1806                                         apss_funnel_in0: endpoint {
1807                                                 remote-endpoint =
1808                                                   <&etm0_out>;
1809                                         };
1810                                 };
1811
1812                                 port@1 {
1813                                         reg = <1>;
1814                                         apss_funnel_in1: endpoint {
1815                                                 remote-endpoint =
1816                                                   <&etm1_out>;
1817                                         };
1818                                 };
1819
1820                                 port@2 {
1821                                         reg = <2>;
1822                                         apss_funnel_in2: endpoint {
1823                                                 remote-endpoint =
1824                                                   <&etm2_out>;
1825                                         };
1826                                 };
1827
1828                                 port@3 {
1829                                         reg = <3>;
1830                                         apss_funnel_in3: endpoint {
1831                                                 remote-endpoint =
1832                                                   <&etm3_out>;
1833                                         };
1834                                 };
1835
1836                                 port@4 {
1837                                         reg = <4>;
1838                                         apss_funnel_in4: endpoint {
1839                                                 remote-endpoint =
1840                                                   <&etm4_out>;
1841                                         };
1842                                 };
1843
1844                                 port@5 {
1845                                         reg = <5>;
1846                                         apss_funnel_in5: endpoint {
1847                                                 remote-endpoint =
1848                                                   <&etm5_out>;
1849                                         };
1850                                 };
1851
1852                                 port@6 {
1853                                         reg = <6>;
1854                                         apss_funnel_in6: endpoint {
1855                                                 remote-endpoint =
1856                                                   <&etm6_out>;
1857                                         };
1858                                 };
1859
1860                                 port@7 {
1861                                         reg = <7>;
1862                                         apss_funnel_in7: endpoint {
1863                                                 remote-endpoint =
1864                                                   <&etm7_out>;
1865                                         };
1866                                 };
1867                         };
1868                 };
1869
1870                 funnel5: funnel@7b70000 {
1871                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1872                         reg = <0x07b70000 0x1000>;
1873                         status = "disabled";
1874
1875                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1876                         clock-names = "apb_pclk", "atclk";
1877
1878                         out-ports {
1879                                 port {
1880                                         apss_merge_funnel_out: endpoint {
1881                                                 remote-endpoint =
1882                                                   <&funnel1_in6>;
1883                                         };
1884                                 };
1885                         };
1886
1887                         in-ports {
1888                                 port {
1889                                         apss_merge_funnel_in: endpoint {
1890                                                 remote-endpoint =
1891                                                   <&apss_funnel_out>;
1892                                         };
1893                                 };
1894                         };
1895                 };
1896
1897                 etm5: etm@7c40000 {
1898                         compatible = "arm,coresight-etm4x", "arm,primecell";
1899                         reg = <0x07c40000 0x1000>;
1900                         status = "disabled";
1901
1902                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1903                         clock-names = "apb_pclk", "atclk";
1904
1905                         cpu = <&CPU4>;
1906
1907                         port {
1908                                 etm4_out: endpoint {
1909                                         remote-endpoint = <&apss_funnel_in4>;
1910                                 };
1911                         };
1912                 };
1913
1914                 etm6: etm@7d40000 {
1915                         compatible = "arm,coresight-etm4x", "arm,primecell";
1916                         reg = <0x07d40000 0x1000>;
1917                         status = "disabled";
1918
1919                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1920                         clock-names = "apb_pclk", "atclk";
1921
1922                         cpu = <&CPU5>;
1923
1924                         port {
1925                                 etm5_out: endpoint {
1926                                         remote-endpoint = <&apss_funnel_in5>;
1927                                 };
1928                         };
1929                 };
1930
1931                 etm7: etm@7e40000 {
1932                         compatible = "arm,coresight-etm4x", "arm,primecell";
1933                         reg = <0x07e40000 0x1000>;
1934                         status = "disabled";
1935
1936                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1937                         clock-names = "apb_pclk", "atclk";
1938
1939                         cpu = <&CPU6>;
1940
1941                         port {
1942                                 etm6_out: endpoint {
1943                                         remote-endpoint = <&apss_funnel_in6>;
1944                                 };
1945                         };
1946                 };
1947
1948                 etm8: etm@7f40000 {
1949                         compatible = "arm,coresight-etm4x", "arm,primecell";
1950                         reg = <0x07f40000 0x1000>;
1951                         status = "disabled";
1952
1953                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1954                         clock-names = "apb_pclk", "atclk";
1955
1956                         cpu = <&CPU7>;
1957
1958                         port {
1959                                 etm7_out: endpoint {
1960                                         remote-endpoint = <&apss_funnel_in7>;
1961                                 };
1962                         };
1963                 };
1964
1965                 sram@290000 {
1966                         compatible = "qcom,rpm-stats";
1967                         reg = <0x00290000 0x10000>;
1968                 };
1969
1970                 spmi_bus: spmi@800f000 {
1971                         compatible = "qcom,spmi-pmic-arb";
1972                         reg =   <0x0800f000 0x1000>,
1973                                 <0x08400000 0x1000000>,
1974                                 <0x09400000 0x1000000>,
1975                                 <0x0a400000 0x220000>,
1976                                 <0x0800a000 0x3000>;
1977                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1978                         interrupt-names = "periph_irq";
1979                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1980                         qcom,ee = <0>;
1981                         qcom,channel = <0>;
1982                         #address-cells = <2>;
1983                         #size-cells = <0>;
1984                         interrupt-controller;
1985                         #interrupt-cells = <4>;
1986                         cell-index = <0>;
1987                 };
1988
1989                 usb3: usb@a8f8800 {
1990                         compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
1991                         reg = <0x0a8f8800 0x400>;
1992                         status = "disabled";
1993                         #address-cells = <1>;
1994                         #size-cells = <1>;
1995                         ranges;
1996
1997                         clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
1998                                  <&gcc GCC_USB30_MASTER_CLK>,
1999                                  <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
2000                                  <&gcc GCC_USB30_SLEEP_CLK>,
2001                                  <&gcc GCC_USB30_MOCK_UTMI_CLK>;
2002                         clock-names = "cfg_noc",
2003                                       "core",
2004                                       "iface",
2005                                       "sleep",
2006                                       "mock_utmi";
2007
2008                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2009                                           <&gcc GCC_USB30_MASTER_CLK>;
2010                         assigned-clock-rates = <19200000>, <120000000>;
2011
2012                         interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2013                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2014                         interrupt-names = "hs_phy_irq", "ss_phy_irq";
2015
2016                         power-domains = <&gcc USB_30_GDSC>;
2017
2018                         resets = <&gcc GCC_USB_30_BCR>;
2019
2020                         usb3_dwc3: usb@a800000 {
2021                                 compatible = "snps,dwc3";
2022                                 reg = <0x0a800000 0xcd00>;
2023                                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2024                                 snps,dis_u2_susphy_quirk;
2025                                 snps,dis_enblslpm_quirk;
2026                                 phys = <&qusb2phy>, <&usb1_ssphy>;
2027                                 phy-names = "usb2-phy", "usb3-phy";
2028                                 snps,has-lpm-erratum;
2029                                 snps,hird-threshold = /bits/ 8 <0x10>;
2030                         };
2031                 };
2032
2033                 usb3phy: phy@c010000 {
2034                         compatible = "qcom,msm8998-qmp-usb3-phy";
2035                         reg = <0x0c010000 0x18c>;
2036                         status = "disabled";
2037                         #address-cells = <1>;
2038                         #size-cells = <1>;
2039                         ranges;
2040
2041                         clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2042                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2043                                  <&gcc GCC_USB3_CLKREF_CLK>;
2044                         clock-names = "aux", "cfg_ahb", "ref";
2045
2046                         resets = <&gcc GCC_USB3_PHY_BCR>,
2047                                  <&gcc GCC_USB3PHY_PHY_BCR>;
2048                         reset-names = "phy", "common";
2049
2050                         usb1_ssphy: phy@c010200 {
2051                                 reg = <0xc010200 0x128>,
2052                                       <0xc010400 0x200>,
2053                                       <0xc010c00 0x20c>,
2054                                       <0xc010600 0x128>,
2055                                       <0xc010800 0x200>;
2056                                 #phy-cells = <0>;
2057                                 #clock-cells = <0>;
2058                                 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
2059                                 clock-names = "pipe0";
2060                                 clock-output-names = "usb3_phy_pipe_clk_src";
2061                         };
2062                 };
2063
2064                 qusb2phy: phy@c012000 {
2065                         compatible = "qcom,msm8998-qusb2-phy";
2066                         reg = <0x0c012000 0x2a8>;
2067                         status = "disabled";
2068                         #phy-cells = <0>;
2069
2070                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2071                                  <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2072                         clock-names = "cfg_ahb", "ref";
2073
2074                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2075
2076                         nvmem-cells = <&qusb2_hstx_trim>;
2077                 };
2078
2079                 sdhc2: mmc@c0a4900 {
2080                         compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4";
2081                         reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2082                         reg-names = "hc", "core";
2083
2084                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2085                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2086                         interrupt-names = "hc_irq", "pwr_irq";
2087
2088                         clock-names = "iface", "core", "xo";
2089                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2090                                  <&gcc GCC_SDCC2_APPS_CLK>,
2091                                  <&xo>;
2092                         bus-width = <4>;
2093                         status = "disabled";
2094                 };
2095
2096                 blsp1_dma: dma-controller@c144000 {
2097                         compatible = "qcom,bam-v1.7.0";
2098                         reg = <0x0c144000 0x25000>;
2099                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2100                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2101                         clock-names = "bam_clk";
2102                         #dma-cells = <1>;
2103                         qcom,ee = <0>;
2104                         qcom,controlled-remotely;
2105                         num-channels = <18>;
2106                         qcom,num-ees = <4>;
2107                 };
2108
2109                 blsp1_uart3: serial@c171000 {
2110                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2111                         reg = <0x0c171000 0x1000>;
2112                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
2113                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2114                                  <&gcc GCC_BLSP1_AHB_CLK>;
2115                         clock-names = "core", "iface";
2116                         dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
2117                         dma-names = "tx", "rx";
2118                         pinctrl-names = "default";
2119                         pinctrl-0 = <&blsp1_uart3_on>;
2120                         status = "disabled";
2121                 };
2122
2123                 blsp1_i2c1: i2c@c175000 {
2124                         compatible = "qcom,i2c-qup-v2.2.1";
2125                         reg = <0x0c175000 0x600>;
2126                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2127
2128                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2129                                  <&gcc GCC_BLSP1_AHB_CLK>;
2130                         clock-names = "core", "iface";
2131                         dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2132                         dma-names = "tx", "rx";
2133                         pinctrl-names = "default", "sleep";
2134                         pinctrl-0 = <&blsp1_i2c1_default>;
2135                         pinctrl-1 = <&blsp1_i2c1_sleep>;
2136                         clock-frequency = <400000>;
2137
2138                         status = "disabled";
2139                         #address-cells = <1>;
2140                         #size-cells = <0>;
2141                 };
2142
2143                 blsp1_i2c2: i2c@c176000 {
2144                         compatible = "qcom,i2c-qup-v2.2.1";
2145                         reg = <0x0c176000 0x600>;
2146                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2147
2148                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2149                                  <&gcc GCC_BLSP1_AHB_CLK>;
2150                         clock-names = "core", "iface";
2151                         dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2152                         dma-names = "tx", "rx";
2153                         pinctrl-names = "default", "sleep";
2154                         pinctrl-0 = <&blsp1_i2c2_default>;
2155                         pinctrl-1 = <&blsp1_i2c2_sleep>;
2156                         clock-frequency = <400000>;
2157
2158                         status = "disabled";
2159                         #address-cells = <1>;
2160                         #size-cells = <0>;
2161                 };
2162
2163                 blsp1_i2c3: i2c@c177000 {
2164                         compatible = "qcom,i2c-qup-v2.2.1";
2165                         reg = <0x0c177000 0x600>;
2166                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2167
2168                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2169                                  <&gcc GCC_BLSP1_AHB_CLK>;
2170                         clock-names = "core", "iface";
2171                         dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2172                         dma-names = "tx", "rx";
2173                         pinctrl-names = "default", "sleep";
2174                         pinctrl-0 = <&blsp1_i2c3_default>;
2175                         pinctrl-1 = <&blsp1_i2c3_sleep>;
2176                         clock-frequency = <400000>;
2177
2178                         status = "disabled";
2179                         #address-cells = <1>;
2180                         #size-cells = <0>;
2181                 };
2182
2183                 blsp1_i2c4: i2c@c178000 {
2184                         compatible = "qcom,i2c-qup-v2.2.1";
2185                         reg = <0x0c178000 0x600>;
2186                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2187
2188                         clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2189                                  <&gcc GCC_BLSP1_AHB_CLK>;
2190                         clock-names = "core", "iface";
2191                         dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2192                         dma-names = "tx", "rx";
2193                         pinctrl-names = "default", "sleep";
2194                         pinctrl-0 = <&blsp1_i2c4_default>;
2195                         pinctrl-1 = <&blsp1_i2c4_sleep>;
2196                         clock-frequency = <400000>;
2197
2198                         status = "disabled";
2199                         #address-cells = <1>;
2200                         #size-cells = <0>;
2201                 };
2202
2203                 blsp1_i2c5: i2c@c179000 {
2204                         compatible = "qcom,i2c-qup-v2.2.1";
2205                         reg = <0x0c179000 0x600>;
2206                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2207
2208                         clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2209                                  <&gcc GCC_BLSP1_AHB_CLK>;
2210                         clock-names = "core", "iface";
2211                         dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2212                         dma-names = "tx", "rx";
2213                         pinctrl-names = "default", "sleep";
2214                         pinctrl-0 = <&blsp1_i2c5_default>;
2215                         pinctrl-1 = <&blsp1_i2c5_sleep>;
2216                         clock-frequency = <400000>;
2217
2218                         status = "disabled";
2219                         #address-cells = <1>;
2220                         #size-cells = <0>;
2221                 };
2222
2223                 blsp1_i2c6: i2c@c17a000 {
2224                         compatible = "qcom,i2c-qup-v2.2.1";
2225                         reg = <0x0c17a000 0x600>;
2226                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2227
2228                         clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2229                                  <&gcc GCC_BLSP1_AHB_CLK>;
2230                         clock-names = "core", "iface";
2231                         dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2232                         dma-names = "tx", "rx";
2233                         pinctrl-names = "default", "sleep";
2234                         pinctrl-0 = <&blsp1_i2c6_default>;
2235                         pinctrl-1 = <&blsp1_i2c6_sleep>;
2236                         clock-frequency = <400000>;
2237
2238                         status = "disabled";
2239                         #address-cells = <1>;
2240                         #size-cells = <0>;
2241                 };
2242
2243                 blsp2_dma: dma-controller@c184000 {
2244                         compatible = "qcom,bam-v1.7.0";
2245                         reg = <0x0c184000 0x25000>;
2246                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2247                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2248                         clock-names = "bam_clk";
2249                         #dma-cells = <1>;
2250                         qcom,ee = <0>;
2251                         qcom,controlled-remotely;
2252                         num-channels = <18>;
2253                         qcom,num-ees = <4>;
2254                 };
2255
2256                 blsp2_uart1: serial@c1b0000 {
2257                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2258                         reg = <0x0c1b0000 0x1000>;
2259                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2260                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2261                                  <&gcc GCC_BLSP2_AHB_CLK>;
2262                         clock-names = "core", "iface";
2263                         status = "disabled";
2264                 };
2265
2266                 blsp2_i2c1: i2c@c1b5000 {
2267                         compatible = "qcom,i2c-qup-v2.2.1";
2268                         reg = <0x0c1b5000 0x600>;
2269                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2270
2271                         clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2272                                  <&gcc GCC_BLSP2_AHB_CLK>;
2273                         clock-names = "core", "iface";
2274                         dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2275                         dma-names = "tx", "rx";
2276                         pinctrl-names = "default", "sleep";
2277                         pinctrl-0 = <&blsp2_i2c1_default>;
2278                         pinctrl-1 = <&blsp2_i2c1_sleep>;
2279                         clock-frequency = <400000>;
2280
2281                         status = "disabled";
2282                         #address-cells = <1>;
2283                         #size-cells = <0>;
2284                 };
2285
2286                 blsp2_i2c2: i2c@c1b6000 {
2287                         compatible = "qcom,i2c-qup-v2.2.1";
2288                         reg = <0x0c1b6000 0x600>;
2289                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2290
2291                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2292                                  <&gcc GCC_BLSP2_AHB_CLK>;
2293                         clock-names = "core", "iface";
2294                         dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2295                         dma-names = "tx", "rx";
2296                         pinctrl-names = "default", "sleep";
2297                         pinctrl-0 = <&blsp2_i2c2_default>;
2298                         pinctrl-1 = <&blsp2_i2c2_sleep>;
2299                         clock-frequency = <400000>;
2300
2301                         status = "disabled";
2302                         #address-cells = <1>;
2303                         #size-cells = <0>;
2304                 };
2305
2306                 blsp2_i2c3: i2c@c1b7000 {
2307                         compatible = "qcom,i2c-qup-v2.2.1";
2308                         reg = <0x0c1b7000 0x600>;
2309                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2310
2311                         clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2312                                  <&gcc GCC_BLSP2_AHB_CLK>;
2313                         clock-names = "core", "iface";
2314                         dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2315                         dma-names = "tx", "rx";
2316                         pinctrl-names = "default", "sleep";
2317                         pinctrl-0 = <&blsp2_i2c3_default>;
2318                         pinctrl-1 = <&blsp2_i2c3_sleep>;
2319                         clock-frequency = <400000>;
2320
2321                         status = "disabled";
2322                         #address-cells = <1>;
2323                         #size-cells = <0>;
2324                 };
2325
2326                 blsp2_i2c4: i2c@c1b8000 {
2327                         compatible = "qcom,i2c-qup-v2.2.1";
2328                         reg = <0x0c1b8000 0x600>;
2329                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2330
2331                         clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2332                                  <&gcc GCC_BLSP2_AHB_CLK>;
2333                         clock-names = "core", "iface";
2334                         dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2335                         dma-names = "tx", "rx";
2336                         pinctrl-names = "default", "sleep";
2337                         pinctrl-0 = <&blsp2_i2c4_default>;
2338                         pinctrl-1 = <&blsp2_i2c4_sleep>;
2339                         clock-frequency = <400000>;
2340
2341                         status = "disabled";
2342                         #address-cells = <1>;
2343                         #size-cells = <0>;
2344                 };
2345
2346                 blsp2_i2c5: i2c@c1b9000 {
2347                         compatible = "qcom,i2c-qup-v2.2.1";
2348                         reg = <0x0c1b9000 0x600>;
2349                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2350
2351                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2352                                  <&gcc GCC_BLSP2_AHB_CLK>;
2353                         clock-names = "core", "iface";
2354                         dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2355                         dma-names = "tx", "rx";
2356                         pinctrl-names = "default", "sleep";
2357                         pinctrl-0 = <&blsp2_i2c5_default>;
2358                         pinctrl-1 = <&blsp2_i2c5_sleep>;
2359                         clock-frequency = <400000>;
2360
2361                         status = "disabled";
2362                         #address-cells = <1>;
2363                         #size-cells = <0>;
2364                 };
2365
2366                 blsp2_i2c6: i2c@c1ba000 {
2367                         compatible = "qcom,i2c-qup-v2.2.1";
2368                         reg = <0x0c1ba000 0x600>;
2369                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2370
2371                         clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2372                                  <&gcc GCC_BLSP2_AHB_CLK>;
2373                         clock-names = "core", "iface";
2374                         dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2375                         dma-names = "tx", "rx";
2376                         pinctrl-names = "default", "sleep";
2377                         pinctrl-0 = <&blsp2_i2c6_default>;
2378                         pinctrl-1 = <&blsp2_i2c6_sleep>;
2379                         clock-frequency = <400000>;
2380
2381                         status = "disabled";
2382                         #address-cells = <1>;
2383                         #size-cells = <0>;
2384                 };
2385
2386                 mmcc: clock-controller@c8c0000 {
2387                         compatible = "qcom,mmcc-msm8998";
2388                         #clock-cells = <1>;
2389                         #reset-cells = <1>;
2390                         #power-domain-cells = <1>;
2391                         reg = <0xc8c0000 0x40000>;
2392
2393                         clock-names = "xo",
2394                                       "gpll0",
2395                                       "dsi0dsi",
2396                                       "dsi0byte",
2397                                       "dsi1dsi",
2398                                       "dsi1byte",
2399                                       "hdmipll",
2400                                       "dplink",
2401                                       "dpvco",
2402                                       "core_bi_pll_test_se";
2403                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2404                                  <&gcc GCC_MMSS_GPLL0_CLK>,
2405                                  <0>,
2406                                  <0>,
2407                                  <0>,
2408                                  <0>,
2409                                  <0>,
2410                                  <0>,
2411                                  <0>,
2412                                  <0>;
2413                 };
2414
2415                 mmss_smmu: iommu@cd00000 {
2416                         compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
2417                         reg = <0x0cd00000 0x40000>;
2418                         #iommu-cells = <1>;
2419
2420                         clocks = <&mmcc MNOC_AHB_CLK>,
2421                                  <&mmcc BIMC_SMMU_AHB_CLK>,
2422                                  <&rpmcc RPM_SMD_MMAXI_CLK>,
2423                                  <&mmcc BIMC_SMMU_AXI_CLK>;
2424                         clock-names = "iface-mm", "iface-smmu",
2425                                       "bus-mm", "bus-smmu";
2426
2427                         #global-interrupts = <0>;
2428                         interrupts =
2429                                 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
2430                                 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
2431                                 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
2432                                 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2433                                 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
2434                                 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
2435                                 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
2436                                 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
2437                                 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
2438                                 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
2439                                 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
2440                                 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
2441                                 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
2442                                 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
2443                                 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
2444                                 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2445                                 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
2446                                 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2447                                 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2448                                 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2449                 };
2450
2451                 remoteproc_adsp: remoteproc@17300000 {
2452                         compatible = "qcom,msm8998-adsp-pas";
2453                         reg = <0x17300000 0x4040>;
2454
2455                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2456                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2457                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2458                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2459                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2460                         interrupt-names = "wdog", "fatal", "ready",
2461                                           "handover", "stop-ack";
2462
2463                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2464                         clock-names = "xo";
2465
2466                         memory-region = <&adsp_mem>;
2467
2468                         qcom,smem-states = <&adsp_smp2p_out 0>;
2469                         qcom,smem-state-names = "stop";
2470
2471                         power-domains = <&rpmpd MSM8998_VDDCX>;
2472                         power-domain-names = "cx";
2473
2474                         status = "disabled";
2475
2476                         glink-edge {
2477                                 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
2478                                 label = "lpass";
2479                                 qcom,remote-pid = <2>;
2480                                 mboxes = <&apcs_glb 9>;
2481                         };
2482                 };
2483
2484                 apcs_glb: mailbox@17911000 {
2485                         compatible = "qcom,msm8998-apcs-hmss-global";
2486                         reg = <0x17911000 0x1000>;
2487
2488                         #mbox-cells = <1>;
2489                 };
2490
2491                 timer@17920000 {
2492                         #address-cells = <1>;
2493                         #size-cells = <1>;
2494                         ranges;
2495                         compatible = "arm,armv7-timer-mem";
2496                         reg = <0x17920000 0x1000>;
2497
2498                         frame@17921000 {
2499                                 frame-number = <0>;
2500                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2501                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2502                                 reg = <0x17921000 0x1000>,
2503                                       <0x17922000 0x1000>;
2504                         };
2505
2506                         frame@17923000 {
2507                                 frame-number = <1>;
2508                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2509                                 reg = <0x17923000 0x1000>;
2510                                 status = "disabled";
2511                         };
2512
2513                         frame@17924000 {
2514                                 frame-number = <2>;
2515                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2516                                 reg = <0x17924000 0x1000>;
2517                                 status = "disabled";
2518                         };
2519
2520                         frame@17925000 {
2521                                 frame-number = <3>;
2522                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2523                                 reg = <0x17925000 0x1000>;
2524                                 status = "disabled";
2525                         };
2526
2527                         frame@17926000 {
2528                                 frame-number = <4>;
2529                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2530                                 reg = <0x17926000 0x1000>;
2531                                 status = "disabled";
2532                         };
2533
2534                         frame@17927000 {
2535                                 frame-number = <5>;
2536                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2537                                 reg = <0x17927000 0x1000>;
2538                                 status = "disabled";
2539                         };
2540
2541                         frame@17928000 {
2542                                 frame-number = <6>;
2543                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2544                                 reg = <0x17928000 0x1000>;
2545                                 status = "disabled";
2546                         };
2547                 };
2548
2549                 intc: interrupt-controller@17a00000 {
2550                         compatible = "arm,gic-v3";
2551                         reg = <0x17a00000 0x10000>,       /* GICD */
2552                               <0x17b00000 0x100000>;      /* GICR * 8 */
2553                         #interrupt-cells = <3>;
2554                         #address-cells = <1>;
2555                         #size-cells = <1>;
2556                         ranges;
2557                         interrupt-controller;
2558                         #redistributor-regions = <1>;
2559                         redistributor-stride = <0x0 0x20000>;
2560                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2561                 };
2562
2563                 wifi: wifi@18800000 {
2564                         compatible = "qcom,wcn3990-wifi";
2565                         status = "disabled";
2566                         reg = <0x18800000 0x800000>;
2567                         reg-names = "membase";
2568                         memory-region = <&wlan_msa_mem>;
2569                         clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
2570                         clock-names = "cxo_ref_clk_pin";
2571                         interrupts =
2572                                 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
2573                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
2574                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
2575                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
2576                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
2577                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2578                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
2579                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2580                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2581                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2582                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2583                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
2584                         iommus = <&anoc2_smmu 0x1900>,
2585                                  <&anoc2_smmu 0x1901>;
2586                         qcom,snoc-host-cap-8bit-quirk;
2587                 };
2588         };
2589 };