1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2020, Konrad Dybcio
6 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&intc>;
21 compatible = "fixed-clock";
23 clock-frequency = <19200000>;
24 clock-output-names = "xo_board";
27 sleep_clk: sleep_clk {
28 compatible = "fixed-clock";
30 clock-frequency = <32764>;
31 clock-output-names = "sleep_clk";
41 compatible = "arm,cortex-a53";
43 enable-method = "psci";
44 cpu-idle-states = <&PERF_CPU_SLEEP_0
48 &PERF_CLUSTER_SLEEP_2>;
49 capacity-dmips-mhz = <1126>;
51 next-level-cache = <&L2_1>;
60 compatible = "arm,cortex-a53";
62 enable-method = "psci";
63 cpu-idle-states = <&PERF_CPU_SLEEP_0
67 &PERF_CLUSTER_SLEEP_2>;
68 capacity-dmips-mhz = <1126>;
70 next-level-cache = <&L2_1>;
75 compatible = "arm,cortex-a53";
77 enable-method = "psci";
78 cpu-idle-states = <&PERF_CPU_SLEEP_0
82 &PERF_CLUSTER_SLEEP_2>;
83 capacity-dmips-mhz = <1126>;
85 next-level-cache = <&L2_1>;
90 compatible = "arm,cortex-a53";
92 enable-method = "psci";
93 cpu-idle-states = <&PERF_CPU_SLEEP_0
97 &PERF_CLUSTER_SLEEP_2>;
98 capacity-dmips-mhz = <1126>;
100 next-level-cache = <&L2_1>;
105 compatible = "arm,cortex-a53";
107 enable-method = "psci";
108 cpu-idle-states = <&PWR_CPU_SLEEP_0
112 &PWR_CLUSTER_SLEEP_2>;
113 capacity-dmips-mhz = <1024>;
114 #cooling-cells = <2>;
115 next-level-cache = <&L2_0>;
117 compatible = "cache";
124 compatible = "arm,cortex-a53";
126 enable-method = "psci";
127 cpu-idle-states = <&PWR_CPU_SLEEP_0
131 &PWR_CLUSTER_SLEEP_2>;
132 capacity-dmips-mhz = <1024>;
133 #cooling-cells = <2>;
134 next-level-cache = <&L2_0>;
139 compatible = "arm,cortex-a53";
141 enable-method = "psci";
142 cpu-idle-states = <&PWR_CPU_SLEEP_0
146 &PWR_CLUSTER_SLEEP_2>;
147 capacity-dmips-mhz = <1024>;
148 #cooling-cells = <2>;
149 next-level-cache = <&L2_0>;
154 compatible = "arm,cortex-a53";
156 enable-method = "psci";
157 cpu-idle-states = <&PWR_CPU_SLEEP_0
161 &PWR_CLUSTER_SLEEP_2>;
162 capacity-dmips-mhz = <1024>;
163 #cooling-cells = <2>;
164 next-level-cache = <&L2_0>;
206 entry-method = "psci";
208 PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
209 compatible = "arm,idle-state";
210 idle-state-name = "pwr-retention";
211 arm,psci-suspend-param = <0x40000002>;
212 entry-latency-us = <338>;
213 exit-latency-us = <423>;
214 min-residency-us = <200>;
217 PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
218 compatible = "arm,idle-state";
219 idle-state-name = "pwr-power-collapse";
220 arm,psci-suspend-param = <0x40000003>;
221 entry-latency-us = <515>;
222 exit-latency-us = <1821>;
223 min-residency-us = <1000>;
227 PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
228 compatible = "arm,idle-state";
229 idle-state-name = "perf-retention";
230 arm,psci-suspend-param = <0x40000002>;
231 entry-latency-us = <154>;
232 exit-latency-us = <87>;
233 min-residency-us = <200>;
236 PERF_CPU_SLEEP_1: cpu-sleep-1-1 {
237 compatible = "arm,idle-state";
238 idle-state-name = "perf-power-collapse";
239 arm,psci-suspend-param = <0x40000003>;
240 entry-latency-us = <262>;
241 exit-latency-us = <301>;
242 min-residency-us = <1000>;
246 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
247 compatible = "arm,idle-state";
248 idle-state-name = "pwr-cluster-dynamic-retention";
249 arm,psci-suspend-param = <0x400000F2>;
250 entry-latency-us = <284>;
251 exit-latency-us = <384>;
252 min-residency-us = <9987>;
256 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
257 compatible = "arm,idle-state";
258 idle-state-name = "pwr-cluster-retention";
259 arm,psci-suspend-param = <0x400000F3>;
260 entry-latency-us = <338>;
261 exit-latency-us = <423>;
262 min-residency-us = <9987>;
266 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
267 compatible = "arm,idle-state";
268 idle-state-name = "pwr-cluster-retention";
269 arm,psci-suspend-param = <0x400000F4>;
270 entry-latency-us = <515>;
271 exit-latency-us = <1821>;
272 min-residency-us = <9987>;
276 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
277 compatible = "arm,idle-state";
278 idle-state-name = "perf-cluster-dynamic-retention";
279 arm,psci-suspend-param = <0x400000F2>;
280 entry-latency-us = <272>;
281 exit-latency-us = <329>;
282 min-residency-us = <9987>;
286 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 {
287 compatible = "arm,idle-state";
288 idle-state-name = "perf-cluster-retention";
289 arm,psci-suspend-param = <0x400000F3>;
290 entry-latency-us = <332>;
291 exit-latency-us = <368>;
292 min-residency-us = <9987>;
296 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 {
297 compatible = "arm,idle-state";
298 idle-state-name = "perf-cluster-retention";
299 arm,psci-suspend-param = <0x400000F4>;
300 entry-latency-us = <545>;
301 exit-latency-us = <1609>;
302 min-residency-us = <9987>;
310 compatible = "qcom,scm-msm8998", "qcom,scm";
315 device_type = "memory";
316 /* We expect the bootloader to fill in the reg */
321 compatible = "arm,armv8-pmuv3";
322 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
326 compatible = "arm,psci-1.0";
331 #address-cells = <2>;
335 wlan_msa_guard: wlan-msa-guard@85600000 {
336 reg = <0x0 0x85600000 0x0 0x100000>;
340 wlan_msa_mem: wlan-msa-mem@85700000 {
341 reg = <0x0 0x85700000 0x0 0x100000>;
345 qhee_code: qhee-code@85800000 {
346 reg = <0x0 0x85800000 0x0 0x3700000>;
350 smem_region: smem-mem@86000000 {
351 reg = <0 0x86000000 0 0x200000>;
355 tz_mem: memory@86200000 {
356 reg = <0x0 0x86200000 0x0 0x3300000>;
360 modem_fw_mem: modem-fw-region@8ac00000 {
361 reg = <0x0 0x8ac00000 0x0 0x7e00000>;
365 adsp_fw_mem: adsp-fw-region@92a00000 {
366 reg = <0x0 0x92a00000 0x0 0x1e00000>;
370 pil_mba_mem: pil-mba-region@94800000 {
371 reg = <0x0 0x94800000 0x0 0x200000>;
375 buffer_mem: buffer-region@94a00000 {
376 reg = <0x0 0x94a00000 0x0 0x100000>;
380 venus_fw_mem: venus-fw-region@9f800000 {
381 reg = <0x0 0x9f800000 0x0 0x800000>;
385 secure_region2: secure-region2@f7c00000 {
386 reg = <0x0 0xf7c00000 0x0 0x5c00000>;
390 adsp_mem: adsp-region@f6000000 {
391 reg = <0x0 0xf6000000 0x0 0x800000>;
395 qseecom_ta_mem: qseecom-ta-region@fec00000 {
396 reg = <0x0 0xfec00000 0x0 0x1000000>;
400 qseecom_mem: qseecom-region@f6800000 {
401 reg = <0x0 0xf6800000 0x0 0x1400000>;
405 secure_display_memory: secure-region@f5c00000 {
406 reg = <0x0 0xf5c00000 0x0 0x5c00000>;
410 cont_splash_mem: cont-splash-region@9d400000 {
411 reg = <0x0 0x9d400000 0x0 0x23ff000>;
417 compatible = "qcom,glink-rpm";
419 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
420 qcom,rpm-msg-ram = <&rpm_msg_ram>;
421 mboxes = <&apcs_glb 0>;
423 rpm_requests: rpm-requests {
424 compatible = "qcom,rpm-sdm660";
425 qcom,glink-channels = "rpm_requests";
427 rpmcc: clock-controller {
428 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
435 compatible = "qcom,smem";
436 memory-region = <&smem_region>;
437 hwlocks = <&tcsr_mutex 3>;
441 #address-cells = <1>;
443 ranges = <0 0 0 0xffffffff>;
444 compatible = "simple-bus";
446 gcc: clock-controller@100000 {
447 compatible = "qcom,gcc-sdm630";
450 #power-domain-cells = <1>;
451 reg = <0x00100000 0x94000>;
453 clock-names = "xo", "sleep_clk";
454 clocks = <&xo_board>,
458 rpm_msg_ram: memory@778000 {
459 compatible = "qcom,rpm-msg-ram";
460 reg = <0x00778000 0x7000>;
463 qfprom: qfprom@780000 {
464 compatible = "qcom,qfprom";
465 reg = <0x00780000 0x621c>;
466 #address-cells = <1>;
471 compatible = "qcom,prng-ee";
472 reg = <0x00793000 0x1000>;
473 clocks = <&gcc GCC_PRNG_AHB_CLK>;
474 clock-names = "core";
478 compatible = "qcom,pshold";
479 reg = <0x010ac000 0x4>;
482 anoc2_smmu: iommu@16c0000 {
483 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
484 reg = <0x016c0000 0x40000>;
487 #global-interrupts = <2>;
489 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
490 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>,
494 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>,
495 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>,
496 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>,
497 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>,
498 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
499 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
502 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
525 tcsr_mutex_regs: syscon@1f40000 {
526 compatible = "syscon";
527 reg = <0x01f40000 0x20000>;
530 tlmm: pinctrl@3000000 {
531 compatible = "qcom,sdm630-pinctrl";
532 reg = <0x03000000 0xc00000>;
533 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
536 interrupt-controller;
537 #interrupt-cells = <0x2>;
539 blsp1_uart1_default: blsp1-uart1-default {
540 pins = "gpio0", "gpio1", "gpio2", "gpio3";
541 drive-strength = <2>;
545 blsp1_uart1_sleep: blsp1-uart1-sleep {
546 pins = "gpio0", "gpio1", "gpio2", "gpio3";
547 drive-strength = <2>;
551 blsp1_uart2_default: blsp1-uart2-default {
552 pins = "gpio4", "gpio5";
553 drive-strength = <2>;
557 blsp2_uart1_tx_active: blsp2-uart1-tx-active {
559 drive-strength = <2>;
563 blsp2_uart1_tx_sleep: blsp2-uart1-tx-sleep {
565 drive-strength = <2>;
569 blsp2_uart1_rxcts_active: blsp2-uart1-rxcts-active {
570 pins = "gpio17", "gpio18";
571 drive-strength = <2>;
575 blsp2_uart1_rxcts_sleep: blsp2-uart1-rxcts-sleep {
576 pins = "gpio17", "gpio18";
577 drive-strength = <2>;
581 blsp2_uart1_rfr_active: blsp2-uart1-rfr-active {
583 drive-strength = <2>;
587 blsp2_uart1_rfr_sleep: blsp2-uart1-rfr-sleep {
589 drive-strength = <2>;
593 i2c1_default: i2c1-default {
594 pins = "gpio2", "gpio3";
595 drive-strength = <2>;
599 i2c1_sleep: i2c1-sleep {
600 pins = "gpio2", "gpio3";
601 drive-strength = <2>;
605 i2c2_default: i2c2-default {
606 pins = "gpio6", "gpio7";
607 drive-strength = <2>;
611 i2c2_sleep: i2c2-sleep {
612 pins = "gpio6", "gpio7";
613 drive-strength = <2>;
617 i2c3_default: i2c3-default {
618 pins = "gpio10", "gpio11";
619 drive-strength = <2>;
623 i2c3_sleep: i2c3-sleep {
624 pins = "gpio10", "gpio11";
625 drive-strength = <2>;
629 i2c4_default: i2c4-default {
630 pins = "gpio14", "gpio15";
631 drive-strength = <2>;
635 i2c4_sleep: i2c4-sleep {
636 pins = "gpio14", "gpio15";
637 drive-strength = <2>;
641 i2c5_default: i2c5-default {
642 pins = "gpio18", "gpio19";
643 drive-strength = <2>;
647 i2c5_sleep: i2c5-sleep {
648 pins = "gpio18", "gpio19";
649 drive-strength = <2>;
653 i2c6_default: i2c6-default {
654 pins = "gpio22", "gpio23";
655 drive-strength = <2>;
659 i2c6_sleep: i2c6-sleep {
660 pins = "gpio22", "gpio23";
661 drive-strength = <2>;
665 i2c7_default: i2c7-default {
666 pins = "gpio26", "gpio27";
667 drive-strength = <2>;
671 i2c7_sleep: i2c7-sleep {
672 pins = "gpio26", "gpio27";
673 drive-strength = <2>;
677 i2c8_default: i2c8-default {
678 pins = "gpio30", "gpio31";
679 drive-strength = <2>;
683 i2c8_sleep: i2c8-sleep {
684 pins = "gpio30", "gpio31";
685 drive-strength = <2>;
689 sdc1_clk_on: sdc1-clk-on {
692 drive-strength = <16>;
695 sdc1_clk_off: sdc1-clk-off {
698 drive-strength = <2>;
701 sdc1_cmd_on: sdc1-cmd-on {
704 drive-strength = <10>;
707 sdc1_cmd_off: sdc1-cmd-off {
710 drive-strength = <2>;
713 sdc1_data_on: sdc1-data-on {
716 drive-strength = <8>;
719 sdc1_data_off: sdc1-data-off {
722 drive-strength = <2>;
725 sdc1_rclk_on: sdc1-rclk-on {
730 sdc1_rclk_off: sdc1-rclk-off {
736 kgsl_smmu: iommu@5040000 {
737 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
738 reg = <0x05040000 0x10000>;
741 #global-interrupts = <2>;
743 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
752 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>;
758 lpass_smmu: iommu@5100000 {
759 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
760 reg = <0x05100000 0x40000>;
763 #global-interrupts = <2>;
765 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
768 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
769 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
770 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
772 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
773 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
774 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
775 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
776 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
777 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
789 spmi_bus: spmi@800f000 {
790 compatible = "qcom,spmi-pmic-arb";
791 reg = <0x0800f000 0x1000>,
792 <0x08400000 0x1000000>,
793 <0x09400000 0x1000000>,
794 <0x0a400000 0x220000>,
796 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
797 interrupt-names = "periph_irq";
798 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
801 #address-cells = <2>;
803 interrupt-controller;
804 #interrupt-cells = <4>;
808 sdhc_1: sdhci@c0c4000 {
809 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
810 reg = <0x0c0c4000 0x1000>,
812 reg-names = "hc", "cqhci";
814 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
815 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
816 interrupt-names = "hc_irq", "pwr_irq";
818 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
819 <&gcc GCC_SDCC1_AHB_CLK>,
821 clock-names = "core", "iface", "xo";
823 pinctrl-names = "default", "sleep";
824 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
825 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
833 blsp1_dma: dma@c144000 {
834 compatible = "qcom,bam-v1.7.0";
835 reg = <0x0c144000 0x1f000>;
836 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
837 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
838 clock-names = "bam_clk";
841 qcom,controlled-remotely;
846 blsp1_uart1: serial@c16f000 {
847 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
848 reg = <0x0c16f000 0x200>;
849 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
851 <&gcc GCC_BLSP1_AHB_CLK>;
852 clock-names = "core", "iface";
853 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
854 dma-names = "tx", "rx";
855 pinctrl-names = "default", "sleep";
856 pinctrl-0 = <&blsp1_uart1_default>;
857 pinctrl-1 = <&blsp1_uart1_sleep>;
861 blsp1_uart2: serial@c170000 {
862 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
863 reg = <0x0c170000 0x1000>;
864 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
866 <&gcc GCC_BLSP1_AHB_CLK>;
867 clock-names = "core", "iface";
868 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
869 dma-names = "tx", "rx";
870 pinctrl-names = "default";
871 pinctrl-0 = <&blsp1_uart2_default>;
875 blsp_i2c1: i2c@c175000 {
876 compatible = "qcom,i2c-qup-v2.2.1";
877 reg = <0x0c175000 0x600>;
878 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
880 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
881 <&gcc GCC_BLSP1_AHB_CLK>;
882 clock-names = "core", "iface";
883 clock-frequency = <400000>;
885 pinctrl-names = "default", "sleep";
886 pinctrl-0 = <&i2c1_default>;
887 pinctrl-1 = <&i2c1_sleep>;
888 #address-cells = <1>;
893 blsp_i2c2: i2c@c176000 {
894 compatible = "qcom,i2c-qup-v2.2.1";
895 reg = <0x0c176000 0x600>;
896 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
899 <&gcc GCC_BLSP1_AHB_CLK>;
900 clock-names = "core", "iface";
901 clock-frequency = <400000>;
903 pinctrl-names = "default", "sleep";
904 pinctrl-0 = <&i2c2_default>;
905 pinctrl-1 = <&i2c2_sleep>;
906 #address-cells = <1>;
911 blsp_i2c3: i2c@c177000 {
912 compatible = "qcom,i2c-qup-v2.2.1";
913 reg = <0x0c177000 0x600>;
914 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
916 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
917 <&gcc GCC_BLSP1_AHB_CLK>;
918 clock-names = "core", "iface";
919 clock-frequency = <400000>;
921 pinctrl-names = "default", "sleep";
922 pinctrl-0 = <&i2c3_default>;
923 pinctrl-1 = <&i2c3_sleep>;
924 #address-cells = <1>;
929 blsp_i2c4: i2c@c178000 {
930 compatible = "qcom,i2c-qup-v2.2.1";
931 reg = <0x0c178000 0x600>;
932 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
934 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
935 <&gcc GCC_BLSP1_AHB_CLK>;
936 clock-names = "core", "iface";
937 clock-frequency = <400000>;
939 pinctrl-names = "default", "sleep";
940 pinctrl-0 = <&i2c4_default>;
941 pinctrl-1 = <&i2c4_sleep>;
942 #address-cells = <1>;
947 blsp2_dma: dma@c184000 {
948 compatible = "qcom,bam-v1.7.0";
949 reg = <0x0c184000 0x1f000>;
950 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
951 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
952 clock-names = "bam_clk";
955 qcom,controlled-remotely;
960 blsp2_uart1: serial@c1af000 {
961 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
962 reg = <0x0c1af000 0x200>;
963 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
964 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>,
965 <&gcc GCC_BLSP2_AHB_CLK>;
966 clock-names = "core", "iface";
967 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
968 dma-names = "tx", "rx";
969 pinctrl-names = "default", "sleep";
970 pinctrl-0 = <&blsp2_uart1_tx_active &blsp2_uart1_rxcts_active
971 &blsp2_uart1_rfr_active>;
972 pinctrl-1 = <&blsp2_uart1_tx_sleep &blsp2_uart1_rxcts_sleep
973 &blsp2_uart1_rfr_sleep>;
977 blsp_i2c5: i2c@c1b5000 {
978 compatible = "qcom,i2c-qup-v2.2.1";
979 reg = <0x0c1b5000 0x600>;
980 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
983 <&gcc GCC_BLSP2_AHB_CLK>;
984 clock-names = "core", "iface";
985 clock-frequency = <400000>;
987 pinctrl-names = "default", "sleep";
988 pinctrl-0 = <&i2c5_default>;
989 pinctrl-1 = <&i2c5_sleep>;
990 #address-cells = <1>;
995 blsp_i2c6: i2c@c1b6000 {
996 compatible = "qcom,i2c-qup-v2.2.1";
997 reg = <0x0c1b6000 0x600>;
998 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1000 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1001 <&gcc GCC_BLSP2_AHB_CLK>;
1002 clock-names = "core", "iface";
1003 clock-frequency = <400000>;
1005 pinctrl-names = "default", "sleep";
1006 pinctrl-0 = <&i2c6_default>;
1007 pinctrl-1 = <&i2c6_sleep>;
1008 #address-cells = <1>;
1010 status = "disabled";
1013 blsp_i2c7: i2c@c1b7000 {
1014 compatible = "qcom,i2c-qup-v2.2.1";
1015 reg = <0x0c1b7000 0x600>;
1016 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1018 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
1019 <&gcc GCC_BLSP2_AHB_CLK>;
1020 clock-names = "core", "iface";
1021 clock-frequency = <400000>;
1023 pinctrl-names = "default", "sleep";
1024 pinctrl-0 = <&i2c7_default>;
1025 pinctrl-1 = <&i2c7_sleep>;
1026 #address-cells = <1>;
1028 status = "disabled";
1031 blsp_i2c8: i2c@c1b8000 {
1032 compatible = "qcom,i2c-qup-v2.2.1";
1033 reg = <0x0c1b8000 0x600>;
1034 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1036 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
1037 <&gcc GCC_BLSP2_AHB_CLK>;
1038 clock-names = "core", "iface";
1039 clock-frequency = <400000>;
1041 pinctrl-names = "default", "sleep";
1042 pinctrl-0 = <&i2c8_default>;
1043 pinctrl-1 = <&i2c8_sleep>;
1044 #address-cells = <1>;
1046 status = "disabled";
1049 mmss_smmu: iommu@cd00000 {
1050 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
1051 reg = <0x0cd00000 0x40000>;
1054 #global-interrupts = <2>;
1056 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1057 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1059 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
1060 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
1061 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
1062 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
1063 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1064 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1065 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1066 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1067 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1068 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1069 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1070 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1071 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1072 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1073 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1074 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1075 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1076 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
1077 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
1078 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
1079 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
1080 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
1081 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
1082 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
1084 status = "disabled";
1087 apcs_glb: mailbox@17911000 {
1088 compatible = "qcom,sdm660-apcs-hmss-global";
1089 reg = <0x17911000 0x1000>;
1095 #address-cells = <1>;
1098 compatible = "arm,armv7-timer-mem";
1099 reg = <0x17920000 0x1000>;
1100 clock-frequency = <19200000>;
1104 interrupts = <0 8 0x4>,
1106 reg = <0x17921000 0x1000>,
1107 <0x17922000 0x1000>;
1112 interrupts = <0 9 0x4>;
1113 reg = <0x17923000 0x1000>;
1114 status = "disabled";
1119 interrupts = <0 10 0x4>;
1120 reg = <0x17924000 0x1000>;
1121 status = "disabled";
1126 interrupts = <0 11 0x4>;
1127 reg = <0x17925000 0x1000>;
1128 status = "disabled";
1133 interrupts = <0 12 0x4>;
1134 reg = <0x17926000 0x1000>;
1135 status = "disabled";
1140 interrupts = <0 13 0x4>;
1141 reg = <0x17927000 0x1000>;
1142 status = "disabled";
1147 interrupts = <0 14 0x4>;
1148 reg = <0x17928000 0x1000>;
1149 status = "disabled";
1153 intc: interrupt-controller@17a00000 {
1154 compatible = "arm,gic-v3";
1155 reg = <0x17a00000 0x10000>, /* GICD */
1156 <0x17b00000 0x100000>; /* GICR * 8 */
1157 #interrupt-cells = <3>;
1158 #address-cells = <1>;
1161 interrupt-controller;
1162 #redistributor-regions = <1>;
1163 redistributor-stride = <0x0 0x20000>;
1164 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1168 tcsr_mutex: hwlock {
1169 compatible = "qcom,tcsr-mutex";
1170 syscon = <&tcsr_mutex_regs 0 0x1000>;
1171 #hwlock-cells = <1>;
1175 compatible = "arm,armv8-timer";
1176 interrupts = <GIC_PPI 1 0xf08>,