1 // SPDX-License-Identifier: GPL-2.0
3 * SDM845 SoC device tree source
5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
11 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/phy/phy-qcom-qusb2.h>
16 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
17 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
18 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
19 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
20 #include <dt-bindings/thermal/thermal.h>
23 interrupt-parent = <&intc>;
66 device_type = "memory";
67 /* We expect the bootloader to fill in the size */
68 reg = <0 0x80000000 0 0>;
77 reg = <0 0x85fc0000 0 0x20000>;
82 compatible = "qcom,cmd-db";
83 reg = <0x0 0x85fe0000 0x0 0x20000>;
87 smem_mem: memory@86000000 {
88 reg = <0x0 0x86000000 0x0 0x200000>;
93 reg = <0 0x86200000 0 0x2d00000>;
97 wlan_msa_mem: memory@96700000 {
98 reg = <0 0x96700000 0 0x100000>;
102 mpss_region: memory@8e000000 {
103 reg = <0 0x8e000000 0 0x7800000>;
107 mba_region: memory@96500000 {
108 reg = <0 0x96500000 0 0x200000>;
114 #address-cells = <2>;
119 compatible = "qcom,kryo385";
121 enable-method = "psci";
122 qcom,freq-domain = <&cpufreq_hw 0>;
123 #cooling-cells = <2>;
124 next-level-cache = <&L2_0>;
126 compatible = "cache";
127 next-level-cache = <&L3_0>;
129 compatible = "cache";
136 compatible = "qcom,kryo385";
138 enable-method = "psci";
139 qcom,freq-domain = <&cpufreq_hw 0>;
140 #cooling-cells = <2>;
141 next-level-cache = <&L2_100>;
143 compatible = "cache";
144 next-level-cache = <&L3_0>;
150 compatible = "qcom,kryo385";
152 enable-method = "psci";
153 qcom,freq-domain = <&cpufreq_hw 0>;
154 #cooling-cells = <2>;
155 next-level-cache = <&L2_200>;
157 compatible = "cache";
158 next-level-cache = <&L3_0>;
164 compatible = "qcom,kryo385";
166 enable-method = "psci";
167 qcom,freq-domain = <&cpufreq_hw 0>;
168 #cooling-cells = <2>;
169 next-level-cache = <&L2_300>;
171 compatible = "cache";
172 next-level-cache = <&L3_0>;
178 compatible = "qcom,kryo385";
180 enable-method = "psci";
181 qcom,freq-domain = <&cpufreq_hw 1>;
182 #cooling-cells = <2>;
183 next-level-cache = <&L2_400>;
185 compatible = "cache";
186 next-level-cache = <&L3_0>;
192 compatible = "qcom,kryo385";
194 enable-method = "psci";
195 qcom,freq-domain = <&cpufreq_hw 1>;
196 #cooling-cells = <2>;
197 next-level-cache = <&L2_500>;
199 compatible = "cache";
200 next-level-cache = <&L3_0>;
206 compatible = "qcom,kryo385";
208 enable-method = "psci";
209 qcom,freq-domain = <&cpufreq_hw 1>;
210 #cooling-cells = <2>;
211 next-level-cache = <&L2_600>;
213 compatible = "cache";
214 next-level-cache = <&L3_0>;
220 compatible = "qcom,kryo385";
222 enable-method = "psci";
223 qcom,freq-domain = <&cpufreq_hw 1>;
224 #cooling-cells = <2>;
225 next-level-cache = <&L2_700>;
227 compatible = "cache";
228 next-level-cache = <&L3_0>;
234 compatible = "arm,armv8-pmuv3";
235 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
239 compatible = "arm,armv8-timer";
240 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
241 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
242 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
243 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
248 compatible = "fixed-clock";
250 clock-frequency = <38400000>;
251 clock-output-names = "xo_board";
254 sleep_clk: sleep-clk {
255 compatible = "fixed-clock";
257 clock-frequency = <32764>;
263 compatible = "qcom,scm-sdm845", "qcom,scm";
268 compatible = "qcom,tcsr-mutex";
269 syscon = <&tcsr_mutex_regs 0 0x1000>;
274 compatible = "qcom,smem";
275 memory-region = <&smem_mem>;
276 hwlocks = <&tcsr_mutex 3>;
280 compatible = "qcom,smp2p";
281 qcom,smem = <94>, <432>;
283 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
285 mboxes = <&apss_shared 6>;
287 qcom,local-pid = <0>;
288 qcom,remote-pid = <5>;
290 cdsp_smp2p_out: master-kernel {
291 qcom,entry-name = "master-kernel";
292 #qcom,smem-state-cells = <1>;
295 cdsp_smp2p_in: slave-kernel {
296 qcom,entry-name = "slave-kernel";
298 interrupt-controller;
299 #interrupt-cells = <2>;
304 compatible = "qcom,smp2p";
305 qcom,smem = <443>, <429>;
307 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
309 mboxes = <&apss_shared 10>;
311 qcom,local-pid = <0>;
312 qcom,remote-pid = <2>;
314 adsp_smp2p_out: master-kernel {
315 qcom,entry-name = "master-kernel";
316 #qcom,smem-state-cells = <1>;
319 adsp_smp2p_in: slave-kernel {
320 qcom,entry-name = "slave-kernel";
322 interrupt-controller;
323 #interrupt-cells = <2>;
328 compatible = "qcom,smp2p";
329 qcom,smem = <435>, <428>;
330 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
331 mboxes = <&apss_shared 14>;
332 qcom,local-pid = <0>;
333 qcom,remote-pid = <1>;
335 modem_smp2p_out: master-kernel {
336 qcom,entry-name = "master-kernel";
337 #qcom,smem-state-cells = <1>;
340 modem_smp2p_in: slave-kernel {
341 qcom,entry-name = "slave-kernel";
342 interrupt-controller;
343 #interrupt-cells = <2>;
348 compatible = "qcom,smp2p";
349 qcom,smem = <481>, <430>;
350 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
351 mboxes = <&apss_shared 26>;
352 qcom,local-pid = <0>;
353 qcom,remote-pid = <3>;
355 slpi_smp2p_out: master-kernel {
356 qcom,entry-name = "master-kernel";
357 #qcom,smem-state-cells = <1>;
360 slpi_smp2p_in: slave-kernel {
361 qcom,entry-name = "slave-kernel";
362 interrupt-controller;
363 #interrupt-cells = <2>;
368 compatible = "arm,psci-1.0";
373 #address-cells = <2>;
375 ranges = <0 0 0 0 0x10 0>;
376 dma-ranges = <0 0 0 0 0x10 0>;
377 compatible = "simple-bus";
379 gcc: clock-controller@100000 {
380 compatible = "qcom,gcc-sdm845";
381 reg = <0 0x00100000 0 0x1f0000>;
384 #power-domain-cells = <1>;
388 compatible = "qcom,qfprom";
389 reg = <0 0x00784000 0 0x8ff>;
390 #address-cells = <1>;
393 qusb2p_hstx_trim: hstx-trim-primary@1eb {
398 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
405 compatible = "qcom,prng-ee";
406 reg = <0 0x00793000 0 0x1000>;
407 clocks = <&gcc GCC_PRNG_AHB_CLK>;
408 clock-names = "core";
411 qupv3_id_0: geniqup@8c0000 {
412 compatible = "qcom,geni-se-qup";
413 reg = <0 0x008c0000 0 0x6000>;
414 clock-names = "m-ahb", "s-ahb";
415 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
416 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
417 #address-cells = <2>;
423 compatible = "qcom,geni-i2c";
424 reg = <0 0x00880000 0 0x4000>;
426 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
427 pinctrl-names = "default";
428 pinctrl-0 = <&qup_i2c0_default>;
429 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
430 #address-cells = <1>;
436 compatible = "qcom,geni-spi";
437 reg = <0 0x00880000 0 0x4000>;
439 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
440 pinctrl-names = "default";
441 pinctrl-0 = <&qup_spi0_default>;
442 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
443 #address-cells = <1>;
448 uart0: serial@880000 {
449 compatible = "qcom,geni-uart";
450 reg = <0 0x00880000 0 0x4000>;
452 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
453 pinctrl-names = "default";
454 pinctrl-0 = <&qup_uart0_default>;
455 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
460 compatible = "qcom,geni-i2c";
461 reg = <0 0x00884000 0 0x4000>;
463 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
464 pinctrl-names = "default";
465 pinctrl-0 = <&qup_i2c1_default>;
466 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
467 #address-cells = <1>;
473 compatible = "qcom,geni-spi";
474 reg = <0 0x00884000 0 0x4000>;
476 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
477 pinctrl-names = "default";
478 pinctrl-0 = <&qup_spi1_default>;
479 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
480 #address-cells = <1>;
485 uart1: serial@884000 {
486 compatible = "qcom,geni-uart";
487 reg = <0 0x00884000 0 0x4000>;
489 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
490 pinctrl-names = "default";
491 pinctrl-0 = <&qup_uart1_default>;
492 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
497 compatible = "qcom,geni-i2c";
498 reg = <0 0x00888000 0 0x4000>;
500 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
501 pinctrl-names = "default";
502 pinctrl-0 = <&qup_i2c2_default>;
503 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
504 #address-cells = <1>;
510 compatible = "qcom,geni-spi";
511 reg = <0 0x00888000 0 0x4000>;
513 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
514 pinctrl-names = "default";
515 pinctrl-0 = <&qup_spi2_default>;
516 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
517 #address-cells = <1>;
522 uart2: serial@888000 {
523 compatible = "qcom,geni-uart";
524 reg = <0 0x00888000 0 0x4000>;
526 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
527 pinctrl-names = "default";
528 pinctrl-0 = <&qup_uart2_default>;
529 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
534 compatible = "qcom,geni-i2c";
535 reg = <0 0x0088c000 0 0x4000>;
537 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&qup_i2c3_default>;
540 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
541 #address-cells = <1>;
547 compatible = "qcom,geni-spi";
548 reg = <0 0x0088c000 0 0x4000>;
550 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
551 pinctrl-names = "default";
552 pinctrl-0 = <&qup_spi3_default>;
553 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
554 #address-cells = <1>;
559 uart3: serial@88c000 {
560 compatible = "qcom,geni-uart";
561 reg = <0 0x0088c000 0 0x4000>;
563 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
564 pinctrl-names = "default";
565 pinctrl-0 = <&qup_uart3_default>;
566 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
571 compatible = "qcom,geni-i2c";
572 reg = <0 0x00890000 0 0x4000>;
574 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
575 pinctrl-names = "default";
576 pinctrl-0 = <&qup_i2c4_default>;
577 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
578 #address-cells = <1>;
584 compatible = "qcom,geni-spi";
585 reg = <0 0x00890000 0 0x4000>;
587 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
588 pinctrl-names = "default";
589 pinctrl-0 = <&qup_spi4_default>;
590 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
591 #address-cells = <1>;
596 uart4: serial@890000 {
597 compatible = "qcom,geni-uart";
598 reg = <0 0x00890000 0 0x4000>;
600 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
601 pinctrl-names = "default";
602 pinctrl-0 = <&qup_uart4_default>;
603 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
608 compatible = "qcom,geni-i2c";
609 reg = <0 0x00894000 0 0x4000>;
611 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
612 pinctrl-names = "default";
613 pinctrl-0 = <&qup_i2c5_default>;
614 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
615 #address-cells = <1>;
621 compatible = "qcom,geni-spi";
622 reg = <0 0x00894000 0 0x4000>;
624 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
625 pinctrl-names = "default";
626 pinctrl-0 = <&qup_spi5_default>;
627 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
628 #address-cells = <1>;
633 uart5: serial@894000 {
634 compatible = "qcom,geni-uart";
635 reg = <0 0x00894000 0 0x4000>;
637 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
638 pinctrl-names = "default";
639 pinctrl-0 = <&qup_uart5_default>;
640 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
645 compatible = "qcom,geni-i2c";
646 reg = <0 0x00898000 0 0x4000>;
648 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
649 pinctrl-names = "default";
650 pinctrl-0 = <&qup_i2c6_default>;
651 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
652 #address-cells = <1>;
658 compatible = "qcom,geni-spi";
659 reg = <0 0x00898000 0 0x4000>;
661 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
662 pinctrl-names = "default";
663 pinctrl-0 = <&qup_spi6_default>;
664 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
665 #address-cells = <1>;
670 uart6: serial@898000 {
671 compatible = "qcom,geni-uart";
672 reg = <0 0x00898000 0 0x4000>;
674 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
675 pinctrl-names = "default";
676 pinctrl-0 = <&qup_uart6_default>;
677 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
682 compatible = "qcom,geni-i2c";
683 reg = <0 0x0089c000 0 0x4000>;
685 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
686 pinctrl-names = "default";
687 pinctrl-0 = <&qup_i2c7_default>;
688 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
689 #address-cells = <1>;
695 compatible = "qcom,geni-spi";
696 reg = <0 0x0089c000 0 0x4000>;
698 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
699 pinctrl-names = "default";
700 pinctrl-0 = <&qup_spi7_default>;
701 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
702 #address-cells = <1>;
707 uart7: serial@89c000 {
708 compatible = "qcom,geni-uart";
709 reg = <0 0x0089c000 0 0x4000>;
711 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
712 pinctrl-names = "default";
713 pinctrl-0 = <&qup_uart7_default>;
714 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
719 qupv3_id_1: geniqup@ac0000 {
720 compatible = "qcom,geni-se-qup";
721 reg = <0 0x00ac0000 0 0x6000>;
722 clock-names = "m-ahb", "s-ahb";
723 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
724 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
725 #address-cells = <2>;
731 compatible = "qcom,geni-i2c";
732 reg = <0 0x00a80000 0 0x4000>;
734 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
735 pinctrl-names = "default";
736 pinctrl-0 = <&qup_i2c8_default>;
737 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
738 #address-cells = <1>;
744 compatible = "qcom,geni-spi";
745 reg = <0 0x00a80000 0 0x4000>;
747 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
748 pinctrl-names = "default";
749 pinctrl-0 = <&qup_spi8_default>;
750 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
751 #address-cells = <1>;
756 uart8: serial@a80000 {
757 compatible = "qcom,geni-uart";
758 reg = <0 0x00a80000 0 0x4000>;
760 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
761 pinctrl-names = "default";
762 pinctrl-0 = <&qup_uart8_default>;
763 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
768 compatible = "qcom,geni-i2c";
769 reg = <0 0x00a84000 0 0x4000>;
771 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
772 pinctrl-names = "default";
773 pinctrl-0 = <&qup_i2c9_default>;
774 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
775 #address-cells = <1>;
781 compatible = "qcom,geni-spi";
782 reg = <0 0x00a84000 0 0x4000>;
784 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
785 pinctrl-names = "default";
786 pinctrl-0 = <&qup_spi9_default>;
787 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
788 #address-cells = <1>;
793 uart9: serial@a84000 {
794 compatible = "qcom,geni-debug-uart";
795 reg = <0 0x00a84000 0 0x4000>;
797 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
798 pinctrl-names = "default";
799 pinctrl-0 = <&qup_uart9_default>;
800 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
805 compatible = "qcom,geni-i2c";
806 reg = <0 0x00a88000 0 0x4000>;
808 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
809 pinctrl-names = "default";
810 pinctrl-0 = <&qup_i2c10_default>;
811 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
812 #address-cells = <1>;
818 compatible = "qcom,geni-spi";
819 reg = <0 0x00a88000 0 0x4000>;
821 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
822 pinctrl-names = "default";
823 pinctrl-0 = <&qup_spi10_default>;
824 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
825 #address-cells = <1>;
830 uart10: serial@a88000 {
831 compatible = "qcom,geni-uart";
832 reg = <0 0x00a88000 0 0x4000>;
834 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
835 pinctrl-names = "default";
836 pinctrl-0 = <&qup_uart10_default>;
837 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
842 compatible = "qcom,geni-i2c";
843 reg = <0 0x00a8c000 0 0x4000>;
845 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
846 pinctrl-names = "default";
847 pinctrl-0 = <&qup_i2c11_default>;
848 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
849 #address-cells = <1>;
855 compatible = "qcom,geni-spi";
856 reg = <0 0x00a8c000 0 0x4000>;
858 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
859 pinctrl-names = "default";
860 pinctrl-0 = <&qup_spi11_default>;
861 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
862 #address-cells = <1>;
867 uart11: serial@a8c000 {
868 compatible = "qcom,geni-uart";
869 reg = <0 0x00a8c000 0 0x4000>;
871 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
872 pinctrl-names = "default";
873 pinctrl-0 = <&qup_uart11_default>;
874 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
879 compatible = "qcom,geni-i2c";
880 reg = <0 0x00a90000 0 0x4000>;
882 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
883 pinctrl-names = "default";
884 pinctrl-0 = <&qup_i2c12_default>;
885 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
886 #address-cells = <1>;
892 compatible = "qcom,geni-spi";
893 reg = <0 0x00a90000 0 0x4000>;
895 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
896 pinctrl-names = "default";
897 pinctrl-0 = <&qup_spi12_default>;
898 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
899 #address-cells = <1>;
904 uart12: serial@a90000 {
905 compatible = "qcom,geni-uart";
906 reg = <0 0x00a90000 0 0x4000>;
908 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
909 pinctrl-names = "default";
910 pinctrl-0 = <&qup_uart12_default>;
911 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
916 compatible = "qcom,geni-i2c";
917 reg = <0 0x00a94000 0 0x4000>;
919 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
920 pinctrl-names = "default";
921 pinctrl-0 = <&qup_i2c13_default>;
922 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
923 #address-cells = <1>;
929 compatible = "qcom,geni-spi";
930 reg = <0 0x00a94000 0 0x4000>;
932 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
933 pinctrl-names = "default";
934 pinctrl-0 = <&qup_spi13_default>;
935 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
936 #address-cells = <1>;
941 uart13: serial@a94000 {
942 compatible = "qcom,geni-uart";
943 reg = <0 0x00a94000 0 0x4000>;
945 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
946 pinctrl-names = "default";
947 pinctrl-0 = <&qup_uart13_default>;
948 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
953 compatible = "qcom,geni-i2c";
954 reg = <0 0x00a98000 0 0x4000>;
956 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
957 pinctrl-names = "default";
958 pinctrl-0 = <&qup_i2c14_default>;
959 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
960 #address-cells = <1>;
966 compatible = "qcom,geni-spi";
967 reg = <0 0x00a98000 0 0x4000>;
969 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
970 pinctrl-names = "default";
971 pinctrl-0 = <&qup_spi14_default>;
972 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
973 #address-cells = <1>;
978 uart14: serial@a98000 {
979 compatible = "qcom,geni-uart";
980 reg = <0 0x00a98000 0 0x4000>;
982 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
983 pinctrl-names = "default";
984 pinctrl-0 = <&qup_uart14_default>;
985 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
990 compatible = "qcom,geni-i2c";
991 reg = <0 0x00a9c000 0 0x4000>;
993 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
994 pinctrl-names = "default";
995 pinctrl-0 = <&qup_i2c15_default>;
996 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
997 #address-cells = <1>;
1003 compatible = "qcom,geni-spi";
1004 reg = <0 0x00a9c000 0 0x4000>;
1006 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1007 pinctrl-names = "default";
1008 pinctrl-0 = <&qup_spi15_default>;
1009 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1010 #address-cells = <1>;
1012 status = "disabled";
1015 uart15: serial@a9c000 {
1016 compatible = "qcom,geni-uart";
1017 reg = <0 0x00a9c000 0 0x4000>;
1019 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1020 pinctrl-names = "default";
1021 pinctrl-0 = <&qup_uart15_default>;
1022 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1023 status = "disabled";
1027 ufs_mem_hc: ufshc@1d84000 {
1028 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
1030 reg = <0 0x01d84000 0 0x2500>;
1031 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1032 phys = <&ufs_mem_phy_lanes>;
1033 phy-names = "ufsphy";
1034 lanes-per-direction = <2>;
1035 power-domains = <&gcc UFS_PHY_GDSC>;
1037 iommus = <&apps_smmu 0x100 0xf>;
1045 "tx_lane0_sync_clk",
1046 "rx_lane0_sync_clk",
1047 "rx_lane1_sync_clk";
1049 <&gcc GCC_UFS_PHY_AXI_CLK>,
1050 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1051 <&gcc GCC_UFS_PHY_AHB_CLK>,
1052 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1053 <&rpmhcc RPMH_CXO_CLK>,
1054 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1055 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1056 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1058 <50000000 200000000>,
1061 <37500000 150000000>,
1067 status = "disabled";
1070 ufs_mem_phy: phy@1d87000 {
1071 compatible = "qcom,sdm845-qmp-ufs-phy";
1072 reg = <0 0x01d87000 0 0x18c>;
1073 #address-cells = <2>;
1076 clock-names = "ref",
1078 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
1079 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1081 status = "disabled";
1083 ufs_mem_phy_lanes: lanes@1d87400 {
1084 reg = <0 0x01d87400 0 0x108>,
1085 <0 0x01d87600 0 0x1e0>,
1086 <0 0x01d87c00 0 0x1dc>,
1087 <0 0x01d87800 0 0x108>,
1088 <0 0x01d87a00 0 0x1e0>;
1093 tcsr_mutex_regs: syscon@1f40000 {
1094 compatible = "syscon";
1095 reg = <0 0x01f40000 0 0x40000>;
1098 tlmm: pinctrl@3400000 {
1099 compatible = "qcom,sdm845-pinctrl";
1100 reg = <0 0x03400000 0 0xc00000>;
1101 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1104 interrupt-controller;
1105 #interrupt-cells = <2>;
1106 gpio-ranges = <&tlmm 0 0 150>;
1108 qspi_clk: qspi-clk {
1111 function = "qspi_clk";
1115 qspi_cs0: qspi-cs0 {
1118 function = "qspi_cs";
1122 qspi_cs1: qspi-cs1 {
1125 function = "qspi_cs";
1129 qspi_data01: qspi-data01 {
1131 pins = "gpio91", "gpio92";
1132 function = "qspi_data";
1136 qspi_data12: qspi-data12 {
1138 pins = "gpio93", "gpio94";
1139 function = "qspi_data";
1143 qup_i2c0_default: qup-i2c0-default {
1145 pins = "gpio0", "gpio1";
1150 qup_i2c1_default: qup-i2c1-default {
1152 pins = "gpio17", "gpio18";
1157 qup_i2c2_default: qup-i2c2-default {
1159 pins = "gpio27", "gpio28";
1164 qup_i2c3_default: qup-i2c3-default {
1166 pins = "gpio41", "gpio42";
1171 qup_i2c4_default: qup-i2c4-default {
1173 pins = "gpio89", "gpio90";
1178 qup_i2c5_default: qup-i2c5-default {
1180 pins = "gpio85", "gpio86";
1185 qup_i2c6_default: qup-i2c6-default {
1187 pins = "gpio45", "gpio46";
1192 qup_i2c7_default: qup-i2c7-default {
1194 pins = "gpio93", "gpio94";
1199 qup_i2c8_default: qup-i2c8-default {
1201 pins = "gpio65", "gpio66";
1206 qup_i2c9_default: qup-i2c9-default {
1208 pins = "gpio6", "gpio7";
1213 qup_i2c10_default: qup-i2c10-default {
1215 pins = "gpio55", "gpio56";
1220 qup_i2c11_default: qup-i2c11-default {
1222 pins = "gpio31", "gpio32";
1227 qup_i2c12_default: qup-i2c12-default {
1229 pins = "gpio49", "gpio50";
1234 qup_i2c13_default: qup-i2c13-default {
1236 pins = "gpio105", "gpio106";
1241 qup_i2c14_default: qup-i2c14-default {
1243 pins = "gpio33", "gpio34";
1248 qup_i2c15_default: qup-i2c15-default {
1250 pins = "gpio81", "gpio82";
1255 qup_spi0_default: qup-spi0-default {
1257 pins = "gpio0", "gpio1",
1263 qup_spi1_default: qup-spi1-default {
1265 pins = "gpio17", "gpio18",
1271 qup_spi2_default: qup-spi2-default {
1273 pins = "gpio27", "gpio28",
1279 qup_spi3_default: qup-spi3-default {
1281 pins = "gpio41", "gpio42",
1287 qup_spi4_default: qup-spi4-default {
1289 pins = "gpio89", "gpio90",
1295 qup_spi5_default: qup-spi5-default {
1297 pins = "gpio85", "gpio86",
1303 qup_spi6_default: qup-spi6-default {
1305 pins = "gpio45", "gpio46",
1311 qup_spi7_default: qup-spi7-default {
1313 pins = "gpio93", "gpio94",
1319 qup_spi8_default: qup-spi8-default {
1321 pins = "gpio65", "gpio66",
1327 qup_spi9_default: qup-spi9-default {
1329 pins = "gpio6", "gpio7",
1335 qup_spi10_default: qup-spi10-default {
1337 pins = "gpio55", "gpio56",
1343 qup_spi11_default: qup-spi11-default {
1345 pins = "gpio31", "gpio32",
1351 qup_spi12_default: qup-spi12-default {
1353 pins = "gpio49", "gpio50",
1359 qup_spi13_default: qup-spi13-default {
1361 pins = "gpio105", "gpio106",
1362 "gpio107", "gpio108";
1367 qup_spi14_default: qup-spi14-default {
1369 pins = "gpio33", "gpio34",
1375 qup_spi15_default: qup-spi15-default {
1377 pins = "gpio81", "gpio82",
1383 qup_uart0_default: qup-uart0-default {
1385 pins = "gpio2", "gpio3";
1390 qup_uart1_default: qup-uart1-default {
1392 pins = "gpio19", "gpio20";
1397 qup_uart2_default: qup-uart2-default {
1399 pins = "gpio29", "gpio30";
1404 qup_uart3_default: qup-uart3-default {
1406 pins = "gpio43", "gpio44";
1411 qup_uart4_default: qup-uart4-default {
1413 pins = "gpio91", "gpio92";
1418 qup_uart5_default: qup-uart5-default {
1420 pins = "gpio87", "gpio88";
1425 qup_uart6_default: qup-uart6-default {
1427 pins = "gpio47", "gpio48";
1432 qup_uart7_default: qup-uart7-default {
1434 pins = "gpio95", "gpio96";
1439 qup_uart8_default: qup-uart8-default {
1441 pins = "gpio67", "gpio68";
1446 qup_uart9_default: qup-uart9-default {
1448 pins = "gpio4", "gpio5";
1453 qup_uart10_default: qup-uart10-default {
1455 pins = "gpio53", "gpio54";
1460 qup_uart11_default: qup-uart11-default {
1462 pins = "gpio33", "gpio34";
1467 qup_uart12_default: qup-uart12-default {
1469 pins = "gpio51", "gpio52";
1474 qup_uart13_default: qup-uart13-default {
1476 pins = "gpio107", "gpio108";
1481 qup_uart14_default: qup-uart14-default {
1483 pins = "gpio31", "gpio32";
1488 qup_uart15_default: qup-uart15-default {
1490 pins = "gpio83", "gpio84";
1496 gpucc: clock-controller@5090000 {
1497 compatible = "qcom,sdm845-gpucc";
1498 reg = <0 0x05090000 0 0x9000>;
1501 #power-domain-cells = <1>;
1502 clocks = <&rpmhcc RPMH_CXO_CLK>;
1506 sdhc_2: sdhci@8804000 {
1507 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
1508 reg = <0 0x08804000 0 0x1000>;
1510 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1511 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1512 interrupt-names = "hc_irq", "pwr_irq";
1514 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1515 <&gcc GCC_SDCC2_APPS_CLK>;
1516 clock-names = "iface", "core";
1517 iommus = <&apps_smmu 0xa0 0xf>;
1519 status = "disabled";
1523 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
1524 reg = <0 0x088df000 0 0x600>;
1525 #address-cells = <1>;
1527 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1528 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
1529 <&gcc GCC_QSPI_CORE_CLK>;
1530 clock-names = "iface", "core";
1531 status = "disabled";
1534 usb_1_hsphy: phy@88e2000 {
1535 compatible = "qcom,sdm845-qusb2-phy";
1536 reg = <0 0x088e2000 0 0x400>;
1537 status = "disabled";
1540 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1541 <&rpmhcc RPMH_CXO_CLK>;
1542 clock-names = "cfg_ahb", "ref";
1544 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1546 nvmem-cells = <&qusb2p_hstx_trim>;
1549 usb_2_hsphy: phy@88e3000 {
1550 compatible = "qcom,sdm845-qusb2-phy";
1551 reg = <0 0x088e3000 0 0x400>;
1552 status = "disabled";
1555 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1556 <&rpmhcc RPMH_CXO_CLK>;
1557 clock-names = "cfg_ahb", "ref";
1559 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1561 nvmem-cells = <&qusb2s_hstx_trim>;
1564 usb_1_qmpphy: phy@88e9000 {
1565 compatible = "qcom,sdm845-qmp-usb3-phy";
1566 reg = <0 0x088e9000 0 0x18c>,
1567 <0 0x088e8000 0 0x10>;
1568 reg-names = "reg-base", "dp_com";
1569 status = "disabled";
1571 #address-cells = <2>;
1575 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1576 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1577 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
1578 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
1579 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
1581 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
1582 <&gcc GCC_USB3_PHY_PRIM_BCR>;
1583 reset-names = "phy", "common";
1585 usb_1_ssphy: lanes@88e9200 {
1586 reg = <0 0x088e9200 0 0x128>,
1587 <0 0x088e9400 0 0x200>,
1588 <0 0x088e9c00 0 0x218>,
1589 <0 0x088e9600 0 0x128>,
1590 <0 0x088e9800 0 0x200>,
1591 <0 0x088e9a00 0 0x100>;
1593 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1594 clock-names = "pipe0";
1595 clock-output-names = "usb3_phy_pipe_clk_src";
1599 usb_2_qmpphy: phy@88eb000 {
1600 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
1601 reg = <0 0x088eb000 0 0x18c>;
1602 status = "disabled";
1604 #address-cells = <2>;
1608 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
1609 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1610 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
1611 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
1612 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
1614 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
1615 <&gcc GCC_USB3_PHY_SEC_BCR>;
1616 reset-names = "phy", "common";
1618 usb_2_ssphy: lane@88eb200 {
1619 reg = <0 0x088eb200 0 0x128>,
1620 <0 0x088eb400 0 0x1fc>,
1621 <0 0x088eb800 0 0x218>,
1622 <0 0x088eb600 0 0x70>;
1624 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
1625 clock-names = "pipe0";
1626 clock-output-names = "usb3_uni_phy_pipe_clk_src";
1630 usb_1: usb@a6f8800 {
1631 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
1632 reg = <0 0x0a6f8800 0 0x400>;
1633 status = "disabled";
1634 #address-cells = <2>;
1639 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1640 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1641 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1642 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1643 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
1644 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1647 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1648 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1649 assigned-clock-rates = <19200000>, <150000000>;
1651 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1652 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
1653 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
1654 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
1655 interrupt-names = "hs_phy_irq", "ss_phy_irq",
1656 "dm_hs_phy_irq", "dp_hs_phy_irq";
1658 power-domains = <&gcc USB30_PRIM_GDSC>;
1660 resets = <&gcc GCC_USB30_PRIM_BCR>;
1662 usb_1_dwc3: dwc3@a600000 {
1663 compatible = "snps,dwc3";
1664 reg = <0 0x0a600000 0 0xcd00>;
1665 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1666 iommus = <&apps_smmu 0x740 0>;
1667 snps,dis_u2_susphy_quirk;
1668 snps,dis_enblslpm_quirk;
1669 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1670 phy-names = "usb2-phy", "usb3-phy";
1674 usb_2: usb@a8f8800 {
1675 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
1676 reg = <0 0x0a8f8800 0 0x400>;
1677 status = "disabled";
1678 #address-cells = <2>;
1683 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1684 <&gcc GCC_USB30_SEC_MASTER_CLK>,
1685 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1686 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1687 <&gcc GCC_USB30_SEC_SLEEP_CLK>;
1688 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1691 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1692 <&gcc GCC_USB30_SEC_MASTER_CLK>;
1693 assigned-clock-rates = <19200000>, <150000000>;
1695 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1696 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
1697 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
1698 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
1699 interrupt-names = "hs_phy_irq", "ss_phy_irq",
1700 "dm_hs_phy_irq", "dp_hs_phy_irq";
1702 power-domains = <&gcc USB30_SEC_GDSC>;
1704 resets = <&gcc GCC_USB30_SEC_BCR>;
1706 usb_2_dwc3: dwc3@a800000 {
1707 compatible = "snps,dwc3";
1708 reg = <0 0x0a800000 0 0xcd00>;
1709 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1710 iommus = <&apps_smmu 0x760 0>;
1711 snps,dis_u2_susphy_quirk;
1712 snps,dis_enblslpm_quirk;
1713 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
1714 phy-names = "usb2-phy", "usb3-phy";
1718 videocc: clock-controller@ab00000 {
1719 compatible = "qcom,sdm845-videocc";
1720 reg = <0 0x0ab00000 0 0x10000>;
1722 #power-domain-cells = <1>;
1726 mdss: mdss@ae00000 {
1727 compatible = "qcom,sdm845-mdss";
1728 reg = <0 0x0ae00000 0 0x1000>;
1731 power-domains = <&dispcc MDSS_GDSC>;
1733 clocks = <&gcc GCC_DISP_AHB_CLK>,
1734 <&gcc GCC_DISP_AXI_CLK>,
1735 <&dispcc DISP_CC_MDSS_MDP_CLK>;
1736 clock-names = "iface", "bus", "core";
1738 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
1739 assigned-clock-rates = <300000000>;
1741 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1742 interrupt-controller;
1743 #interrupt-cells = <1>;
1745 iommus = <&apps_smmu 0x880 0x8>,
1746 <&apps_smmu 0xc80 0x8>;
1748 status = "disabled";
1750 #address-cells = <2>;
1754 mdss_mdp: mdp@ae01000 {
1755 compatible = "qcom,sdm845-dpu";
1756 reg = <0 0x0ae01000 0 0x8f000>,
1757 <0 0x0aeb0000 0 0x2008>;
1758 reg-names = "mdp", "vbif";
1760 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
1761 <&dispcc DISP_CC_MDSS_AXI_CLK>,
1762 <&dispcc DISP_CC_MDSS_MDP_CLK>,
1763 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1764 clock-names = "iface", "bus", "core", "vsync";
1766 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
1767 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1768 assigned-clock-rates = <300000000>,
1771 interrupt-parent = <&mdss>;
1772 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
1774 status = "disabled";
1777 #address-cells = <1>;
1782 dpu_intf1_out: endpoint {
1783 remote-endpoint = <&dsi0_in>;
1789 dpu_intf2_out: endpoint {
1790 remote-endpoint = <&dsi1_in>;
1797 compatible = "qcom,mdss-dsi-ctrl";
1798 reg = <0 0x0ae94000 0 0x400>;
1799 reg-names = "dsi_ctrl";
1801 interrupt-parent = <&mdss>;
1802 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
1804 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
1805 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
1806 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
1807 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
1808 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1809 <&dispcc DISP_CC_MDSS_AXI_CLK>;
1810 clock-names = "byte",
1820 status = "disabled";
1822 #address-cells = <1>;
1826 #address-cells = <1>;
1832 remote-endpoint = <&dpu_intf1_out>;
1838 dsi0_out: endpoint {
1844 dsi0_phy: dsi-phy@ae94400 {
1845 compatible = "qcom,dsi-phy-10nm";
1846 reg = <0 0x0ae94400 0 0x200>,
1847 <0 0x0ae94600 0 0x280>,
1848 <0 0x0ae94a00 0 0x1e0>;
1849 reg-names = "dsi_phy",
1856 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
1857 clock-names = "iface";
1859 status = "disabled";
1863 compatible = "qcom,mdss-dsi-ctrl";
1864 reg = <0 0x0ae96000 0 0x400>;
1865 reg-names = "dsi_ctrl";
1867 interrupt-parent = <&mdss>;
1868 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
1870 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
1871 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
1872 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
1873 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
1874 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1875 <&dispcc DISP_CC_MDSS_AXI_CLK>;
1876 clock-names = "byte",
1886 status = "disabled";
1888 #address-cells = <1>;
1892 #address-cells = <1>;
1898 remote-endpoint = <&dpu_intf2_out>;
1904 dsi1_out: endpoint {
1910 dsi1_phy: dsi-phy@ae96400 {
1911 compatible = "qcom,dsi-phy-10nm";
1912 reg = <0 0x0ae96400 0 0x200>,
1913 <0 0x0ae96600 0 0x280>,
1914 <0 0x0ae96a00 0 0x10e>;
1915 reg-names = "dsi_phy",
1922 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
1923 clock-names = "iface";
1925 status = "disabled";
1929 dispcc: clock-controller@af00000 {
1930 compatible = "qcom,sdm845-dispcc";
1931 reg = <0 0x0af00000 0 0x10000>;
1934 #power-domain-cells = <1>;
1937 pdc_reset: reset-controller@b2e0000 {
1938 compatible = "qcom,sdm845-pdc-global";
1939 reg = <0 0x0b2e0000 0 0x20000>;
1943 tsens0: thermal-sensor@c263000 {
1944 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
1945 reg = <0 0x0c263000 0 0x1ff>, /* TM */
1946 <0 0x0c222000 0 0x1ff>; /* SROT */
1947 #qcom,sensors = <13>;
1948 #thermal-sensor-cells = <1>;
1951 tsens1: thermal-sensor@c265000 {
1952 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
1953 reg = <0 0x0c265000 0 0x1ff>, /* TM */
1954 <0 0x0c223000 0 0x1ff>; /* SROT */
1955 #qcom,sensors = <8>;
1956 #thermal-sensor-cells = <1>;
1959 aoss_reset: reset-controller@c2a0000 {
1960 compatible = "qcom,sdm845-aoss-cc";
1961 reg = <0 0x0c2a0000 0 0x31000>;
1965 spmi_bus: spmi@c440000 {
1966 compatible = "qcom,spmi-pmic-arb";
1967 reg = <0 0x0c440000 0 0x1100>,
1968 <0 0x0c600000 0 0x2000000>,
1969 <0 0x0e600000 0 0x100000>,
1970 <0 0x0e700000 0 0xa0000>,
1971 <0 0x0c40a000 0 0x26000>;
1972 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1973 interrupt-names = "periph_irq";
1974 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
1977 #address-cells = <2>;
1979 interrupt-controller;
1980 #interrupt-cells = <4>;
1984 apps_smmu: iommu@15000000 {
1985 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
1986 reg = <0 0x15000000 0 0x80000>;
1988 #global-interrupts = <1>;
1989 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1990 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1991 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1992 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1993 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1994 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1995 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1996 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1997 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1998 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1999 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2000 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2001 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2002 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2003 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2004 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2005 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2006 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2007 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2008 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2009 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2010 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2011 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2012 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2013 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
2014 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
2015 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
2016 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
2017 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
2018 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
2019 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
2020 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
2021 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
2022 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
2023 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
2024 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
2025 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
2026 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
2027 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
2028 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
2029 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
2030 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2031 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2032 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2033 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2034 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2035 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2036 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2037 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2038 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2039 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2040 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2041 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2042 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2043 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2044 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2045 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2046 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2047 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2048 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2049 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2050 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2051 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2052 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2053 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
2056 lpasscc: clock-controller@17014000 {
2057 compatible = "qcom,sdm845-lpasscc";
2058 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
2059 reg-names = "cc", "qdsp6ss";
2061 status = "disabled";
2064 apss_shared: mailbox@17990000 {
2065 compatible = "qcom,sdm845-apss-shared";
2066 reg = <0 0x17990000 0 0x1000>;
2070 apps_rsc: rsc@179c0000 {
2072 compatible = "qcom,rpmh-rsc";
2073 reg = <0 0x179c0000 0 0x10000>,
2074 <0 0x179d0000 0 0x10000>,
2075 <0 0x179e0000 0 0x10000>;
2076 reg-names = "drv-0", "drv-1", "drv-2";
2077 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2078 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2079 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
2080 qcom,tcs-offset = <0xd00>;
2082 qcom,tcs-config = <ACTIVE_TCS 2>,
2087 rpmhcc: clock-controller {
2088 compatible = "qcom,sdm845-rpmh-clk";
2092 rpmhpd: power-controller {
2093 compatible = "qcom,sdm845-rpmhpd";
2094 #power-domain-cells = <1>;
2095 operating-points-v2 = <&rpmhpd_opp_table>;
2097 rpmhpd_opp_table: opp-table {
2098 compatible = "operating-points-v2";
2100 rpmhpd_opp_ret: opp1 {
2104 rpmhpd_opp_min_svs: opp2 {
2108 rpmhpd_opp_low_svs: opp3 {
2112 rpmhpd_opp_svs: opp4 {
2116 rpmhpd_opp_svs_l1: opp5 {
2120 rpmhpd_opp_nom: opp6 {
2124 rpmhpd_opp_nom_l1: opp7 {
2128 rpmhpd_opp_nom_l2: opp8 {
2132 rpmhpd_opp_turbo: opp9 {
2136 rpmhpd_opp_turbo_l1: opp10 {
2142 rsc_hlos: interconnect {
2143 compatible = "qcom,sdm845-rsc-hlos";
2144 #interconnect-cells = <1>;
2148 intc: interrupt-controller@17a00000 {
2149 compatible = "arm,gic-v3";
2150 #address-cells = <2>;
2153 #interrupt-cells = <3>;
2154 interrupt-controller;
2155 reg = <0 0x17a00000 0 0x10000>, /* GICD */
2156 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
2157 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2160 compatible = "arm,gic-v3-its";
2163 reg = <0 0x17a40000 0 0x20000>;
2164 status = "disabled";
2169 #address-cells = <2>;
2172 compatible = "arm,armv7-timer-mem";
2173 reg = <0 0x17c90000 0 0x1000>;
2177 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
2178 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
2179 reg = <0 0x17ca0000 0 0x1000>,
2180 <0 0x17cb0000 0 0x1000>;
2185 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
2186 reg = <0 0x17cc0000 0 0x1000>;
2187 status = "disabled";
2192 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2193 reg = <0 0x17cd0000 0 0x1000>;
2194 status = "disabled";
2199 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2200 reg = <0 0x17ce0000 0 0x1000>;
2201 status = "disabled";
2206 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2207 reg = <0 0x17cf0000 0 0x1000>;
2208 status = "disabled";
2213 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2214 reg = <0 0x17d00000 0 0x1000>;
2215 status = "disabled";
2220 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2221 reg = <0 0x17d10000 0 0x1000>;
2222 status = "disabled";
2226 cpufreq_hw: cpufreq@17d43000 {
2227 compatible = "qcom,cpufreq-hw";
2228 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
2229 reg-names = "freq-domain0", "freq-domain1";
2231 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
2232 clock-names = "xo", "alternate";
2234 #freq-domain-cells = <1>;
2237 wifi: wifi@18800000 {
2238 compatible = "qcom,wcn3990-wifi";
2239 status = "disabled";
2240 reg = <0 0x18800000 0 0x800000>;
2241 reg-names = "membase";
2242 memory-region = <&wlan_msa_mem>;
2243 clock-names = "cxo_ref_clk_pin";
2244 clocks = <&rpmhcc RPMH_RF_CLK2>;
2246 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
2247 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
2248 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
2249 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
2250 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2251 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
2252 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
2253 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2254 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2255 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2256 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2257 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
2258 iommus = <&apps_smmu 0x0040 0x1>;
2264 polling-delay-passive = <250>;
2265 polling-delay = <1000>;
2267 thermal-sensors = <&tsens0 1>;
2270 cpu0_alert0: trip-point@0 {
2271 temperature = <90000>;
2272 hysteresis = <2000>;
2276 cpu0_alert1: trip-point@1 {
2277 temperature = <95000>;
2278 hysteresis = <2000>;
2282 cpu0_crit: cpu_crit {
2283 temperature = <110000>;
2284 hysteresis = <1000>;
2291 trip = <&cpu0_alert0>;
2292 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2293 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2294 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2295 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2298 trip = <&cpu0_alert1>;
2299 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2300 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2301 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2302 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2308 polling-delay-passive = <250>;
2309 polling-delay = <1000>;
2311 thermal-sensors = <&tsens0 2>;
2314 cpu1_alert0: trip-point@0 {
2315 temperature = <90000>;
2316 hysteresis = <2000>;
2320 cpu1_alert1: trip-point@1 {
2321 temperature = <95000>;
2322 hysteresis = <2000>;
2326 cpu1_crit: cpu_crit {
2327 temperature = <110000>;
2328 hysteresis = <1000>;
2335 trip = <&cpu1_alert0>;
2336 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2337 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2338 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2339 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2342 trip = <&cpu1_alert1>;
2343 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2344 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2345 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2346 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2352 polling-delay-passive = <250>;
2353 polling-delay = <1000>;
2355 thermal-sensors = <&tsens0 3>;
2358 cpu2_alert0: trip-point@0 {
2359 temperature = <90000>;
2360 hysteresis = <2000>;
2364 cpu2_alert1: trip-point@1 {
2365 temperature = <95000>;
2366 hysteresis = <2000>;
2370 cpu2_crit: cpu_crit {
2371 temperature = <110000>;
2372 hysteresis = <1000>;
2379 trip = <&cpu2_alert0>;
2380 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2381 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2382 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2383 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2386 trip = <&cpu2_alert1>;
2387 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2388 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2389 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2390 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2396 polling-delay-passive = <250>;
2397 polling-delay = <1000>;
2399 thermal-sensors = <&tsens0 4>;
2402 cpu3_alert0: trip-point@0 {
2403 temperature = <90000>;
2404 hysteresis = <2000>;
2408 cpu3_alert1: trip-point@1 {
2409 temperature = <95000>;
2410 hysteresis = <2000>;
2414 cpu3_crit: cpu_crit {
2415 temperature = <110000>;
2416 hysteresis = <1000>;
2423 trip = <&cpu3_alert0>;
2424 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2425 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2426 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2427 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2430 trip = <&cpu3_alert1>;
2431 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2432 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2433 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2434 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2440 polling-delay-passive = <250>;
2441 polling-delay = <1000>;
2443 thermal-sensors = <&tsens0 7>;
2446 cpu4_alert0: trip-point@0 {
2447 temperature = <90000>;
2448 hysteresis = <2000>;
2452 cpu4_alert1: trip-point@1 {
2453 temperature = <95000>;
2454 hysteresis = <2000>;
2458 cpu4_crit: cpu_crit {
2459 temperature = <110000>;
2460 hysteresis = <1000>;
2467 trip = <&cpu4_alert0>;
2468 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2469 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2470 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2471 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2474 trip = <&cpu4_alert1>;
2475 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2476 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2477 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2478 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2484 polling-delay-passive = <250>;
2485 polling-delay = <1000>;
2487 thermal-sensors = <&tsens0 8>;
2490 cpu5_alert0: trip-point@0 {
2491 temperature = <90000>;
2492 hysteresis = <2000>;
2496 cpu5_alert1: trip-point@1 {
2497 temperature = <95000>;
2498 hysteresis = <2000>;
2502 cpu5_crit: cpu_crit {
2503 temperature = <110000>;
2504 hysteresis = <1000>;
2511 trip = <&cpu5_alert0>;
2512 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2513 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2514 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2515 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2518 trip = <&cpu5_alert1>;
2519 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2520 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2521 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2522 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2528 polling-delay-passive = <250>;
2529 polling-delay = <1000>;
2531 thermal-sensors = <&tsens0 9>;
2534 cpu6_alert0: trip-point@0 {
2535 temperature = <90000>;
2536 hysteresis = <2000>;
2540 cpu6_alert1: trip-point@1 {
2541 temperature = <95000>;
2542 hysteresis = <2000>;
2546 cpu6_crit: cpu_crit {
2547 temperature = <110000>;
2548 hysteresis = <1000>;
2555 trip = <&cpu6_alert0>;
2556 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2557 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2558 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2559 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2562 trip = <&cpu6_alert1>;
2563 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2564 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2565 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2566 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2572 polling-delay-passive = <250>;
2573 polling-delay = <1000>;
2575 thermal-sensors = <&tsens0 10>;
2578 cpu7_alert0: trip-point@0 {
2579 temperature = <90000>;
2580 hysteresis = <2000>;
2584 cpu7_alert1: trip-point@1 {
2585 temperature = <95000>;
2586 hysteresis = <2000>;
2590 cpu7_crit: cpu_crit {
2591 temperature = <110000>;
2592 hysteresis = <1000>;
2599 trip = <&cpu7_alert0>;
2600 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2601 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2602 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2603 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2606 trip = <&cpu7_alert1>;
2607 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2608 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2609 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2610 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;