1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sm8250.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/power/qcom-aoss-qmp.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/soc/qcom,apr.h>
19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
20 #include <dt-bindings/sound/qcom,q6afe.h>
21 #include <dt-bindings/thermal/thermal.h>
22 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
25 interrupt-parent = <&intc>;
77 compatible = "fixed-clock";
79 clock-frequency = <38400000>;
80 clock-output-names = "xo_board";
83 sleep_clk: sleep-clk {
84 compatible = "fixed-clock";
85 clock-frequency = <32768>;
96 compatible = "qcom,kryo485";
98 enable-method = "psci";
99 capacity-dmips-mhz = <448>;
100 dynamic-power-coefficient = <205>;
101 next-level-cache = <&L2_0>;
102 qcom,freq-domain = <&cpufreq_hw 0>;
103 #cooling-cells = <2>;
105 compatible = "cache";
106 next-level-cache = <&L3_0>;
108 compatible = "cache";
115 compatible = "qcom,kryo485";
117 enable-method = "psci";
118 capacity-dmips-mhz = <448>;
119 dynamic-power-coefficient = <205>;
120 next-level-cache = <&L2_100>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
122 #cooling-cells = <2>;
124 compatible = "cache";
125 next-level-cache = <&L3_0>;
131 compatible = "qcom,kryo485";
133 enable-method = "psci";
134 capacity-dmips-mhz = <448>;
135 dynamic-power-coefficient = <205>;
136 next-level-cache = <&L2_200>;
137 qcom,freq-domain = <&cpufreq_hw 0>;
138 #cooling-cells = <2>;
140 compatible = "cache";
141 next-level-cache = <&L3_0>;
147 compatible = "qcom,kryo485";
149 enable-method = "psci";
150 capacity-dmips-mhz = <448>;
151 dynamic-power-coefficient = <205>;
152 next-level-cache = <&L2_300>;
153 qcom,freq-domain = <&cpufreq_hw 0>;
154 #cooling-cells = <2>;
156 compatible = "cache";
157 next-level-cache = <&L3_0>;
163 compatible = "qcom,kryo485";
165 enable-method = "psci";
166 capacity-dmips-mhz = <1024>;
167 dynamic-power-coefficient = <379>;
168 next-level-cache = <&L2_400>;
169 qcom,freq-domain = <&cpufreq_hw 1>;
170 #cooling-cells = <2>;
172 compatible = "cache";
173 next-level-cache = <&L3_0>;
179 compatible = "qcom,kryo485";
181 enable-method = "psci";
182 capacity-dmips-mhz = <1024>;
183 dynamic-power-coefficient = <379>;
184 next-level-cache = <&L2_500>;
185 qcom,freq-domain = <&cpufreq_hw 1>;
186 #cooling-cells = <2>;
188 compatible = "cache";
189 next-level-cache = <&L3_0>;
196 compatible = "qcom,kryo485";
198 enable-method = "psci";
199 capacity-dmips-mhz = <1024>;
200 dynamic-power-coefficient = <379>;
201 next-level-cache = <&L2_600>;
202 qcom,freq-domain = <&cpufreq_hw 1>;
203 #cooling-cells = <2>;
205 compatible = "cache";
206 next-level-cache = <&L3_0>;
212 compatible = "qcom,kryo485";
214 enable-method = "psci";
215 capacity-dmips-mhz = <1024>;
216 dynamic-power-coefficient = <444>;
217 next-level-cache = <&L2_700>;
218 qcom,freq-domain = <&cpufreq_hw 2>;
219 #cooling-cells = <2>;
221 compatible = "cache";
222 next-level-cache = <&L3_0>;
265 compatible = "qcom,scm";
271 device_type = "memory";
272 /* We expect the bootloader to fill in the size */
273 reg = <0x0 0x80000000 0x0 0x0>;
277 compatible = "regulator-fixed-domain";
278 power-domains = <&rpmhpd SM8250_MMCX>;
279 required-opps = <&rpmhpd_opp_low_svs>;
280 regulator-name = "MMCX";
284 compatible = "arm,armv8-pmuv3";
285 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
289 compatible = "arm,psci-1.0";
294 #address-cells = <2>;
298 hyp_mem: memory@80000000 {
299 reg = <0x0 0x80000000 0x0 0x600000>;
303 xbl_aop_mem: memory@80700000 {
304 reg = <0x0 0x80700000 0x0 0x160000>;
308 cmd_db: memory@80860000 {
309 compatible = "qcom,cmd-db";
310 reg = <0x0 0x80860000 0x0 0x20000>;
314 smem_mem: memory@80900000 {
315 reg = <0x0 0x80900000 0x0 0x200000>;
319 removed_mem: memory@80b00000 {
320 reg = <0x0 0x80b00000 0x0 0x5300000>;
324 camera_mem: memory@86200000 {
325 reg = <0x0 0x86200000 0x0 0x500000>;
329 wlan_mem: memory@86700000 {
330 reg = <0x0 0x86700000 0x0 0x100000>;
334 ipa_fw_mem: memory@86800000 {
335 reg = <0x0 0x86800000 0x0 0x10000>;
339 ipa_gsi_mem: memory@86810000 {
340 reg = <0x0 0x86810000 0x0 0xa000>;
344 gpu_mem: memory@8681a000 {
345 reg = <0x0 0x8681a000 0x0 0x2000>;
349 npu_mem: memory@86900000 {
350 reg = <0x0 0x86900000 0x0 0x500000>;
354 video_mem: memory@86e00000 {
355 reg = <0x0 0x86e00000 0x0 0x500000>;
359 cvp_mem: memory@87300000 {
360 reg = <0x0 0x87300000 0x0 0x500000>;
364 cdsp_mem: memory@87800000 {
365 reg = <0x0 0x87800000 0x0 0x1400000>;
369 slpi_mem: memory@88c00000 {
370 reg = <0x0 0x88c00000 0x0 0x1500000>;
374 adsp_mem: memory@8a100000 {
375 reg = <0x0 0x8a100000 0x0 0x1d00000>;
379 spss_mem: memory@8be00000 {
380 reg = <0x0 0x8be00000 0x0 0x100000>;
384 cdsp_secure_heap: memory@8bf00000 {
385 reg = <0x0 0x8bf00000 0x0 0x4600000>;
391 compatible = "qcom,smem";
392 memory-region = <&smem_mem>;
393 hwlocks = <&tcsr_mutex 3>;
397 compatible = "qcom,smp2p";
398 qcom,smem = <443>, <429>;
399 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
400 IPCC_MPROC_SIGNAL_SMP2P
401 IRQ_TYPE_EDGE_RISING>;
402 mboxes = <&ipcc IPCC_CLIENT_LPASS
403 IPCC_MPROC_SIGNAL_SMP2P>;
405 qcom,local-pid = <0>;
406 qcom,remote-pid = <2>;
408 smp2p_adsp_out: master-kernel {
409 qcom,entry-name = "master-kernel";
410 #qcom,smem-state-cells = <1>;
413 smp2p_adsp_in: slave-kernel {
414 qcom,entry-name = "slave-kernel";
415 interrupt-controller;
416 #interrupt-cells = <2>;
421 compatible = "qcom,smp2p";
422 qcom,smem = <94>, <432>;
423 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
424 IPCC_MPROC_SIGNAL_SMP2P
425 IRQ_TYPE_EDGE_RISING>;
426 mboxes = <&ipcc IPCC_CLIENT_CDSP
427 IPCC_MPROC_SIGNAL_SMP2P>;
429 qcom,local-pid = <0>;
430 qcom,remote-pid = <5>;
432 smp2p_cdsp_out: master-kernel {
433 qcom,entry-name = "master-kernel";
434 #qcom,smem-state-cells = <1>;
437 smp2p_cdsp_in: slave-kernel {
438 qcom,entry-name = "slave-kernel";
439 interrupt-controller;
440 #interrupt-cells = <2>;
445 compatible = "qcom,smp2p";
446 qcom,smem = <481>, <430>;
447 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
448 IPCC_MPROC_SIGNAL_SMP2P
449 IRQ_TYPE_EDGE_RISING>;
450 mboxes = <&ipcc IPCC_CLIENT_SLPI
451 IPCC_MPROC_SIGNAL_SMP2P>;
453 qcom,local-pid = <0>;
454 qcom,remote-pid = <3>;
456 smp2p_slpi_out: master-kernel {
457 qcom,entry-name = "master-kernel";
458 #qcom,smem-state-cells = <1>;
461 smp2p_slpi_in: slave-kernel {
462 qcom,entry-name = "slave-kernel";
463 interrupt-controller;
464 #interrupt-cells = <2>;
469 #address-cells = <2>;
471 ranges = <0 0 0 0 0x10 0>;
472 dma-ranges = <0 0 0 0 0x10 0>;
473 compatible = "simple-bus";
475 gcc: clock-controller@100000 {
476 compatible = "qcom,gcc-sm8250";
477 reg = <0x0 0x00100000 0x0 0x1f0000>;
480 #power-domain-cells = <1>;
481 clock-names = "bi_tcxo",
484 clocks = <&rpmhcc RPMH_CXO_CLK>,
485 <&rpmhcc RPMH_CXO_CLK_A>,
489 ipcc: mailbox@408000 {
490 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
491 reg = <0 0x00408000 0 0x1000>;
492 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
493 interrupt-controller;
494 #interrupt-cells = <3>;
499 compatible = "qcom,prng-ee";
500 reg = <0 0x00793000 0 0x1000>;
501 clocks = <&gcc GCC_PRNG_AHB_CLK>;
502 clock-names = "core";
505 qup_opp_table: qup-opp-table {
506 compatible = "operating-points-v2";
509 opp-hz = /bits/ 64 <50000000>;
510 required-opps = <&rpmhpd_opp_min_svs>;
514 opp-hz = /bits/ 64 <75000000>;
515 required-opps = <&rpmhpd_opp_low_svs>;
519 opp-hz = /bits/ 64 <120000000>;
520 required-opps = <&rpmhpd_opp_svs>;
524 gpi_dma2: dma-controller@800000 {
525 compatible = "qcom,sm8250-gpi-dma";
526 reg = <0 0x00800000 0 0x70000>;
527 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
538 dma-channel-mask = <0x3f>;
539 iommus = <&apps_smmu 0x76 0x0>;
544 qupv3_id_2: geniqup@8c0000 {
545 compatible = "qcom,geni-se-qup";
546 reg = <0x0 0x008c0000 0x0 0x6000>;
547 clock-names = "m-ahb", "s-ahb";
548 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
549 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
550 #address-cells = <2>;
552 iommus = <&apps_smmu 0x63 0x0>;
557 compatible = "qcom,geni-i2c";
558 reg = <0 0x00880000 0 0x4000>;
560 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
561 pinctrl-names = "default";
562 pinctrl-0 = <&qup_i2c14_default>;
563 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
564 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
565 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
566 dma-names = "tx", "rx";
567 #address-cells = <1>;
573 compatible = "qcom,geni-spi";
574 reg = <0 0x00880000 0 0x4000>;
576 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
577 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
578 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
579 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
580 dma-names = "tx", "rx";
581 power-domains = <&rpmhpd SM8250_CX>;
582 operating-points-v2 = <&qup_opp_table>;
583 #address-cells = <1>;
589 compatible = "qcom,geni-i2c";
590 reg = <0 0x00884000 0 0x4000>;
592 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
593 pinctrl-names = "default";
594 pinctrl-0 = <&qup_i2c15_default>;
595 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
596 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
597 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
598 dma-names = "tx", "rx";
599 #address-cells = <1>;
605 compatible = "qcom,geni-spi";
606 reg = <0 0x00884000 0 0x4000>;
608 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
609 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
610 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
611 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
612 dma-names = "tx", "rx";
613 power-domains = <&rpmhpd SM8250_CX>;
614 operating-points-v2 = <&qup_opp_table>;
615 #address-cells = <1>;
621 compatible = "qcom,geni-i2c";
622 reg = <0 0x00888000 0 0x4000>;
624 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
625 pinctrl-names = "default";
626 pinctrl-0 = <&qup_i2c16_default>;
627 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
628 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
629 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
630 dma-names = "tx", "rx";
631 #address-cells = <1>;
637 compatible = "qcom,geni-spi";
638 reg = <0 0x00888000 0 0x4000>;
640 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
641 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
642 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
643 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
644 dma-names = "tx", "rx";
645 power-domains = <&rpmhpd SM8250_CX>;
646 operating-points-v2 = <&qup_opp_table>;
647 #address-cells = <1>;
653 compatible = "qcom,geni-i2c";
654 reg = <0 0x0088c000 0 0x4000>;
656 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
657 pinctrl-names = "default";
658 pinctrl-0 = <&qup_i2c17_default>;
659 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
660 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
661 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
662 dma-names = "tx", "rx";
663 #address-cells = <1>;
669 compatible = "qcom,geni-spi";
670 reg = <0 0x0088c000 0 0x4000>;
672 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
673 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
674 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
675 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
676 dma-names = "tx", "rx";
677 power-domains = <&rpmhpd SM8250_CX>;
678 operating-points-v2 = <&qup_opp_table>;
679 #address-cells = <1>;
684 uart17: serial@88c000 {
685 compatible = "qcom,geni-uart";
686 reg = <0 0x0088c000 0 0x4000>;
688 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
689 pinctrl-names = "default";
690 pinctrl-0 = <&qup_uart17_default>;
691 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
692 power-domains = <&rpmhpd SM8250_CX>;
693 operating-points-v2 = <&qup_opp_table>;
698 compatible = "qcom,geni-i2c";
699 reg = <0 0x00890000 0 0x4000>;
701 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
702 pinctrl-names = "default";
703 pinctrl-0 = <&qup_i2c18_default>;
704 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
705 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
706 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
707 dma-names = "tx", "rx";
708 #address-cells = <1>;
714 compatible = "qcom,geni-spi";
715 reg = <0 0x00890000 0 0x4000>;
717 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
718 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
719 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
720 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
721 dma-names = "tx", "rx";
722 power-domains = <&rpmhpd SM8250_CX>;
723 operating-points-v2 = <&qup_opp_table>;
724 #address-cells = <1>;
729 uart18: serial@890000 {
730 compatible = "qcom,geni-uart";
731 reg = <0 0x00890000 0 0x4000>;
733 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
734 pinctrl-names = "default";
735 pinctrl-0 = <&qup_uart18_default>;
736 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
737 power-domains = <&rpmhpd SM8250_CX>;
738 operating-points-v2 = <&qup_opp_table>;
743 compatible = "qcom,geni-i2c";
744 reg = <0 0x00894000 0 0x4000>;
746 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
747 pinctrl-names = "default";
748 pinctrl-0 = <&qup_i2c19_default>;
749 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
750 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
751 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
752 dma-names = "tx", "rx";
753 #address-cells = <1>;
759 compatible = "qcom,geni-spi";
760 reg = <0 0x00894000 0 0x4000>;
762 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
763 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
764 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
765 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
766 dma-names = "tx", "rx";
767 power-domains = <&rpmhpd SM8250_CX>;
768 operating-points-v2 = <&qup_opp_table>;
769 #address-cells = <1>;
775 gpi_dma0: dma-controller@900000 {
776 compatible = "qcom,sm8250-gpi-dma";
777 reg = <0 0x00900000 0 0x70000>;
778 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
790 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
792 dma-channel-mask = <0x7ff>;
793 iommus = <&apps_smmu 0x5b6 0x0>;
798 qupv3_id_0: geniqup@9c0000 {
799 compatible = "qcom,geni-se-qup";
800 reg = <0x0 0x009c0000 0x0 0x6000>;
801 clock-names = "m-ahb", "s-ahb";
802 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
803 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
804 #address-cells = <2>;
806 iommus = <&apps_smmu 0x5a3 0x0>;
811 compatible = "qcom,geni-i2c";
812 reg = <0 0x00980000 0 0x4000>;
814 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
815 pinctrl-names = "default";
816 pinctrl-0 = <&qup_i2c0_default>;
817 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
818 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
819 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
820 dma-names = "tx", "rx";
821 #address-cells = <1>;
827 compatible = "qcom,geni-spi";
828 reg = <0 0x00980000 0 0x4000>;
830 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
831 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
832 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
833 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
834 dma-names = "tx", "rx";
835 power-domains = <&rpmhpd SM8250_CX>;
836 operating-points-v2 = <&qup_opp_table>;
837 #address-cells = <1>;
843 compatible = "qcom,geni-i2c";
844 reg = <0 0x00984000 0 0x4000>;
846 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
847 pinctrl-names = "default";
848 pinctrl-0 = <&qup_i2c1_default>;
849 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
850 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
851 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
852 dma-names = "tx", "rx";
853 #address-cells = <1>;
859 compatible = "qcom,geni-spi";
860 reg = <0 0x00984000 0 0x4000>;
862 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
863 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
864 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
865 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
866 dma-names = "tx", "rx";
867 power-domains = <&rpmhpd SM8250_CX>;
868 operating-points-v2 = <&qup_opp_table>;
869 #address-cells = <1>;
875 compatible = "qcom,geni-i2c";
876 reg = <0 0x00988000 0 0x4000>;
878 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
879 pinctrl-names = "default";
880 pinctrl-0 = <&qup_i2c2_default>;
881 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
882 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
883 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
884 dma-names = "tx", "rx";
885 #address-cells = <1>;
891 compatible = "qcom,geni-spi";
892 reg = <0 0x00988000 0 0x4000>;
894 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
895 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
896 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
897 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
898 dma-names = "tx", "rx";
899 power-domains = <&rpmhpd SM8250_CX>;
900 operating-points-v2 = <&qup_opp_table>;
901 #address-cells = <1>;
906 uart2: serial@988000 {
907 compatible = "qcom,geni-debug-uart";
908 reg = <0 0x00988000 0 0x4000>;
910 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
911 pinctrl-names = "default";
912 pinctrl-0 = <&qup_uart2_default>;
913 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
914 power-domains = <&rpmhpd SM8250_CX>;
915 operating-points-v2 = <&qup_opp_table>;
920 compatible = "qcom,geni-i2c";
921 reg = <0 0x0098c000 0 0x4000>;
923 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
924 pinctrl-names = "default";
925 pinctrl-0 = <&qup_i2c3_default>;
926 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
927 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
928 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
929 dma-names = "tx", "rx";
930 #address-cells = <1>;
936 compatible = "qcom,geni-spi";
937 reg = <0 0x0098c000 0 0x4000>;
939 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
940 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
941 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
942 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
943 dma-names = "tx", "rx";
944 power-domains = <&rpmhpd SM8250_CX>;
945 operating-points-v2 = <&qup_opp_table>;
946 #address-cells = <1>;
952 compatible = "qcom,geni-i2c";
953 reg = <0 0x00990000 0 0x4000>;
955 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
956 pinctrl-names = "default";
957 pinctrl-0 = <&qup_i2c4_default>;
958 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
959 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
960 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
961 dma-names = "tx", "rx";
962 #address-cells = <1>;
968 compatible = "qcom,geni-spi";
969 reg = <0 0x00990000 0 0x4000>;
971 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
972 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
973 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
974 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
975 dma-names = "tx", "rx";
976 power-domains = <&rpmhpd SM8250_CX>;
977 operating-points-v2 = <&qup_opp_table>;
978 #address-cells = <1>;
984 compatible = "qcom,geni-i2c";
985 reg = <0 0x00994000 0 0x4000>;
987 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
988 pinctrl-names = "default";
989 pinctrl-0 = <&qup_i2c5_default>;
990 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
991 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
992 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
993 dma-names = "tx", "rx";
994 #address-cells = <1>;
1000 compatible = "qcom,geni-spi";
1001 reg = <0 0x00994000 0 0x4000>;
1003 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1004 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1005 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1006 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1007 dma-names = "tx", "rx";
1008 power-domains = <&rpmhpd SM8250_CX>;
1009 operating-points-v2 = <&qup_opp_table>;
1010 #address-cells = <1>;
1012 status = "disabled";
1016 compatible = "qcom,geni-i2c";
1017 reg = <0 0x00998000 0 0x4000>;
1019 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1020 pinctrl-names = "default";
1021 pinctrl-0 = <&qup_i2c6_default>;
1022 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1023 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1024 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1025 dma-names = "tx", "rx";
1026 #address-cells = <1>;
1028 status = "disabled";
1032 compatible = "qcom,geni-spi";
1033 reg = <0 0x00998000 0 0x4000>;
1035 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1036 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1037 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1038 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1039 dma-names = "tx", "rx";
1040 power-domains = <&rpmhpd SM8250_CX>;
1041 operating-points-v2 = <&qup_opp_table>;
1042 #address-cells = <1>;
1044 status = "disabled";
1047 uart6: serial@998000 {
1048 compatible = "qcom,geni-uart";
1049 reg = <0 0x00998000 0 0x4000>;
1051 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1052 pinctrl-names = "default";
1053 pinctrl-0 = <&qup_uart6_default>;
1054 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1055 power-domains = <&rpmhpd SM8250_CX>;
1056 operating-points-v2 = <&qup_opp_table>;
1057 status = "disabled";
1061 compatible = "qcom,geni-i2c";
1062 reg = <0 0x0099c000 0 0x4000>;
1064 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1065 pinctrl-names = "default";
1066 pinctrl-0 = <&qup_i2c7_default>;
1067 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1068 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1069 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1070 dma-names = "tx", "rx";
1071 #address-cells = <1>;
1073 status = "disabled";
1077 compatible = "qcom,geni-spi";
1078 reg = <0 0x0099c000 0 0x4000>;
1080 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1081 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1082 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1083 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1084 dma-names = "tx", "rx";
1085 power-domains = <&rpmhpd SM8250_CX>;
1086 operating-points-v2 = <&qup_opp_table>;
1087 #address-cells = <1>;
1089 status = "disabled";
1093 gpi_dma1: dma-controller@a00000 {
1094 compatible = "qcom,sm8250-gpi-dma";
1095 reg = <0 0x00a00000 0 0x70000>;
1096 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1097 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1098 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1099 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1100 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1101 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1102 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1103 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1104 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1105 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1106 dma-channels = <10>;
1107 dma-channel-mask = <0x3f>;
1108 iommus = <&apps_smmu 0x56 0x0>;
1110 status = "disabled";
1113 qupv3_id_1: geniqup@ac0000 {
1114 compatible = "qcom,geni-se-qup";
1115 reg = <0x0 0x00ac0000 0x0 0x6000>;
1116 clock-names = "m-ahb", "s-ahb";
1117 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1118 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1119 #address-cells = <2>;
1121 iommus = <&apps_smmu 0x43 0x0>;
1123 status = "disabled";
1126 compatible = "qcom,geni-i2c";
1127 reg = <0 0x00a80000 0 0x4000>;
1129 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1130 pinctrl-names = "default";
1131 pinctrl-0 = <&qup_i2c8_default>;
1132 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1133 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1134 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1135 dma-names = "tx", "rx";
1136 #address-cells = <1>;
1138 status = "disabled";
1142 compatible = "qcom,geni-spi";
1143 reg = <0 0x00a80000 0 0x4000>;
1145 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1146 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1147 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1148 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1149 dma-names = "tx", "rx";
1150 power-domains = <&rpmhpd SM8250_CX>;
1151 operating-points-v2 = <&qup_opp_table>;
1152 #address-cells = <1>;
1154 status = "disabled";
1158 compatible = "qcom,geni-i2c";
1159 reg = <0 0x00a84000 0 0x4000>;
1161 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1162 pinctrl-names = "default";
1163 pinctrl-0 = <&qup_i2c9_default>;
1164 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1165 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1166 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1167 dma-names = "tx", "rx";
1168 #address-cells = <1>;
1170 status = "disabled";
1174 compatible = "qcom,geni-spi";
1175 reg = <0 0x00a84000 0 0x4000>;
1177 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1178 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1179 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1180 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1181 dma-names = "tx", "rx";
1182 power-domains = <&rpmhpd SM8250_CX>;
1183 operating-points-v2 = <&qup_opp_table>;
1184 #address-cells = <1>;
1186 status = "disabled";
1190 compatible = "qcom,geni-i2c";
1191 reg = <0 0x00a88000 0 0x4000>;
1193 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1194 pinctrl-names = "default";
1195 pinctrl-0 = <&qup_i2c10_default>;
1196 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1197 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1198 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1199 dma-names = "tx", "rx";
1200 #address-cells = <1>;
1202 status = "disabled";
1206 compatible = "qcom,geni-spi";
1207 reg = <0 0x00a88000 0 0x4000>;
1209 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1210 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1211 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1212 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1213 dma-names = "tx", "rx";
1214 power-domains = <&rpmhpd SM8250_CX>;
1215 operating-points-v2 = <&qup_opp_table>;
1216 #address-cells = <1>;
1218 status = "disabled";
1222 compatible = "qcom,geni-i2c";
1223 reg = <0 0x00a8c000 0 0x4000>;
1225 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1226 pinctrl-names = "default";
1227 pinctrl-0 = <&qup_i2c11_default>;
1228 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1229 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1230 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1231 dma-names = "tx", "rx";
1232 #address-cells = <1>;
1234 status = "disabled";
1238 compatible = "qcom,geni-spi";
1239 reg = <0 0x00a8c000 0 0x4000>;
1241 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1242 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1243 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1244 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1245 dma-names = "tx", "rx";
1246 power-domains = <&rpmhpd SM8250_CX>;
1247 operating-points-v2 = <&qup_opp_table>;
1248 #address-cells = <1>;
1250 status = "disabled";
1254 compatible = "qcom,geni-i2c";
1255 reg = <0 0x00a90000 0 0x4000>;
1257 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1258 pinctrl-names = "default";
1259 pinctrl-0 = <&qup_i2c12_default>;
1260 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1261 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1262 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1263 dma-names = "tx", "rx";
1264 #address-cells = <1>;
1266 status = "disabled";
1270 compatible = "qcom,geni-spi";
1271 reg = <0 0x00a90000 0 0x4000>;
1273 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1274 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1275 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1276 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1277 dma-names = "tx", "rx";
1278 power-domains = <&rpmhpd SM8250_CX>;
1279 operating-points-v2 = <&qup_opp_table>;
1280 #address-cells = <1>;
1282 status = "disabled";
1285 uart12: serial@a90000 {
1286 compatible = "qcom,geni-debug-uart";
1287 reg = <0x0 0x00a90000 0x0 0x4000>;
1289 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1290 pinctrl-names = "default";
1291 pinctrl-0 = <&qup_uart12_default>;
1292 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1293 power-domains = <&rpmhpd SM8250_CX>;
1294 operating-points-v2 = <&qup_opp_table>;
1295 status = "disabled";
1299 compatible = "qcom,geni-i2c";
1300 reg = <0 0x00a94000 0 0x4000>;
1302 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1303 pinctrl-names = "default";
1304 pinctrl-0 = <&qup_i2c13_default>;
1305 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1306 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1307 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1308 dma-names = "tx", "rx";
1309 #address-cells = <1>;
1311 status = "disabled";
1315 compatible = "qcom,geni-spi";
1316 reg = <0 0x00a94000 0 0x4000>;
1318 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1319 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1320 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1321 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1322 dma-names = "tx", "rx";
1323 power-domains = <&rpmhpd SM8250_CX>;
1324 operating-points-v2 = <&qup_opp_table>;
1325 #address-cells = <1>;
1327 status = "disabled";
1331 config_noc: interconnect@1500000 {
1332 compatible = "qcom,sm8250-config-noc";
1333 reg = <0 0x01500000 0 0xa580>;
1334 #interconnect-cells = <1>;
1335 qcom,bcm-voters = <&apps_bcm_voter>;
1338 system_noc: interconnect@1620000 {
1339 compatible = "qcom,sm8250-system-noc";
1340 reg = <0 0x01620000 0 0x1c200>;
1341 #interconnect-cells = <1>;
1342 qcom,bcm-voters = <&apps_bcm_voter>;
1345 mc_virt: interconnect@163d000 {
1346 compatible = "qcom,sm8250-mc-virt";
1347 reg = <0 0x0163d000 0 0x1000>;
1348 #interconnect-cells = <1>;
1349 qcom,bcm-voters = <&apps_bcm_voter>;
1352 aggre1_noc: interconnect@16e0000 {
1353 compatible = "qcom,sm8250-aggre1-noc";
1354 reg = <0 0x016e0000 0 0x1f180>;
1355 #interconnect-cells = <1>;
1356 qcom,bcm-voters = <&apps_bcm_voter>;
1359 aggre2_noc: interconnect@1700000 {
1360 compatible = "qcom,sm8250-aggre2-noc";
1361 reg = <0 0x01700000 0 0x33000>;
1362 #interconnect-cells = <1>;
1363 qcom,bcm-voters = <&apps_bcm_voter>;
1366 compute_noc: interconnect@1733000 {
1367 compatible = "qcom,sm8250-compute-noc";
1368 reg = <0 0x01733000 0 0xa180>;
1369 #interconnect-cells = <1>;
1370 qcom,bcm-voters = <&apps_bcm_voter>;
1373 mmss_noc: interconnect@1740000 {
1374 compatible = "qcom,sm8250-mmss-noc";
1375 reg = <0 0x01740000 0 0x1f080>;
1376 #interconnect-cells = <1>;
1377 qcom,bcm-voters = <&apps_bcm_voter>;
1380 pcie0: pci@1c00000 {
1381 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1382 reg = <0 0x01c00000 0 0x3000>,
1383 <0 0x60000000 0 0xf1d>,
1384 <0 0x60000f20 0 0xa8>,
1385 <0 0x60001000 0 0x1000>,
1386 <0 0x60100000 0 0x100000>;
1387 reg-names = "parf", "dbi", "elbi", "atu", "config";
1388 device_type = "pci";
1389 linux,pci-domain = <0>;
1390 bus-range = <0x00 0xff>;
1393 #address-cells = <3>;
1396 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1397 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1399 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1400 interrupt-names = "msi";
1401 #interrupt-cells = <1>;
1402 interrupt-map-mask = <0 0 0 0x7>;
1403 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1404 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1405 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1406 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1408 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1409 <&gcc GCC_PCIE_0_AUX_CLK>,
1410 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1411 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1412 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1413 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1414 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1415 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1416 clock-names = "pipe",
1425 iommus = <&apps_smmu 0x1c00 0x7f>;
1426 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1427 <0x100 &apps_smmu 0x1c01 0x1>;
1429 resets = <&gcc GCC_PCIE_0_BCR>;
1430 reset-names = "pci";
1432 power-domains = <&gcc PCIE_0_GDSC>;
1434 phys = <&pcie0_lane>;
1435 phy-names = "pciephy";
1437 perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>;
1438 enable-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>;
1440 pinctrl-names = "default";
1441 pinctrl-0 = <&pcie0_default_state>;
1443 status = "disabled";
1446 pcie0_phy: phy@1c06000 {
1447 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
1448 reg = <0 0x01c06000 0 0x1c0>;
1449 #address-cells = <2>;
1452 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1453 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1454 <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
1455 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1456 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1458 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1459 reset-names = "phy";
1461 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1462 assigned-clock-rates = <100000000>;
1464 status = "disabled";
1466 pcie0_lane: lanes@1c06200 {
1467 reg = <0 0x1c06200 0 0x170>, /* tx */
1468 <0 0x1c06400 0 0x200>, /* rx */
1469 <0 0x1c06800 0 0x1f0>, /* pcs */
1470 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
1471 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1472 clock-names = "pipe0";
1475 clock-output-names = "pcie_0_pipe_clk";
1479 pcie1: pci@1c08000 {
1480 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1481 reg = <0 0x01c08000 0 0x3000>,
1482 <0 0x40000000 0 0xf1d>,
1483 <0 0x40000f20 0 0xa8>,
1484 <0 0x40001000 0 0x1000>,
1485 <0 0x40100000 0 0x100000>;
1486 reg-names = "parf", "dbi", "elbi", "atu", "config";
1487 device_type = "pci";
1488 linux,pci-domain = <1>;
1489 bus-range = <0x00 0xff>;
1492 #address-cells = <3>;
1495 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1496 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1498 interrupts = <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>;
1499 interrupt-names = "msi";
1500 #interrupt-cells = <1>;
1501 interrupt-map-mask = <0 0 0 0x7>;
1502 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1503 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1504 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1505 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1507 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1508 <&gcc GCC_PCIE_1_AUX_CLK>,
1509 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1510 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1511 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1512 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1513 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1514 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1515 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1516 clock-names = "pipe",
1526 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1527 assigned-clock-rates = <19200000>;
1529 iommus = <&apps_smmu 0x1c80 0x7f>;
1530 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1531 <0x100 &apps_smmu 0x1c81 0x1>;
1533 resets = <&gcc GCC_PCIE_1_BCR>;
1534 reset-names = "pci";
1536 power-domains = <&gcc PCIE_1_GDSC>;
1538 phys = <&pcie1_lane>;
1539 phy-names = "pciephy";
1541 perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>;
1542 enable-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>;
1544 pinctrl-names = "default";
1545 pinctrl-0 = <&pcie1_default_state>;
1547 status = "disabled";
1550 pcie1_phy: phy@1c0e000 {
1551 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
1552 reg = <0 0x01c0e000 0 0x1c0>;
1553 #address-cells = <2>;
1556 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1557 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1558 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1559 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1560 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1562 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1563 reset-names = "phy";
1565 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1566 assigned-clock-rates = <100000000>;
1568 status = "disabled";
1570 pcie1_lane: lanes@1c0e200 {
1571 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
1572 <0 0x1c0e400 0 0x200>, /* rx0 */
1573 <0 0x1c0ea00 0 0x1f0>, /* pcs */
1574 <0 0x1c0e600 0 0x170>, /* tx1 */
1575 <0 0x1c0e800 0 0x200>, /* rx1 */
1576 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
1577 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
1578 clock-names = "pipe0";
1581 clock-output-names = "pcie_1_pipe_clk";
1585 pcie2: pci@1c10000 {
1586 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1587 reg = <0 0x01c10000 0 0x3000>,
1588 <0 0x64000000 0 0xf1d>,
1589 <0 0x64000f20 0 0xa8>,
1590 <0 0x64001000 0 0x1000>,
1591 <0 0x64100000 0 0x100000>;
1592 reg-names = "parf", "dbi", "elbi", "atu", "config";
1593 device_type = "pci";
1594 linux,pci-domain = <2>;
1595 bus-range = <0x00 0xff>;
1598 #address-cells = <3>;
1601 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>,
1602 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
1604 interrupts = <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
1605 interrupt-names = "msi";
1606 #interrupt-cells = <1>;
1607 interrupt-map-mask = <0 0 0 0x7>;
1608 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1609 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1610 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1611 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1613 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1614 <&gcc GCC_PCIE_2_AUX_CLK>,
1615 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1616 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1617 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
1618 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
1619 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
1620 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1621 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1622 clock-names = "pipe",
1632 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
1633 assigned-clock-rates = <19200000>;
1635 iommus = <&apps_smmu 0x1d00 0x7f>;
1636 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
1637 <0x100 &apps_smmu 0x1d01 0x1>;
1639 resets = <&gcc GCC_PCIE_2_BCR>;
1640 reset-names = "pci";
1642 power-domains = <&gcc PCIE_2_GDSC>;
1644 phys = <&pcie2_lane>;
1645 phy-names = "pciephy";
1647 perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>;
1648 enable-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>;
1650 pinctrl-names = "default";
1651 pinctrl-0 = <&pcie2_default_state>;
1653 status = "disabled";
1656 pcie2_phy: phy@1c16000 {
1657 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
1658 reg = <0 0x1c16000 0 0x1c0>;
1659 #address-cells = <2>;
1662 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1663 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1664 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
1665 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
1666 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1668 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
1669 reset-names = "phy";
1671 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
1672 assigned-clock-rates = <100000000>;
1674 status = "disabled";
1676 pcie2_lane: lanes@1c16200 {
1677 reg = <0 0x1c16200 0 0x170>, /* tx0 */
1678 <0 0x1c16400 0 0x200>, /* rx0 */
1679 <0 0x1c16a00 0 0x1f0>, /* pcs */
1680 <0 0x1c16600 0 0x170>, /* tx1 */
1681 <0 0x1c16800 0 0x200>, /* rx1 */
1682 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
1683 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
1684 clock-names = "pipe0";
1687 clock-output-names = "pcie_2_pipe_clk";
1691 ufs_mem_hc: ufshc@1d84000 {
1692 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
1694 reg = <0 0x01d84000 0 0x3000>;
1695 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1696 phys = <&ufs_mem_phy_lanes>;
1697 phy-names = "ufsphy";
1698 lanes-per-direction = <2>;
1700 resets = <&gcc GCC_UFS_PHY_BCR>;
1701 reset-names = "rst";
1703 power-domains = <&gcc UFS_PHY_GDSC>;
1705 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
1713 "tx_lane0_sync_clk",
1714 "rx_lane0_sync_clk",
1715 "rx_lane1_sync_clk";
1717 <&gcc GCC_UFS_PHY_AXI_CLK>,
1718 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1719 <&gcc GCC_UFS_PHY_AHB_CLK>,
1720 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1721 <&rpmhcc RPMH_CXO_CLK>,
1722 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1723 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1724 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1726 <37500000 300000000>,
1729 <37500000 300000000>,
1735 status = "disabled";
1738 ufs_mem_phy: phy@1d87000 {
1739 compatible = "qcom,sm8250-qmp-ufs-phy";
1740 reg = <0 0x01d87000 0 0x1c0>;
1741 #address-cells = <2>;
1744 clock-names = "ref",
1746 clocks = <&rpmhcc RPMH_CXO_CLK>,
1747 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1749 resets = <&ufs_mem_hc 0>;
1750 reset-names = "ufsphy";
1751 status = "disabled";
1753 ufs_mem_phy_lanes: lanes@1d87400 {
1754 reg = <0 0x01d87400 0 0x108>,
1755 <0 0x01d87600 0 0x1e0>,
1756 <0 0x01d87c00 0 0x1dc>,
1757 <0 0x01d87800 0 0x108>,
1758 <0 0x01d87a00 0 0x1e0>;
1763 ipa_virt: interconnect@1e00000 {
1764 compatible = "qcom,sm8250-ipa-virt";
1765 reg = <0 0x01e00000 0 0x1000>;
1766 #interconnect-cells = <1>;
1767 qcom,bcm-voters = <&apps_bcm_voter>;
1770 tcsr_mutex: hwlock@1f40000 {
1771 compatible = "qcom,tcsr-mutex";
1772 reg = <0x0 0x01f40000 0x0 0x40000>;
1773 #hwlock-cells = <1>;
1776 wsamacro: codec@3240000 {
1777 compatible = "qcom,sm8250-lpass-wsa-macro";
1778 reg = <0 0x03240000 0 0x1000>;
1779 clocks = <&audiocc 1>,
1781 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1782 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1786 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
1789 clock-frequency = <9600000>;
1790 clock-output-names = "mclk";
1791 #sound-dai-cells = <1>;
1793 pinctrl-names = "default";
1794 pinctrl-0 = <&wsa_swr_active>;
1797 swr0: soundwire-controller@3250000 {
1798 reg = <0 0x03250000 0 0x2000>;
1799 compatible = "qcom,soundwire-v1.5.1";
1800 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1801 clocks = <&wsamacro>;
1802 clock-names = "iface";
1804 qcom,din-ports = <2>;
1805 qcom,dout-ports = <6>;
1807 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
1808 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
1809 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
1810 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
1812 #sound-dai-cells = <1>;
1813 #address-cells = <2>;
1817 audiocc: clock-controller@3300000 {
1818 compatible = "qcom,sm8250-lpass-audiocc";
1819 reg = <0 0x03300000 0 0x30000>;
1821 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1822 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1823 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1824 clock-names = "core", "audio", "bus";
1827 vamacro: codec@3370000 {
1828 compatible = "qcom,sm8250-lpass-va-macro";
1829 reg = <0 0x03370000 0 0x1000>;
1830 clocks = <&aoncc 0>,
1831 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1832 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1834 clock-names = "mclk", "macro", "dcodec";
1837 clock-frequency = <9600000>;
1838 clock-output-names = "fsgen";
1839 #sound-dai-cells = <1>;
1842 aoncc: clock-controller@3380000 {
1843 compatible = "qcom,sm8250-lpass-aoncc";
1844 reg = <0 0x03380000 0 0x40000>;
1846 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1847 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1848 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1849 clock-names = "core", "audio", "bus";
1852 lpass_tlmm: pinctrl@33c0000{
1853 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
1854 reg = <0 0x033c0000 0x0 0x20000>,
1855 <0 0x03550000 0x0 0x10000>;
1858 gpio-ranges = <&lpass_tlmm 0 0 14>;
1860 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1861 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1862 clock-names = "core", "audio";
1864 wsa_swr_active: wsa-swr-active-pins {
1867 function = "wsa_swr_clk";
1868 drive-strength = <2>;
1875 function = "wsa_swr_data";
1876 drive-strength = <2>;
1883 wsa_swr_sleep: wsa-swr-sleep-pins {
1886 function = "wsa_swr_clk";
1887 drive-strength = <2>;
1894 function = "wsa_swr_data";
1895 drive-strength = <2>;
1902 dmic01_active: dmic01-active-pins {
1905 function = "dmic1_clk";
1906 drive-strength = <8>;
1911 function = "dmic1_data";
1912 drive-strength = <8>;
1917 dmic01_sleep: dmic01-sleep-pins {
1920 function = "dmic1_clk";
1921 drive-strength = <2>;
1928 function = "dmic1_data";
1929 drive-strength = <2>;
1937 compatible = "qcom,adreno-650.2",
1939 #stream-id-cells = <16>;
1941 reg = <0 0x03d00000 0 0x40000>;
1942 reg-names = "kgsl_3d0_reg_memory";
1944 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1946 iommus = <&adreno_smmu 0 0x401>;
1948 operating-points-v2 = <&gpu_opp_table>;
1952 status = "disabled";
1955 memory-region = <&gpu_mem>;
1958 /* note: downstream checks gpu binning for 670 Mhz */
1959 gpu_opp_table: opp-table {
1960 compatible = "operating-points-v2";
1963 opp-hz = /bits/ 64 <670000000>;
1964 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1968 opp-hz = /bits/ 64 <587000000>;
1969 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1973 opp-hz = /bits/ 64 <525000000>;
1974 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1978 opp-hz = /bits/ 64 <490000000>;
1979 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1983 opp-hz = /bits/ 64 <441600000>;
1984 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
1988 opp-hz = /bits/ 64 <400000000>;
1989 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1993 opp-hz = /bits/ 64 <305000000>;
1994 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2000 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2002 reg = <0 0x03d6a000 0 0x30000>,
2003 <0 0x3de0000 0 0x10000>,
2004 <0 0xb290000 0 0x10000>,
2005 <0 0xb490000 0 0x10000>;
2006 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2008 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2009 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2010 interrupt-names = "hfi", "gmu";
2012 clocks = <&gpucc GPU_CC_AHB_CLK>,
2013 <&gpucc GPU_CC_CX_GMU_CLK>,
2014 <&gpucc GPU_CC_CXO_CLK>,
2015 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2016 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2017 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2019 power-domains = <&gpucc GPU_CX_GDSC>,
2020 <&gpucc GPU_GX_GDSC>;
2021 power-domain-names = "cx", "gx";
2023 iommus = <&adreno_smmu 5 0x400>;
2025 operating-points-v2 = <&gmu_opp_table>;
2027 status = "disabled";
2029 gmu_opp_table: opp-table {
2030 compatible = "operating-points-v2";
2033 opp-hz = /bits/ 64 <200000000>;
2034 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2039 gpucc: clock-controller@3d90000 {
2040 compatible = "qcom,sm8250-gpucc";
2041 reg = <0 0x03d90000 0 0x9000>;
2042 clocks = <&rpmhcc RPMH_CXO_CLK>,
2043 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2044 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2045 clock-names = "bi_tcxo",
2046 "gcc_gpu_gpll0_clk_src",
2047 "gcc_gpu_gpll0_div_clk_src";
2050 #power-domain-cells = <1>;
2053 adreno_smmu: iommu@3da0000 {
2054 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
2055 reg = <0 0x03da0000 0 0x10000>;
2057 #global-interrupts = <2>;
2058 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
2059 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2060 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2061 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2062 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2063 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2064 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2065 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2066 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2067 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
2068 clocks = <&gpucc GPU_CC_AHB_CLK>,
2069 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2070 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2071 clock-names = "ahb", "bus", "iface";
2073 power-domains = <&gpucc GPU_CX_GDSC>;
2076 slpi: remoteproc@5c00000 {
2077 compatible = "qcom,sm8250-slpi-pas";
2078 reg = <0 0x05c00000 0 0x4000>;
2080 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
2081 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2082 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2083 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2084 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2085 interrupt-names = "wdog", "fatal", "ready",
2086 "handover", "stop-ack";
2088 clocks = <&rpmhcc RPMH_CXO_CLK>;
2091 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
2092 <&rpmhpd SM8250_LCX>,
2093 <&rpmhpd SM8250_LMX>;
2094 power-domain-names = "load_state", "lcx", "lmx";
2096 memory-region = <&slpi_mem>;
2098 qcom,smem-states = <&smp2p_slpi_out 0>;
2099 qcom,smem-state-names = "stop";
2101 status = "disabled";
2104 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2105 IPCC_MPROC_SIGNAL_GLINK_QMP
2106 IRQ_TYPE_EDGE_RISING>;
2107 mboxes = <&ipcc IPCC_CLIENT_SLPI
2108 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2111 qcom,remote-pid = <3>;
2114 compatible = "qcom,fastrpc";
2115 qcom,glink-channels = "fastrpcglink-apps-dsp";
2117 #address-cells = <1>;
2121 compatible = "qcom,fastrpc-compute-cb";
2123 iommus = <&apps_smmu 0x0541 0x0>;
2127 compatible = "qcom,fastrpc-compute-cb";
2129 iommus = <&apps_smmu 0x0542 0x0>;
2133 compatible = "qcom,fastrpc-compute-cb";
2135 iommus = <&apps_smmu 0x0543 0x0>;
2136 /* note: shared-cb = <4> in downstream */
2142 cdsp: remoteproc@8300000 {
2143 compatible = "qcom,sm8250-cdsp-pas";
2144 reg = <0 0x08300000 0 0x10000>;
2146 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
2147 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2148 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2149 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2150 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2151 interrupt-names = "wdog", "fatal", "ready",
2152 "handover", "stop-ack";
2154 clocks = <&rpmhcc RPMH_CXO_CLK>;
2157 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
2158 <&rpmhpd SM8250_CX>;
2159 power-domain-names = "load_state", "cx";
2161 memory-region = <&cdsp_mem>;
2163 qcom,smem-states = <&smp2p_cdsp_out 0>;
2164 qcom,smem-state-names = "stop";
2166 status = "disabled";
2169 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2170 IPCC_MPROC_SIGNAL_GLINK_QMP
2171 IRQ_TYPE_EDGE_RISING>;
2172 mboxes = <&ipcc IPCC_CLIENT_CDSP
2173 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2176 qcom,remote-pid = <5>;
2179 compatible = "qcom,fastrpc";
2180 qcom,glink-channels = "fastrpcglink-apps-dsp";
2182 #address-cells = <1>;
2186 compatible = "qcom,fastrpc-compute-cb";
2188 iommus = <&apps_smmu 0x1001 0x0460>;
2192 compatible = "qcom,fastrpc-compute-cb";
2194 iommus = <&apps_smmu 0x1002 0x0460>;
2198 compatible = "qcom,fastrpc-compute-cb";
2200 iommus = <&apps_smmu 0x1003 0x0460>;
2204 compatible = "qcom,fastrpc-compute-cb";
2206 iommus = <&apps_smmu 0x1004 0x0460>;
2210 compatible = "qcom,fastrpc-compute-cb";
2212 iommus = <&apps_smmu 0x1005 0x0460>;
2216 compatible = "qcom,fastrpc-compute-cb";
2218 iommus = <&apps_smmu 0x1006 0x0460>;
2222 compatible = "qcom,fastrpc-compute-cb";
2224 iommus = <&apps_smmu 0x1007 0x0460>;
2228 compatible = "qcom,fastrpc-compute-cb";
2230 iommus = <&apps_smmu 0x1008 0x0460>;
2233 /* note: secure cb9 in downstream */
2241 usb_1_hsphy: phy@88e3000 {
2242 compatible = "qcom,sm8250-usb-hs-phy",
2243 "qcom,usb-snps-hs-7nm-phy";
2244 reg = <0 0x088e3000 0 0x400>;
2245 status = "disabled";
2248 clocks = <&rpmhcc RPMH_CXO_CLK>;
2249 clock-names = "ref";
2251 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2254 usb_2_hsphy: phy@88e4000 {
2255 compatible = "qcom,sm8250-usb-hs-phy",
2256 "qcom,usb-snps-hs-7nm-phy";
2257 reg = <0 0x088e4000 0 0x400>;
2258 status = "disabled";
2261 clocks = <&rpmhcc RPMH_CXO_CLK>;
2262 clock-names = "ref";
2264 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2267 usb_1_qmpphy: phy@88e9000 {
2268 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
2269 reg = <0 0x088e9000 0 0x200>,
2270 <0 0x088e8000 0 0x40>,
2271 <0 0x088ea000 0 0x200>;
2272 status = "disabled";
2273 #address-cells = <2>;
2277 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2278 <&rpmhcc RPMH_CXO_CLK>,
2279 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2280 clock-names = "aux", "ref_clk_src", "com_aux";
2282 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2283 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2284 reset-names = "phy", "common";
2286 usb_1_ssphy: usb3-phy@88e9200 {
2287 reg = <0 0x088e9200 0 0x200>,
2288 <0 0x088e9400 0 0x200>,
2289 <0 0x088e9c00 0 0x400>,
2290 <0 0x088e9600 0 0x200>,
2291 <0 0x088e9800 0 0x200>,
2292 <0 0x088e9a00 0 0x100>;
2295 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2296 clock-names = "pipe0";
2297 clock-output-names = "usb3_phy_pipe_clk_src";
2300 dp_phy: dp-phy@88ea200 {
2301 reg = <0 0x088ea200 0 0x200>,
2302 <0 0x088ea400 0 0x200>,
2303 <0 0x088eac00 0 0x400>,
2304 <0 0x088ea600 0 0x200>,
2305 <0 0x088ea800 0 0x200>,
2306 <0 0x088eaa00 0 0x100>;
2309 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2310 clock-names = "pipe0";
2311 clock-output-names = "usb3_phy_pipe_clk_src";
2315 usb_2_qmpphy: phy@88eb000 {
2316 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
2317 reg = <0 0x088eb000 0 0x200>;
2318 status = "disabled";
2319 #address-cells = <2>;
2323 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2324 <&rpmhcc RPMH_CXO_CLK>,
2325 <&gcc GCC_USB3_SEC_CLKREF_EN>,
2326 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2327 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2329 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2330 <&gcc GCC_USB3_PHY_SEC_BCR>;
2331 reset-names = "phy", "common";
2333 usb_2_ssphy: lanes@88eb200 {
2334 reg = <0 0x088eb200 0 0x200>,
2335 <0 0x088eb400 0 0x200>,
2336 <0 0x088eb800 0 0x800>;
2339 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2340 clock-names = "pipe0";
2341 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2345 sdhc_2: sdhci@8804000 {
2346 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
2347 reg = <0 0x08804000 0 0x1000>;
2349 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2350 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2351 interrupt-names = "hc_irq", "pwr_irq";
2353 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2354 <&gcc GCC_SDCC2_APPS_CLK>,
2355 <&rpmhcc RPMH_CXO_CLK>;
2356 clock-names = "iface", "core", "xo";
2357 iommus = <&apps_smmu 0x4a0 0x0>;
2358 qcom,dll-config = <0x0007642c>;
2359 qcom,ddr-config = <0x80040868>;
2360 power-domains = <&rpmhpd SM8250_CX>;
2361 operating-points-v2 = <&sdhc2_opp_table>;
2363 status = "disabled";
2365 sdhc2_opp_table: sdhc2-opp-table {
2366 compatible = "operating-points-v2";
2369 opp-hz = /bits/ 64 <19200000>;
2370 required-opps = <&rpmhpd_opp_min_svs>;
2374 opp-hz = /bits/ 64 <50000000>;
2375 required-opps = <&rpmhpd_opp_low_svs>;
2379 opp-hz = /bits/ 64 <100000000>;
2380 required-opps = <&rpmhpd_opp_svs>;
2384 opp-hz = /bits/ 64 <202000000>;
2385 required-opps = <&rpmhpd_opp_svs_l1>;
2390 dc_noc: interconnect@90c0000 {
2391 compatible = "qcom,sm8250-dc-noc";
2392 reg = <0 0x090c0000 0 0x4200>;
2393 #interconnect-cells = <1>;
2394 qcom,bcm-voters = <&apps_bcm_voter>;
2397 gem_noc: interconnect@9100000 {
2398 compatible = "qcom,sm8250-gem-noc";
2399 reg = <0 0x09100000 0 0xb4000>;
2400 #interconnect-cells = <1>;
2401 qcom,bcm-voters = <&apps_bcm_voter>;
2404 npu_noc: interconnect@9990000 {
2405 compatible = "qcom,sm8250-npu-noc";
2406 reg = <0 0x09990000 0 0x1600>;
2407 #interconnect-cells = <1>;
2408 qcom,bcm-voters = <&apps_bcm_voter>;
2411 usb_1: usb@a6f8800 {
2412 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
2413 reg = <0 0x0a6f8800 0 0x400>;
2414 status = "disabled";
2415 #address-cells = <2>;
2420 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2421 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2422 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2423 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2424 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2425 <&gcc GCC_USB3_SEC_CLKREF_EN>;
2426 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2429 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2430 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2431 assigned-clock-rates = <19200000>, <200000000>;
2433 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2434 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
2435 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2436 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
2437 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
2438 "dm_hs_phy_irq", "ss_phy_irq";
2440 power-domains = <&gcc USB30_PRIM_GDSC>;
2442 resets = <&gcc GCC_USB30_PRIM_BCR>;
2444 usb_1_dwc3: usb@a600000 {
2445 compatible = "snps,dwc3";
2446 reg = <0 0x0a600000 0 0xcd00>;
2447 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2448 iommus = <&apps_smmu 0x0 0x0>;
2449 snps,dis_u2_susphy_quirk;
2450 snps,dis_enblslpm_quirk;
2451 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2452 phy-names = "usb2-phy", "usb3-phy";
2456 system-cache-controller@9200000 {
2457 compatible = "qcom,sm8250-llcc";
2458 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
2459 reg-names = "llcc_base", "llcc_broadcast_base";
2462 usb_2: usb@a8f8800 {
2463 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
2464 reg = <0 0x0a8f8800 0 0x400>;
2465 status = "disabled";
2466 #address-cells = <2>;
2471 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2472 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2473 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2474 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2475 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2476 <&gcc GCC_USB3_SEC_CLKREF_EN>;
2477 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2480 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2481 <&gcc GCC_USB30_SEC_MASTER_CLK>;
2482 assigned-clock-rates = <19200000>, <200000000>;
2484 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2485 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
2486 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
2487 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
2488 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
2489 "dm_hs_phy_irq", "ss_phy_irq";
2491 power-domains = <&gcc USB30_SEC_GDSC>;
2493 resets = <&gcc GCC_USB30_SEC_BCR>;
2495 usb_2_dwc3: usb@a800000 {
2496 compatible = "snps,dwc3";
2497 reg = <0 0x0a800000 0 0xcd00>;
2498 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2499 iommus = <&apps_smmu 0x20 0>;
2500 snps,dis_u2_susphy_quirk;
2501 snps,dis_enblslpm_quirk;
2502 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
2503 phy-names = "usb2-phy", "usb3-phy";
2507 venus: video-codec@aa00000 {
2508 compatible = "qcom,sm8250-venus";
2509 reg = <0 0x0aa00000 0 0x100000>;
2510 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
2511 power-domains = <&videocc MVS0C_GDSC>,
2512 <&videocc MVS0_GDSC>,
2513 <&rpmhpd SM8250_MX>;
2514 power-domain-names = "venus", "vcodec0", "mx";
2515 operating-points-v2 = <&venus_opp_table>;
2517 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
2518 <&videocc VIDEO_CC_MVS0C_CLK>,
2519 <&videocc VIDEO_CC_MVS0_CLK>;
2520 clock-names = "iface", "core", "vcodec0_core";
2522 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>,
2523 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>;
2524 interconnect-names = "cpu-cfg", "video-mem";
2526 iommus = <&apps_smmu 0x2100 0x0400>;
2527 memory-region = <&video_mem>;
2529 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
2530 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
2531 reset-names = "bus", "core";
2533 status = "disabled";
2536 compatible = "venus-decoder";
2540 compatible = "venus-encoder";
2543 venus_opp_table: venus-opp-table {
2544 compatible = "operating-points-v2";
2547 opp-hz = /bits/ 64 <720000000>;
2548 required-opps = <&rpmhpd_opp_low_svs>;
2552 opp-hz = /bits/ 64 <1014000000>;
2553 required-opps = <&rpmhpd_opp_svs>;
2557 opp-hz = /bits/ 64 <1098000000>;
2558 required-opps = <&rpmhpd_opp_svs_l1>;
2562 opp-hz = /bits/ 64 <1332000000>;
2563 required-opps = <&rpmhpd_opp_nom>;
2568 videocc: clock-controller@abf0000 {
2569 compatible = "qcom,sm8250-videocc";
2570 reg = <0 0x0abf0000 0 0x10000>;
2571 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
2572 <&rpmhcc RPMH_CXO_CLK>,
2573 <&rpmhcc RPMH_CXO_CLK_A>;
2574 mmcx-supply = <&mmcx_reg>;
2575 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
2578 #power-domain-cells = <1>;
2581 mdss: mdss@ae00000 {
2582 compatible = "qcom,sm8250-mdss";
2583 reg = <0 0x0ae00000 0 0x1000>;
2586 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
2587 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
2588 interconnect-names = "mdp0-mem", "mdp1-mem";
2590 power-domains = <&dispcc MDSS_GDSC>;
2592 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2593 <&gcc GCC_DISP_HF_AXI_CLK>,
2594 <&gcc GCC_DISP_SF_AXI_CLK>,
2595 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2596 clock-names = "iface", "bus", "nrt_bus", "core";
2598 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
2599 assigned-clock-rates = <460000000>;
2601 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2602 interrupt-controller;
2603 #interrupt-cells = <1>;
2605 iommus = <&apps_smmu 0x820 0x402>;
2607 status = "disabled";
2609 #address-cells = <2>;
2613 mdss_mdp: mdp@ae01000 {
2614 compatible = "qcom,sm8250-dpu";
2615 reg = <0 0x0ae01000 0 0x8f000>,
2616 <0 0x0aeb0000 0 0x2008>;
2617 reg-names = "mdp", "vbif";
2619 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2620 <&gcc GCC_DISP_HF_AXI_CLK>,
2621 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2622 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2623 clock-names = "iface", "bus", "core", "vsync";
2625 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2626 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2627 assigned-clock-rates = <460000000>,
2630 operating-points-v2 = <&mdp_opp_table>;
2631 power-domains = <&rpmhpd SM8250_MMCX>;
2633 interrupt-parent = <&mdss>;
2634 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
2637 #address-cells = <1>;
2642 dpu_intf1_out: endpoint {
2643 remote-endpoint = <&dsi0_in>;
2649 dpu_intf2_out: endpoint {
2650 remote-endpoint = <&dsi1_in>;
2655 mdp_opp_table: mdp-opp-table {
2656 compatible = "operating-points-v2";
2659 opp-hz = /bits/ 64 <200000000>;
2660 required-opps = <&rpmhpd_opp_low_svs>;
2664 opp-hz = /bits/ 64 <300000000>;
2665 required-opps = <&rpmhpd_opp_svs>;
2669 opp-hz = /bits/ 64 <345000000>;
2670 required-opps = <&rpmhpd_opp_svs_l1>;
2674 opp-hz = /bits/ 64 <460000000>;
2675 required-opps = <&rpmhpd_opp_nom>;
2681 compatible = "qcom,mdss-dsi-ctrl";
2682 reg = <0 0x0ae94000 0 0x400>;
2683 reg-names = "dsi_ctrl";
2685 interrupt-parent = <&mdss>;
2686 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
2688 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2689 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2690 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2691 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2692 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2693 <&gcc GCC_DISP_HF_AXI_CLK>;
2694 clock-names = "byte",
2701 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
2702 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
2704 operating-points-v2 = <&dsi_opp_table>;
2705 power-domains = <&rpmhpd SM8250_MMCX>;
2710 status = "disabled";
2712 #address-cells = <1>;
2716 #address-cells = <1>;
2722 remote-endpoint = <&dpu_intf1_out>;
2728 dsi0_out: endpoint {
2734 dsi0_phy: dsi-phy@ae94400 {
2735 compatible = "qcom,dsi-phy-7nm";
2736 reg = <0 0x0ae94400 0 0x200>,
2737 <0 0x0ae94600 0 0x280>,
2738 <0 0x0ae94900 0 0x260>;
2739 reg-names = "dsi_phy",
2746 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2747 <&rpmhcc RPMH_CXO_CLK>;
2748 clock-names = "iface", "ref";
2750 status = "disabled";
2754 compatible = "qcom,mdss-dsi-ctrl";
2755 reg = <0 0x0ae96000 0 0x400>;
2756 reg-names = "dsi_ctrl";
2758 interrupt-parent = <&mdss>;
2759 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
2761 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2762 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
2763 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
2764 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
2765 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2766 <&gcc GCC_DISP_HF_AXI_CLK>;
2767 clock-names = "byte",
2774 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
2775 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
2777 operating-points-v2 = <&dsi_opp_table>;
2778 power-domains = <&rpmhpd SM8250_MMCX>;
2783 status = "disabled";
2785 #address-cells = <1>;
2789 #address-cells = <1>;
2795 remote-endpoint = <&dpu_intf2_out>;
2801 dsi1_out: endpoint {
2807 dsi1_phy: dsi-phy@ae96400 {
2808 compatible = "qcom,dsi-phy-7nm";
2809 reg = <0 0x0ae96400 0 0x200>,
2810 <0 0x0ae96600 0 0x280>,
2811 <0 0x0ae96900 0 0x260>;
2812 reg-names = "dsi_phy",
2819 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2820 <&rpmhcc RPMH_CXO_CLK>;
2821 clock-names = "iface", "ref";
2823 status = "disabled";
2825 dsi_opp_table: dsi-opp-table {
2826 compatible = "operating-points-v2";
2829 opp-hz = /bits/ 64 <187500000>;
2830 required-opps = <&rpmhpd_opp_low_svs>;
2834 opp-hz = /bits/ 64 <300000000>;
2835 required-opps = <&rpmhpd_opp_svs>;
2839 opp-hz = /bits/ 64 <358000000>;
2840 required-opps = <&rpmhpd_opp_svs_l1>;
2846 dispcc: clock-controller@af00000 {
2847 compatible = "qcom,sm8250-dispcc";
2848 reg = <0 0x0af00000 0 0x10000>;
2849 mmcx-supply = <&mmcx_reg>;
2850 clocks = <&rpmhcc RPMH_CXO_CLK>,
2857 clock-names = "bi_tcxo",
2858 "dsi0_phy_pll_out_byteclk",
2859 "dsi0_phy_pll_out_dsiclk",
2860 "dsi1_phy_pll_out_byteclk",
2861 "dsi1_phy_pll_out_dsiclk",
2862 "dp_phy_pll_link_clk",
2863 "dp_phy_pll_vco_div_clk";
2866 #power-domain-cells = <1>;
2869 pdc: interrupt-controller@b220000 {
2870 compatible = "qcom,sm8250-pdc", "qcom,pdc";
2871 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
2872 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2873 <125 63 1>, <126 716 12>;
2874 #interrupt-cells = <2>;
2875 interrupt-parent = <&intc>;
2876 interrupt-controller;
2879 tsens0: thermal-sensor@c263000 {
2880 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
2881 reg = <0 0x0c263000 0 0x1ff>, /* TM */
2882 <0 0x0c222000 0 0x1ff>; /* SROT */
2883 #qcom,sensors = <16>;
2884 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
2885 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
2886 interrupt-names = "uplow", "critical";
2887 #thermal-sensor-cells = <1>;
2890 tsens1: thermal-sensor@c265000 {
2891 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
2892 reg = <0 0x0c265000 0 0x1ff>, /* TM */
2893 <0 0x0c223000 0 0x1ff>; /* SROT */
2894 #qcom,sensors = <9>;
2895 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
2896 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
2897 interrupt-names = "uplow", "critical";
2898 #thermal-sensor-cells = <1>;
2901 aoss_qmp: power-controller@c300000 {
2902 compatible = "qcom,sm8250-aoss-qmp";
2903 reg = <0 0x0c300000 0 0x100000>;
2904 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
2905 IPCC_MPROC_SIGNAL_GLINK_QMP
2906 IRQ_TYPE_EDGE_RISING>;
2907 mboxes = <&ipcc IPCC_CLIENT_AOP
2908 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2911 #power-domain-cells = <1>;
2914 spmi_bus: spmi@c440000 {
2915 compatible = "qcom,spmi-pmic-arb";
2916 reg = <0x0 0x0c440000 0x0 0x0001100>,
2917 <0x0 0x0c600000 0x0 0x2000000>,
2918 <0x0 0x0e600000 0x0 0x0100000>,
2919 <0x0 0x0e700000 0x0 0x00a0000>,
2920 <0x0 0x0c40a000 0x0 0x0026000>;
2921 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2922 interrupt-names = "periph_irq";
2923 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2926 #address-cells = <2>;
2928 interrupt-controller;
2929 #interrupt-cells = <4>;
2932 tlmm: pinctrl@f100000 {
2933 compatible = "qcom,sm8250-pinctrl";
2934 reg = <0 0x0f100000 0 0x300000>,
2935 <0 0x0f500000 0 0x300000>,
2936 <0 0x0f900000 0 0x300000>;
2937 reg-names = "west", "south", "north";
2938 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2941 interrupt-controller;
2942 #interrupt-cells = <2>;
2943 gpio-ranges = <&tlmm 0 0 181>;
2944 wakeup-parent = <&pdc>;
2946 pri_mi2s_active: pri-mi2s-active {
2949 function = "mi2s0_sck";
2950 drive-strength = <8>;
2956 function = "mi2s0_ws";
2957 drive-strength = <8>;
2963 function = "mi2s0_data0";
2964 drive-strength = <8>;
2971 function = "mi2s0_data1";
2972 drive-strength = <8>;
2977 qup_i2c0_default: qup-i2c0-default {
2979 pins = "gpio28", "gpio29";
2984 pins = "gpio28", "gpio29";
2985 drive-strength = <2>;
2990 qup_i2c1_default: qup-i2c1-default {
2992 pins = "gpio4", "gpio5";
2997 pins = "gpio4", "gpio5";
2998 drive-strength = <2>;
3003 qup_i2c2_default: qup-i2c2-default {
3005 pins = "gpio115", "gpio116";
3010 pins = "gpio115", "gpio116";
3011 drive-strength = <2>;
3016 qup_i2c3_default: qup-i2c3-default {
3018 pins = "gpio119", "gpio120";
3023 pins = "gpio119", "gpio120";
3024 drive-strength = <2>;
3029 qup_i2c4_default: qup-i2c4-default {
3031 pins = "gpio8", "gpio9";
3036 pins = "gpio8", "gpio9";
3037 drive-strength = <2>;
3042 qup_i2c5_default: qup-i2c5-default {
3044 pins = "gpio12", "gpio13";
3049 pins = "gpio12", "gpio13";
3050 drive-strength = <2>;
3055 qup_i2c6_default: qup-i2c6-default {
3057 pins = "gpio16", "gpio17";
3062 pins = "gpio16", "gpio17";
3063 drive-strength = <2>;
3068 qup_i2c7_default: qup-i2c7-default {
3070 pins = "gpio20", "gpio21";
3075 pins = "gpio20", "gpio21";
3076 drive-strength = <2>;
3081 qup_i2c8_default: qup-i2c8-default {
3083 pins = "gpio24", "gpio25";
3088 pins = "gpio24", "gpio25";
3089 drive-strength = <2>;
3094 qup_i2c9_default: qup-i2c9-default {
3096 pins = "gpio125", "gpio126";
3101 pins = "gpio125", "gpio126";
3102 drive-strength = <2>;
3107 qup_i2c10_default: qup-i2c10-default {
3109 pins = "gpio129", "gpio130";
3114 pins = "gpio129", "gpio130";
3115 drive-strength = <2>;
3120 qup_i2c11_default: qup-i2c11-default {
3122 pins = "gpio60", "gpio61";
3127 pins = "gpio60", "gpio61";
3128 drive-strength = <2>;
3133 qup_i2c12_default: qup-i2c12-default {
3135 pins = "gpio32", "gpio33";
3140 pins = "gpio32", "gpio33";
3141 drive-strength = <2>;
3146 qup_i2c13_default: qup-i2c13-default {
3148 pins = "gpio36", "gpio37";
3153 pins = "gpio36", "gpio37";
3154 drive-strength = <2>;
3159 qup_i2c14_default: qup-i2c14-default {
3161 pins = "gpio40", "gpio41";
3166 pins = "gpio40", "gpio41";
3167 drive-strength = <2>;
3172 qup_i2c15_default: qup-i2c15-default {
3174 pins = "gpio44", "gpio45";
3179 pins = "gpio44", "gpio45";
3180 drive-strength = <2>;
3185 qup_i2c16_default: qup-i2c16-default {
3187 pins = "gpio48", "gpio49";
3192 pins = "gpio48", "gpio49";
3193 drive-strength = <2>;
3198 qup_i2c17_default: qup-i2c17-default {
3200 pins = "gpio52", "gpio53";
3205 pins = "gpio52", "gpio53";
3206 drive-strength = <2>;
3211 qup_i2c18_default: qup-i2c18-default {
3213 pins = "gpio56", "gpio57";
3218 pins = "gpio56", "gpio57";
3219 drive-strength = <2>;
3224 qup_i2c19_default: qup-i2c19-default {
3226 pins = "gpio0", "gpio1";
3231 pins = "gpio0", "gpio1";
3232 drive-strength = <2>;
3237 qup_spi0_cs: qup-spi0-cs {
3242 qup_spi0_cs_gpio: qup-spi0-cs-gpio {
3247 qup_spi0_data_clk: qup-spi0-data-clk {
3248 pins = "gpio28", "gpio29",
3253 qup_spi1_cs: qup-spi1-cs {
3258 qup_spi1_cs_gpio: qup-spi1-cs-gpio {
3263 qup_spi1_data_clk: qup-spi1-data-clk {
3264 pins = "gpio4", "gpio5",
3269 qup_spi2_cs: qup-spi2-cs {
3274 qup_spi2_cs_gpio: qup-spi2-cs-gpio {
3279 qup_spi2_data_clk: qup-spi2-data-clk {
3280 pins = "gpio115", "gpio116",
3285 qup_spi3_cs: qup-spi3-cs {
3290 qup_spi3_cs_gpio: qup-spi3-cs-gpio {
3295 qup_spi3_data_clk: qup-spi3-data-clk {
3296 pins = "gpio119", "gpio120",
3301 qup_spi4_cs: qup-spi4-cs {
3306 qup_spi4_cs_gpio: qup-spi4-cs-gpio {
3311 qup_spi4_data_clk: qup-spi4-data-clk {
3312 pins = "gpio8", "gpio9",
3317 qup_spi5_cs: qup-spi5-cs {
3322 qup_spi5_cs_gpio: qup-spi5-cs-gpio {
3327 qup_spi5_data_clk: qup-spi5-data-clk {
3328 pins = "gpio12", "gpio13",
3333 qup_spi6_cs: qup-spi6-cs {
3338 qup_spi6_cs_gpio: qup-spi6-cs-gpio {
3343 qup_spi6_data_clk: qup-spi6-data-clk {
3344 pins = "gpio16", "gpio17",
3349 qup_spi7_cs: qup-spi7-cs {
3354 qup_spi7_cs_gpio: qup-spi7-cs-gpio {
3359 qup_spi7_data_clk: qup-spi7-data-clk {
3360 pins = "gpio20", "gpio21",
3365 qup_spi8_cs: qup-spi8-cs {
3370 qup_spi8_cs_gpio: qup-spi8-cs-gpio {
3375 qup_spi8_data_clk: qup-spi8-data-clk {
3376 pins = "gpio24", "gpio25",
3381 qup_spi9_cs: qup-spi9-cs {
3386 qup_spi9_cs_gpio: qup-spi9-cs-gpio {
3391 qup_spi9_data_clk: qup-spi9-data-clk {
3392 pins = "gpio125", "gpio126",
3397 qup_spi10_cs: qup-spi10-cs {
3402 qup_spi10_cs_gpio: qup-spi10-cs-gpio {
3407 qup_spi10_data_clk: qup-spi10-data-clk {
3408 pins = "gpio129", "gpio130",
3413 qup_spi11_cs: qup-spi11-cs {
3418 qup_spi11_cs_gpio: qup-spi11-cs-gpio {
3423 qup_spi11_data_clk: qup-spi11-data-clk {
3424 pins = "gpio60", "gpio61",
3429 qup_spi12_cs: qup-spi12-cs {
3434 qup_spi12_cs_gpio: qup-spi12-cs-gpio {
3439 qup_spi12_data_clk: qup-spi12-data-clk {
3440 pins = "gpio32", "gpio33",
3445 qup_spi13_cs: qup-spi13-cs {
3450 qup_spi13_cs_gpio: qup-spi13-cs-gpio {
3455 qup_spi13_data_clk: qup-spi13-data-clk {
3456 pins = "gpio36", "gpio37",
3461 qup_spi14_cs: qup-spi14-cs {
3466 qup_spi14_cs_gpio: qup-spi14-cs-gpio {
3471 qup_spi14_data_clk: qup-spi14-data-clk {
3472 pins = "gpio40", "gpio41",
3477 qup_spi15_cs: qup-spi15-cs {
3482 qup_spi15_cs_gpio: qup-spi15-cs-gpio {
3487 qup_spi15_data_clk: qup-spi15-data-clk {
3488 pins = "gpio44", "gpio45",
3493 qup_spi16_cs: qup-spi16-cs {
3498 qup_spi16_cs_gpio: qup-spi16-cs-gpio {
3503 qup_spi16_data_clk: qup-spi16-data-clk {
3504 pins = "gpio48", "gpio49",
3509 qup_spi17_cs: qup-spi17-cs {
3514 qup_spi17_cs_gpio: qup-spi17-cs-gpio {
3519 qup_spi17_data_clk: qup-spi17-data-clk {
3520 pins = "gpio52", "gpio53",
3525 qup_spi18_cs: qup-spi18-cs {
3530 qup_spi18_cs_gpio: qup-spi18-cs-gpio {
3535 qup_spi18_data_clk: qup-spi18-data-clk {
3536 pins = "gpio56", "gpio57",
3541 qup_spi19_cs: qup-spi19-cs {
3546 qup_spi19_cs_gpio: qup-spi19-cs-gpio {
3551 qup_spi19_data_clk: qup-spi19-data-clk {
3552 pins = "gpio0", "gpio1",
3557 qup_uart2_default: qup-uart2-default {
3559 pins = "gpio117", "gpio118";
3564 qup_uart6_default: qup-uart6-default {
3566 pins = "gpio16", "gpio17",
3572 qup_uart12_default: qup-uart12-default {
3574 pins = "gpio34", "gpio35";
3579 qup_uart17_default: qup-uart17-default {
3581 pins = "gpio52", "gpio53",
3587 qup_uart18_default: qup-uart18-default {
3589 pins = "gpio58", "gpio59";
3594 tert_mi2s_active: tert-mi2s-active {
3597 function = "mi2s2_sck";
3598 drive-strength = <8>;
3604 function = "mi2s2_data0";
3605 drive-strength = <8>;
3612 function = "mi2s2_ws";
3613 drive-strength = <8>;
3618 sdc2_sleep_state: sdc2-sleep {
3621 drive-strength = <2>;
3627 drive-strength = <2>;
3633 drive-strength = <2>;
3638 pcie0_default_state: pcie0-default {
3642 drive-strength = <2>;
3648 function = "pci_e0";
3649 drive-strength = <2>;
3656 drive-strength = <2>;
3661 pcie1_default_state: pcie1-default {
3665 drive-strength = <2>;
3671 function = "pci_e1";
3672 drive-strength = <2>;
3679 drive-strength = <2>;
3684 pcie2_default_state: pcie2-default {
3688 drive-strength = <2>;
3694 function = "pci_e2";
3695 drive-strength = <2>;
3702 drive-strength = <2>;
3708 apps_smmu: iommu@15000000 {
3709 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
3710 reg = <0 0x15000000 0 0x100000>;
3712 #global-interrupts = <2>;
3713 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
3714 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3715 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3716 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3717 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3718 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3719 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3720 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3721 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3722 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3723 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3724 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3725 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3726 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3727 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3728 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3729 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3730 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3731 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3732 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3733 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3734 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3735 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3736 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3737 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3738 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3739 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3740 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3741 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3742 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3743 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3744 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3745 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3746 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3747 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3748 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3749 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3750 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3751 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3752 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3753 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3754 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3755 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3756 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3757 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3758 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3759 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3760 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3761 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3762 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3763 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3764 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3765 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3766 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3767 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3768 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3769 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3770 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3771 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3772 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3773 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3774 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3775 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3776 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3777 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3778 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3779 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3780 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3781 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3782 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3783 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3784 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3785 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3786 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3787 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3788 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3789 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3790 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3791 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3792 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3793 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3794 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3795 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3796 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3797 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3798 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3799 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3800 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3801 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3802 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3803 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3804 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3805 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3806 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3807 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3808 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
3809 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
3810 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
3813 adsp: remoteproc@17300000 {
3814 compatible = "qcom,sm8250-adsp-pas";
3815 reg = <0 0x17300000 0 0x100>;
3817 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
3818 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3819 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3820 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
3821 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3822 interrupt-names = "wdog", "fatal", "ready",
3823 "handover", "stop-ack";
3825 clocks = <&rpmhcc RPMH_CXO_CLK>;
3828 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
3829 <&rpmhpd SM8250_LCX>,
3830 <&rpmhpd SM8250_LMX>;
3831 power-domain-names = "load_state", "lcx", "lmx";
3833 memory-region = <&adsp_mem>;
3835 qcom,smem-states = <&smp2p_adsp_out 0>;
3836 qcom,smem-state-names = "stop";
3838 status = "disabled";
3841 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3842 IPCC_MPROC_SIGNAL_GLINK_QMP
3843 IRQ_TYPE_EDGE_RISING>;
3844 mboxes = <&ipcc IPCC_CLIENT_LPASS
3845 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3848 qcom,remote-pid = <2>;
3851 compatible = "qcom,apr-v2";
3852 qcom,glink-channels = "apr_audio_svc";
3853 qcom,apr-domain = <APR_DOMAIN_ADSP>;
3854 #address-cells = <1>;
3858 reg = <APR_SVC_ADSP_CORE>;
3859 compatible = "qcom,q6core";
3860 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3863 q6afe: apr-service@4 {
3864 compatible = "qcom,q6afe";
3865 reg = <APR_SVC_AFE>;
3866 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3868 compatible = "qcom,q6afe-dais";
3869 #address-cells = <1>;
3871 #sound-dai-cells = <1>;
3875 compatible = "qcom,q6afe-clocks";
3880 q6asm: apr-service@7 {
3881 compatible = "qcom,q6asm";
3882 reg = <APR_SVC_ASM>;
3883 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3885 compatible = "qcom,q6asm-dais";
3886 #address-cells = <1>;
3888 #sound-dai-cells = <1>;
3889 iommus = <&apps_smmu 0x1801 0x0>;
3893 q6adm: apr-service@8 {
3894 compatible = "qcom,q6adm";
3895 reg = <APR_SVC_ADM>;
3896 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3897 q6routing: routing {
3898 compatible = "qcom,q6adm-routing";
3899 #sound-dai-cells = <0>;
3905 compatible = "qcom,fastrpc";
3906 qcom,glink-channels = "fastrpcglink-apps-dsp";
3908 #address-cells = <1>;
3912 compatible = "qcom,fastrpc-compute-cb";
3914 iommus = <&apps_smmu 0x1803 0x0>;
3918 compatible = "qcom,fastrpc-compute-cb";
3920 iommus = <&apps_smmu 0x1804 0x0>;
3924 compatible = "qcom,fastrpc-compute-cb";
3926 iommus = <&apps_smmu 0x1805 0x0>;
3932 intc: interrupt-controller@17a00000 {
3933 compatible = "arm,gic-v3";
3934 #interrupt-cells = <3>;
3935 interrupt-controller;
3936 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3937 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3938 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3942 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
3943 reg = <0 0x17c10000 0 0x1000>;
3944 clocks = <&sleep_clk>;
3945 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
3949 #address-cells = <2>;
3952 compatible = "arm,armv7-timer-mem";
3953 reg = <0x0 0x17c20000 0x0 0x1000>;
3954 clock-frequency = <19200000>;
3958 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3959 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3960 reg = <0x0 0x17c21000 0x0 0x1000>,
3961 <0x0 0x17c22000 0x0 0x1000>;
3966 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3967 reg = <0x0 0x17c23000 0x0 0x1000>;
3968 status = "disabled";
3973 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3974 reg = <0x0 0x17c25000 0x0 0x1000>;
3975 status = "disabled";
3980 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3981 reg = <0x0 0x17c27000 0x0 0x1000>;
3982 status = "disabled";
3987 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3988 reg = <0x0 0x17c29000 0x0 0x1000>;
3989 status = "disabled";
3994 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3995 reg = <0x0 0x17c2b000 0x0 0x1000>;
3996 status = "disabled";
4001 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4002 reg = <0x0 0x17c2d000 0x0 0x1000>;
4003 status = "disabled";
4007 apps_rsc: rsc@18200000 {
4009 compatible = "qcom,rpmh-rsc";
4010 reg = <0x0 0x18200000 0x0 0x10000>,
4011 <0x0 0x18210000 0x0 0x10000>,
4012 <0x0 0x18220000 0x0 0x10000>;
4013 reg-names = "drv-0", "drv-1", "drv-2";
4014 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4015 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4016 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4017 qcom,tcs-offset = <0xd00>;
4019 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
4020 <WAKE_TCS 3>, <CONTROL_TCS 1>;
4022 rpmhcc: clock-controller {
4023 compatible = "qcom,sm8250-rpmh-clk";
4026 clocks = <&xo_board>;
4029 rpmhpd: power-controller {
4030 compatible = "qcom,sm8250-rpmhpd";
4031 #power-domain-cells = <1>;
4032 operating-points-v2 = <&rpmhpd_opp_table>;
4034 rpmhpd_opp_table: opp-table {
4035 compatible = "operating-points-v2";
4037 rpmhpd_opp_ret: opp1 {
4038 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4041 rpmhpd_opp_min_svs: opp2 {
4042 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4045 rpmhpd_opp_low_svs: opp3 {
4046 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4049 rpmhpd_opp_svs: opp4 {
4050 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4053 rpmhpd_opp_svs_l1: opp5 {
4054 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4057 rpmhpd_opp_nom: opp6 {
4058 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4061 rpmhpd_opp_nom_l1: opp7 {
4062 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4065 rpmhpd_opp_nom_l2: opp8 {
4066 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4069 rpmhpd_opp_turbo: opp9 {
4070 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4073 rpmhpd_opp_turbo_l1: opp10 {
4074 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4079 apps_bcm_voter: bcm_voter {
4080 compatible = "qcom,bcm-voter";
4084 epss_l3: interconnect@18590000 {
4085 compatible = "qcom,sm8250-epss-l3";
4086 reg = <0 0x18590000 0 0x1000>;
4088 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4089 clock-names = "xo", "alternate";
4091 #interconnect-cells = <1>;
4094 cpufreq_hw: cpufreq@18591000 {
4095 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
4096 reg = <0 0x18591000 0 0x1000>,
4097 <0 0x18592000 0 0x1000>,
4098 <0 0x18593000 0 0x1000>;
4099 reg-names = "freq-domain0", "freq-domain1",
4102 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4103 clock-names = "xo", "alternate";
4105 #freq-domain-cells = <1>;
4110 compatible = "arm,armv8-timer";
4111 interrupts = <GIC_PPI 13
4112 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4114 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4116 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4118 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
4123 polling-delay-passive = <250>;
4124 polling-delay = <1000>;
4126 thermal-sensors = <&tsens0 1>;
4129 cpu0_alert0: trip-point0 {
4130 temperature = <90000>;
4131 hysteresis = <2000>;
4135 cpu0_alert1: trip-point1 {
4136 temperature = <95000>;
4137 hysteresis = <2000>;
4141 cpu0_crit: cpu_crit {
4142 temperature = <110000>;
4143 hysteresis = <1000>;
4150 trip = <&cpu0_alert0>;
4151 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4152 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4153 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4154 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4157 trip = <&cpu0_alert1>;
4158 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4159 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4160 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4161 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4167 polling-delay-passive = <250>;
4168 polling-delay = <1000>;
4170 thermal-sensors = <&tsens0 2>;
4173 cpu1_alert0: trip-point0 {
4174 temperature = <90000>;
4175 hysteresis = <2000>;
4179 cpu1_alert1: trip-point1 {
4180 temperature = <95000>;
4181 hysteresis = <2000>;
4185 cpu1_crit: cpu_crit {
4186 temperature = <110000>;
4187 hysteresis = <1000>;
4194 trip = <&cpu1_alert0>;
4195 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4196 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4197 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4198 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4201 trip = <&cpu1_alert1>;
4202 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4203 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4204 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4205 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4211 polling-delay-passive = <250>;
4212 polling-delay = <1000>;
4214 thermal-sensors = <&tsens0 3>;
4217 cpu2_alert0: trip-point0 {
4218 temperature = <90000>;
4219 hysteresis = <2000>;
4223 cpu2_alert1: trip-point1 {
4224 temperature = <95000>;
4225 hysteresis = <2000>;
4229 cpu2_crit: cpu_crit {
4230 temperature = <110000>;
4231 hysteresis = <1000>;
4238 trip = <&cpu2_alert0>;
4239 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4240 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4241 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4242 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4245 trip = <&cpu2_alert1>;
4246 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4247 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4248 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4249 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4255 polling-delay-passive = <250>;
4256 polling-delay = <1000>;
4258 thermal-sensors = <&tsens0 4>;
4261 cpu3_alert0: trip-point0 {
4262 temperature = <90000>;
4263 hysteresis = <2000>;
4267 cpu3_alert1: trip-point1 {
4268 temperature = <95000>;
4269 hysteresis = <2000>;
4273 cpu3_crit: cpu_crit {
4274 temperature = <110000>;
4275 hysteresis = <1000>;
4282 trip = <&cpu3_alert0>;
4283 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4284 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4285 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4286 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4289 trip = <&cpu3_alert1>;
4290 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4291 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4292 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4293 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4299 polling-delay-passive = <250>;
4300 polling-delay = <1000>;
4302 thermal-sensors = <&tsens0 7>;
4305 cpu4_top_alert0: trip-point0 {
4306 temperature = <90000>;
4307 hysteresis = <2000>;
4311 cpu4_top_alert1: trip-point1 {
4312 temperature = <95000>;
4313 hysteresis = <2000>;
4317 cpu4_top_crit: cpu_crit {
4318 temperature = <110000>;
4319 hysteresis = <1000>;
4326 trip = <&cpu4_top_alert0>;
4327 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4328 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4329 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4330 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4333 trip = <&cpu4_top_alert1>;
4334 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4335 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4336 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4337 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4343 polling-delay-passive = <250>;
4344 polling-delay = <1000>;
4346 thermal-sensors = <&tsens0 8>;
4349 cpu5_top_alert0: trip-point0 {
4350 temperature = <90000>;
4351 hysteresis = <2000>;
4355 cpu5_top_alert1: trip-point1 {
4356 temperature = <95000>;
4357 hysteresis = <2000>;
4361 cpu5_top_crit: cpu_crit {
4362 temperature = <110000>;
4363 hysteresis = <1000>;
4370 trip = <&cpu5_top_alert0>;
4371 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4372 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4373 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4374 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4377 trip = <&cpu5_top_alert1>;
4378 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4379 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4380 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4381 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4387 polling-delay-passive = <250>;
4388 polling-delay = <1000>;
4390 thermal-sensors = <&tsens0 9>;
4393 cpu6_top_alert0: trip-point0 {
4394 temperature = <90000>;
4395 hysteresis = <2000>;
4399 cpu6_top_alert1: trip-point1 {
4400 temperature = <95000>;
4401 hysteresis = <2000>;
4405 cpu6_top_crit: cpu_crit {
4406 temperature = <110000>;
4407 hysteresis = <1000>;
4414 trip = <&cpu6_top_alert0>;
4415 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4416 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4417 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4418 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4421 trip = <&cpu6_top_alert1>;
4422 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4423 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4424 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4425 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4431 polling-delay-passive = <250>;
4432 polling-delay = <1000>;
4434 thermal-sensors = <&tsens0 10>;
4437 cpu7_top_alert0: trip-point0 {
4438 temperature = <90000>;
4439 hysteresis = <2000>;
4443 cpu7_top_alert1: trip-point1 {
4444 temperature = <95000>;
4445 hysteresis = <2000>;
4449 cpu7_top_crit: cpu_crit {
4450 temperature = <110000>;
4451 hysteresis = <1000>;
4458 trip = <&cpu7_top_alert0>;
4459 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4460 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4461 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4462 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4465 trip = <&cpu7_top_alert1>;
4466 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4467 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4468 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4469 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4474 cpu4-bottom-thermal {
4475 polling-delay-passive = <250>;
4476 polling-delay = <1000>;
4478 thermal-sensors = <&tsens0 11>;
4481 cpu4_bottom_alert0: trip-point0 {
4482 temperature = <90000>;
4483 hysteresis = <2000>;
4487 cpu4_bottom_alert1: trip-point1 {
4488 temperature = <95000>;
4489 hysteresis = <2000>;
4493 cpu4_bottom_crit: cpu_crit {
4494 temperature = <110000>;
4495 hysteresis = <1000>;
4502 trip = <&cpu4_bottom_alert0>;
4503 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4504 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4505 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4506 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4509 trip = <&cpu4_bottom_alert1>;
4510 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4511 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4512 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4513 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4518 cpu5-bottom-thermal {
4519 polling-delay-passive = <250>;
4520 polling-delay = <1000>;
4522 thermal-sensors = <&tsens0 12>;
4525 cpu5_bottom_alert0: trip-point0 {
4526 temperature = <90000>;
4527 hysteresis = <2000>;
4531 cpu5_bottom_alert1: trip-point1 {
4532 temperature = <95000>;
4533 hysteresis = <2000>;
4537 cpu5_bottom_crit: cpu_crit {
4538 temperature = <110000>;
4539 hysteresis = <1000>;
4546 trip = <&cpu5_bottom_alert0>;
4547 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4548 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4549 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4550 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4553 trip = <&cpu5_bottom_alert1>;
4554 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4555 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4556 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4557 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4562 cpu6-bottom-thermal {
4563 polling-delay-passive = <250>;
4564 polling-delay = <1000>;
4566 thermal-sensors = <&tsens0 13>;
4569 cpu6_bottom_alert0: trip-point0 {
4570 temperature = <90000>;
4571 hysteresis = <2000>;
4575 cpu6_bottom_alert1: trip-point1 {
4576 temperature = <95000>;
4577 hysteresis = <2000>;
4581 cpu6_bottom_crit: cpu_crit {
4582 temperature = <110000>;
4583 hysteresis = <1000>;
4590 trip = <&cpu6_bottom_alert0>;
4591 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4592 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4593 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4594 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4597 trip = <&cpu6_bottom_alert1>;
4598 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4599 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4600 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4601 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4606 cpu7-bottom-thermal {
4607 polling-delay-passive = <250>;
4608 polling-delay = <1000>;
4610 thermal-sensors = <&tsens0 14>;
4613 cpu7_bottom_alert0: trip-point0 {
4614 temperature = <90000>;
4615 hysteresis = <2000>;
4619 cpu7_bottom_alert1: trip-point1 {
4620 temperature = <95000>;
4621 hysteresis = <2000>;
4625 cpu7_bottom_crit: cpu_crit {
4626 temperature = <110000>;
4627 hysteresis = <1000>;
4634 trip = <&cpu7_bottom_alert0>;
4635 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4636 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4637 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4638 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4641 trip = <&cpu7_bottom_alert1>;
4642 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4643 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4644 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4645 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4651 polling-delay-passive = <250>;
4652 polling-delay = <1000>;
4654 thermal-sensors = <&tsens0 0>;
4657 aoss0_alert0: trip-point0 {
4658 temperature = <90000>;
4659 hysteresis = <2000>;
4666 polling-delay-passive = <250>;
4667 polling-delay = <1000>;
4669 thermal-sensors = <&tsens0 5>;
4672 cluster0_alert0: trip-point0 {
4673 temperature = <90000>;
4674 hysteresis = <2000>;
4677 cluster0_crit: cluster0_crit {
4678 temperature = <110000>;
4679 hysteresis = <2000>;
4686 polling-delay-passive = <250>;
4687 polling-delay = <1000>;
4689 thermal-sensors = <&tsens0 6>;
4692 cluster1_alert0: trip-point0 {
4693 temperature = <90000>;
4694 hysteresis = <2000>;
4697 cluster1_crit: cluster1_crit {
4698 temperature = <110000>;
4699 hysteresis = <2000>;
4706 polling-delay-passive = <250>;
4707 polling-delay = <1000>;
4709 thermal-sensors = <&tsens0 15>;
4712 gpu1_alert0: trip-point0 {
4713 temperature = <90000>;
4714 hysteresis = <2000>;
4721 polling-delay-passive = <250>;
4722 polling-delay = <1000>;
4724 thermal-sensors = <&tsens1 0>;
4727 aoss1_alert0: trip-point0 {
4728 temperature = <90000>;
4729 hysteresis = <2000>;
4736 polling-delay-passive = <250>;
4737 polling-delay = <1000>;
4739 thermal-sensors = <&tsens1 1>;
4742 wlan_alert0: trip-point0 {
4743 temperature = <90000>;
4744 hysteresis = <2000>;
4751 polling-delay-passive = <250>;
4752 polling-delay = <1000>;
4754 thermal-sensors = <&tsens1 2>;
4757 video_alert0: trip-point0 {
4758 temperature = <90000>;
4759 hysteresis = <2000>;
4766 polling-delay-passive = <250>;
4767 polling-delay = <1000>;
4769 thermal-sensors = <&tsens1 3>;
4772 mem_alert0: trip-point0 {
4773 temperature = <90000>;
4774 hysteresis = <2000>;
4781 polling-delay-passive = <250>;
4782 polling-delay = <1000>;
4784 thermal-sensors = <&tsens1 4>;
4787 q6_hvx_alert0: trip-point0 {
4788 temperature = <90000>;
4789 hysteresis = <2000>;
4796 polling-delay-passive = <250>;
4797 polling-delay = <1000>;
4799 thermal-sensors = <&tsens1 5>;
4802 camera_alert0: trip-point0 {
4803 temperature = <90000>;
4804 hysteresis = <2000>;
4811 polling-delay-passive = <250>;
4812 polling-delay = <1000>;
4814 thermal-sensors = <&tsens1 6>;
4817 compute_alert0: trip-point0 {
4818 temperature = <90000>;
4819 hysteresis = <2000>;
4826 polling-delay-passive = <250>;
4827 polling-delay = <1000>;
4829 thermal-sensors = <&tsens1 7>;
4832 npu_alert0: trip-point0 {
4833 temperature = <90000>;
4834 hysteresis = <2000>;
4840 gpu-thermal-bottom {
4841 polling-delay-passive = <250>;
4842 polling-delay = <1000>;
4844 thermal-sensors = <&tsens1 8>;
4847 gpu2_alert0: trip-point0 {
4848 temperature = <90000>;
4849 hysteresis = <2000>;