src/arm64/qcom/sm8250.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
   8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
   9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
  10 #include <dt-bindings/clock/qcom,rpmh.h>
  11 #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
  12 #include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>
  13 #include <dt-bindings/dma/qcom-gpi.h>
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  16 #include <dt-bindings/interconnect/qcom,sm8250.h>
  17 #include <dt-bindings/mailbox/qcom-ipcc.h>
  18 #include <dt-bindings/power/qcom-rpmpd.h>
  19 #include <dt-bindings/soc/qcom,apr.h>
  20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  21 #include <dt-bindings/sound/qcom,q6afe.h>
  22 #include <dt-bindings/thermal/thermal.h>
  23 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
  24 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
  25
  26 / {
  27         interrupt-parent = <&intc>;
  28
  29         #address-cells = <2>;
  30         #size-cells = <2>;
  31
  32         aliases {
  33                 i2c0 = &i2c0;
  34                 i2c1 = &i2c1;
  35                 i2c2 = &i2c2;
  36                 i2c3 = &i2c3;
  37                 i2c4 = &i2c4;
  38                 i2c5 = &i2c5;
  39                 i2c6 = &i2c6;
  40                 i2c7 = &i2c7;
  41                 i2c8 = &i2c8;
  42                 i2c9 = &i2c9;
  43                 i2c10 = &i2c10;
  44                 i2c11 = &i2c11;
  45                 i2c12 = &i2c12;
  46                 i2c13 = &i2c13;
  47                 i2c14 = &i2c14;
  48                 i2c15 = &i2c15;
  49                 i2c16 = &i2c16;
  50                 i2c17 = &i2c17;
  51                 i2c18 = &i2c18;
  52                 i2c19 = &i2c19;
  53                 spi0 = &spi0;
  54                 spi1 = &spi1;
  55                 spi2 = &spi2;
  56                 spi3 = &spi3;
  57                 spi4 = &spi4;
  58                 spi5 = &spi5;
  59                 spi6 = &spi6;
  60                 spi7 = &spi7;
  61                 spi8 = &spi8;
  62                 spi9 = &spi9;
  63                 spi10 = &spi10;
  64                 spi11 = &spi11;
  65                 spi12 = &spi12;
  66                 spi13 = &spi13;
  67                 spi14 = &spi14;
  68                 spi15 = &spi15;
  69                 spi16 = &spi16;
  70                 spi17 = &spi17;
  71                 spi18 = &spi18;
  72                 spi19 = &spi19;
  73         };
  74
  75         chosen { };
  76
  77         clocks {
  78                 xo_board: xo-board {
  79                         compatible = "fixed-clock";
  80                         #clock-cells = <0>;
  81                         clock-frequency = <38400000>;
  82                         clock-output-names = "xo_board";
  83                 };
  84
  85                 sleep_clk: sleep-clk {
  86                         compatible = "fixed-clock";
  87                         clock-frequency = <32768>;
  88                         #clock-cells = <0>;
  89                 };
  90         };
  91
  92         cpus {
  93                 #address-cells = <2>;
  94                 #size-cells = <0>;
  95
  96                 CPU0: cpu@0 {
  97                         device_type = "cpu";
  98                         compatible = "qcom,kryo485";
  99                         reg = <0x0 0x0>;
 100                         enable-method = "psci";
 101                         capacity-dmips-mhz = <448>;
 102                         dynamic-power-coefficient = <205>;
 103                         next-level-cache = <&L2_0>;
 104                         power-domains = <&CPU_PD0>;
 105                         power-domain-names = "psci";
 106                         qcom,freq-domain = <&cpufreq_hw 0>;
 107                         operating-points-v2 = <&cpu0_opp_table>;
 108                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 109                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 110                         #cooling-cells = <2>;
 111                         L2_0: l2-cache {
 112                                 compatible = "cache";
 113                                 next-level-cache = <&L3_0>;
 114                                 L3_0: l3-cache {
 115                                         compatible = "cache";
 116                                 };
 117                         };
 118                 };
 119
 120                 CPU1: cpu@100 {
 121                         device_type = "cpu";
 122                         compatible = "qcom,kryo485";
 123                         reg = <0x0 0x100>;
 124                         enable-method = "psci";
 125                         capacity-dmips-mhz = <448>;
 126                         dynamic-power-coefficient = <205>;
 127                         next-level-cache = <&L2_100>;
 128                         power-domains = <&CPU_PD1>;
 129                         power-domain-names = "psci";
 130                         qcom,freq-domain = <&cpufreq_hw 0>;
 131                         operating-points-v2 = <&cpu0_opp_table>;
 132                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 133                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 134                         #cooling-cells = <2>;
 135                         L2_100: l2-cache {
 136                                 compatible = "cache";
 137                                 next-level-cache = <&L3_0>;
 138                         };
 139                 };
 140
 141                 CPU2: cpu@200 {
 142                         device_type = "cpu";
 143                         compatible = "qcom,kryo485";
 144                         reg = <0x0 0x200>;
 145                         enable-method = "psci";
 146                         capacity-dmips-mhz = <448>;
 147                         dynamic-power-coefficient = <205>;
 148                         next-level-cache = <&L2_200>;
 149                         power-domains = <&CPU_PD2>;
 150                         power-domain-names = "psci";
 151                         qcom,freq-domain = <&cpufreq_hw 0>;
 152                         operating-points-v2 = <&cpu0_opp_table>;
 153                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 154                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 155                         #cooling-cells = <2>;
 156                         L2_200: l2-cache {
 157                                 compatible = "cache";
 158                                 next-level-cache = <&L3_0>;
 159                         };
 160                 };
 161
 162                 CPU3: cpu@300 {
 163                         device_type = "cpu";
 164                         compatible = "qcom,kryo485";
 165                         reg = <0x0 0x300>;
 166                         enable-method = "psci";
 167                         capacity-dmips-mhz = <448>;
 168                         dynamic-power-coefficient = <205>;
 169                         next-level-cache = <&L2_300>;
 170                         power-domains = <&CPU_PD3>;
 171                         power-domain-names = "psci";
 172                         qcom,freq-domain = <&cpufreq_hw 0>;
 173                         operating-points-v2 = <&cpu0_opp_table>;
 174                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 175                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 176                         #cooling-cells = <2>;
 177                         L2_300: l2-cache {
 178                                 compatible = "cache";
 179                                 next-level-cache = <&L3_0>;
 180                         };
 181                 };
 182
 183                 CPU4: cpu@400 {
 184                         device_type = "cpu";
 185                         compatible = "qcom,kryo485";
 186                         reg = <0x0 0x400>;
 187                         enable-method = "psci";
 188                         capacity-dmips-mhz = <1024>;
 189                         dynamic-power-coefficient = <379>;
 190                         next-level-cache = <&L2_400>;
 191                         power-domains = <&CPU_PD4>;
 192                         power-domain-names = "psci";
 193                         qcom,freq-domain = <&cpufreq_hw 1>;
 194                         operating-points-v2 = <&cpu4_opp_table>;
 195                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 196                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 197                         #cooling-cells = <2>;
 198                         L2_400: l2-cache {
 199                                 compatible = "cache";
 200                                 next-level-cache = <&L3_0>;
 201                         };
 202                 };
 203
 204                 CPU5: cpu@500 {
 205                         device_type = "cpu";
 206                         compatible = "qcom,kryo485";
 207                         reg = <0x0 0x500>;
 208                         enable-method = "psci";
 209                         capacity-dmips-mhz = <1024>;
 210                         dynamic-power-coefficient = <379>;
 211                         next-level-cache = <&L2_500>;
 212                         power-domains = <&CPU_PD5>;
 213                         power-domain-names = "psci";
 214                         qcom,freq-domain = <&cpufreq_hw 1>;
 215                         operating-points-v2 = <&cpu4_opp_table>;
 216                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 217                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 218                         #cooling-cells = <2>;
 219                         L2_500: l2-cache {
 220                                 compatible = "cache";
 221                                 next-level-cache = <&L3_0>;
 222                         };
 223
 224                 };
 225
 226                 CPU6: cpu@600 {
 227                         device_type = "cpu";
 228                         compatible = "qcom,kryo485";
 229                         reg = <0x0 0x600>;
 230                         enable-method = "psci";
 231                         capacity-dmips-mhz = <1024>;
 232                         dynamic-power-coefficient = <379>;
 233                         next-level-cache = <&L2_600>;
 234                         power-domains = <&CPU_PD6>;
 235                         power-domain-names = "psci";
 236                         qcom,freq-domain = <&cpufreq_hw 1>;
 237                         operating-points-v2 = <&cpu4_opp_table>;
 238                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 239                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 240                         #cooling-cells = <2>;
 241                         L2_600: l2-cache {
 242                                 compatible = "cache";
 243                                 next-level-cache = <&L3_0>;
 244                         };
 245                 };
 246
 247                 CPU7: cpu@700 {
 248                         device_type = "cpu";
 249                         compatible = "qcom,kryo485";
 250                         reg = <0x0 0x700>;
 251                         enable-method = "psci";
 252                         capacity-dmips-mhz = <1024>;
 253                         dynamic-power-coefficient = <444>;
 254                         next-level-cache = <&L2_700>;
 255                         power-domains = <&CPU_PD7>;
 256                         power-domain-names = "psci";
 257                         qcom,freq-domain = <&cpufreq_hw 2>;
 258                         operating-points-v2 = <&cpu7_opp_table>;
 259                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 260                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 261                         #cooling-cells = <2>;
 262                         L2_700: l2-cache {
 263                                 compatible = "cache";
 264                                 next-level-cache = <&L3_0>;
 265                         };
 266                 };
 267
 268                 cpu-map {
 269                         cluster0 {
 270                                 core0 {
 271                                         cpu = <&CPU0>;
 272                                 };
 273
 274                                 core1 {
 275                                         cpu = <&CPU1>;
 276                                 };
 277
 278                                 core2 {
 279                                         cpu = <&CPU2>;
 280                                 };
 281
 282                                 core3 {
 283                                         cpu = <&CPU3>;
 284                                 };
 285
 286                                 core4 {
 287                                         cpu = <&CPU4>;
 288                                 };
 289
 290                                 core5 {
 291                                         cpu = <&CPU5>;
 292                                 };
 293
 294                                 core6 {
 295                                         cpu = <&CPU6>;
 296                                 };
 297
 298                                 core7 {
 299                                         cpu = <&CPU7>;
 300                                 };
 301                         };
 302                 };
 303
 304                 idle-states {
 305                         entry-method = "psci";
 306
 307                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 308                                 compatible = "arm,idle-state";
 309                                 idle-state-name = "silver-rail-power-collapse";
 310                                 arm,psci-suspend-param = <0x40000004>;
 311                                 entry-latency-us = <360>;
 312                                 exit-latency-us = <531>;
 313                                 min-residency-us = <3934>;
 314                                 local-timer-stop;
 315                         };
 316
 317                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 318                                 compatible = "arm,idle-state";
 319                                 idle-state-name = "gold-rail-power-collapse";
 320                                 arm,psci-suspend-param = <0x40000004>;
 321                                 entry-latency-us = <702>;
 322                                 exit-latency-us = <1061>;
 323                                 min-residency-us = <4488>;
 324                                 local-timer-stop;
 325                         };
 326                 };
 327
 328                 domain-idle-states {
 329                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 330                                 compatible = "domain-idle-state";
 331                                 idle-state-name = "cluster-llcc-off";
 332                                 arm,psci-suspend-param = <0x4100c244>;
 333                                 entry-latency-us = <3264>;
 334                                 exit-latency-us = <6562>;
 335                                 min-residency-us = <9987>;
 336                                 local-timer-stop;
 337                         };
 338                 };
 339         };
 340
 341         cpu0_opp_table: opp-table-cpu0 {
 342                 compatible = "operating-points-v2";
 343                 opp-shared;
 344
 345                 cpu0_opp1: opp-300000000 {
 346                         opp-hz = /bits/ 64 <300000000>;
 347                         opp-peak-kBps = <800000 9600000>;
 348                 };
 349
 350                 cpu0_opp2: opp-403200000 {
 351                         opp-hz = /bits/ 64 <403200000>;
 352                         opp-peak-kBps = <800000 9600000>;
 353                 };
 354
 355                 cpu0_opp3: opp-518400000 {
 356                         opp-hz = /bits/ 64 <518400000>;
 357                         opp-peak-kBps = <800000 16588800>;
 358                 };
 359
 360                 cpu0_opp4: opp-614400000 {
 361                         opp-hz = /bits/ 64 <614400000>;
 362                         opp-peak-kBps = <800000 16588800>;
 363                 };
 364
 365                 cpu0_opp5: opp-691200000 {
 366                         opp-hz = /bits/ 64 <691200000>;
 367                         opp-peak-kBps = <800000 19660800>;
 368                 };
 369
 370                 cpu0_opp6: opp-787200000 {
 371                         opp-hz = /bits/ 64 <787200000>;
 372                         opp-peak-kBps = <1804000 19660800>;
 373                 };
 374
 375                 cpu0_opp7: opp-883200000 {
 376                         opp-hz = /bits/ 64 <883200000>;
 377                         opp-peak-kBps = <1804000 23347200>;
 378                 };
 379
 380                 cpu0_opp8: opp-979200000 {
 381                         opp-hz = /bits/ 64 <979200000>;
 382                         opp-peak-kBps = <1804000 26419200>;
 383                 };
 384
 385                 cpu0_opp9: opp-1075200000 {
 386                         opp-hz = /bits/ 64 <1075200000>;
 387                         opp-peak-kBps = <1804000 29491200>;
 388                 };
 389
 390                 cpu0_opp10: opp-1171200000 {
 391                         opp-hz = /bits/ 64 <1171200000>;
 392                         opp-peak-kBps = <1804000 32563200>;
 393                 };
 394
 395                 cpu0_opp11: opp-1248000000 {
 396                         opp-hz = /bits/ 64 <1248000000>;
 397                         opp-peak-kBps = <1804000 36249600>;
 398                 };
 399
 400                 cpu0_opp12: opp-1344000000 {
 401                         opp-hz = /bits/ 64 <1344000000>;
 402                         opp-peak-kBps = <2188000 36249600>;
 403                 };
 404
 405                 cpu0_opp13: opp-1420800000 {
 406                         opp-hz = /bits/ 64 <1420800000>;
 407                         opp-peak-kBps = <2188000 39321600>;
 408                 };
 409
 410                 cpu0_opp14: opp-1516800000 {
 411                         opp-hz = /bits/ 64 <1516800000>;
 412                         opp-peak-kBps = <3072000 42393600>;
 413                 };
 414
 415                 cpu0_opp15: opp-1612800000 {
 416                         opp-hz = /bits/ 64 <1612800000>;
 417                         opp-peak-kBps = <3072000 42393600>;
 418                 };
 419
 420                 cpu0_opp16: opp-1708800000 {
 421                         opp-hz = /bits/ 64 <1708800000>;
 422                         opp-peak-kBps = <4068000 42393600>;
 423                 };
 424
 425                 cpu0_opp17: opp-1804800000 {
 426                         opp-hz = /bits/ 64 <1804800000>;
 427                         opp-peak-kBps = <4068000 42393600>;
 428                 };
 429         };
 430
 431         cpu4_opp_table: opp-table-cpu4 {
 432                 compatible = "operating-points-v2";
 433                 opp-shared;
 434
 435                 cpu4_opp1: opp-710400000 {
 436                         opp-hz = /bits/ 64 <710400000>;
 437                         opp-peak-kBps = <1804000 19660800>;
 438                 };
 439
 440                 cpu4_opp2: opp-825600000 {
 441                         opp-hz = /bits/ 64 <825600000>;
 442                         opp-peak-kBps = <2188000 23347200>;
 443                 };
 444
 445                 cpu4_opp3: opp-940800000 {
 446                         opp-hz = /bits/ 64 <940800000>;
 447                         opp-peak-kBps = <2188000 26419200>;
 448                 };
 449
 450                 cpu4_opp4: opp-1056000000 {
 451                         opp-hz = /bits/ 64 <1056000000>;
 452                         opp-peak-kBps = <3072000 26419200>;
 453                 };
 454
 455                 cpu4_opp5: opp-1171200000 {
 456                         opp-hz = /bits/ 64 <1171200000>;
 457                         opp-peak-kBps = <3072000 29491200>;
 458                 };
 459
 460                 cpu4_opp6: opp-1286400000 {
 461                         opp-hz = /bits/ 64 <1286400000>;
 462                         opp-peak-kBps = <4068000 29491200>;
 463                 };
 464
 465                 cpu4_opp7: opp-1382400000 {
 466                         opp-hz = /bits/ 64 <1382400000>;
 467                         opp-peak-kBps = <4068000 32563200>;
 468                 };
 469
 470                 cpu4_opp8: opp-1478400000 {
 471                         opp-hz = /bits/ 64 <1478400000>;
 472                         opp-peak-kBps = <4068000 32563200>;
 473                 };
 474
 475                 cpu4_opp9: opp-1574400000 {
 476                         opp-hz = /bits/ 64 <1574400000>;
 477                         opp-peak-kBps = <5412000 39321600>;
 478                 };
 479
 480                 cpu4_opp10: opp-1670400000 {
 481                         opp-hz = /bits/ 64 <1670400000>;
 482                         opp-peak-kBps = <5412000 42393600>;
 483                 };
 484
 485                 cpu4_opp11: opp-1766400000 {
 486                         opp-hz = /bits/ 64 <1766400000>;
 487                         opp-peak-kBps = <5412000 45465600>;
 488                 };
 489
 490                 cpu4_opp12: opp-1862400000 {
 491                         opp-hz = /bits/ 64 <1862400000>;
 492                         opp-peak-kBps = <6220000 45465600>;
 493                 };
 494
 495                 cpu4_opp13: opp-1958400000 {
 496                         opp-hz = /bits/ 64 <1958400000>;
 497                         opp-peak-kBps = <6220000 48537600>;
 498                 };
 499
 500                 cpu4_opp14: opp-2054400000 {
 501                         opp-hz = /bits/ 64 <2054400000>;
 502                         opp-peak-kBps = <7216000 48537600>;
 503                 };
 504
 505                 cpu4_opp15: opp-2150400000 {
 506                         opp-hz = /bits/ 64 <2150400000>;
 507                         opp-peak-kBps = <7216000 51609600>;
 508                 };
 509
 510                 cpu4_opp16: opp-2246400000 {
 511                         opp-hz = /bits/ 64 <2246400000>;
 512                         opp-peak-kBps = <7216000 51609600>;
 513                 };
 514
 515                 cpu4_opp17: opp-2342400000 {
 516                         opp-hz = /bits/ 64 <2342400000>;
 517                         opp-peak-kBps = <8368000 51609600>;
 518                 };
 519
 520                 cpu4_opp18: opp-2419200000 {
 521                         opp-hz = /bits/ 64 <2419200000>;
 522                         opp-peak-kBps = <8368000 51609600>;
 523                 };
 524         };
 525
 526         cpu7_opp_table: opp-table-cpu7 {
 527                 compatible = "operating-points-v2";
 528                 opp-shared;
 529
 530                 cpu7_opp1: opp-844800000 {
 531                         opp-hz = /bits/ 64 <844800000>;
 532                         opp-peak-kBps = <2188000 19660800>;
 533                 };
 534
 535                 cpu7_opp2: opp-960000000 {
 536                         opp-hz = /bits/ 64 <960000000>;
 537                         opp-peak-kBps = <2188000 26419200>;
 538                 };
 539
 540                 cpu7_opp3: opp-1075200000 {
 541                         opp-hz = /bits/ 64 <1075200000>;
 542                         opp-peak-kBps = <3072000 26419200>;
 543                 };
 544
 545                 cpu7_opp4: opp-1190400000 {
 546                         opp-hz = /bits/ 64 <1190400000>;
 547                         opp-peak-kBps = <3072000 29491200>;
 548                 };
 549
 550                 cpu7_opp5: opp-1305600000 {
 551                         opp-hz = /bits/ 64 <1305600000>;
 552                         opp-peak-kBps = <4068000 32563200>;
 553                 };
 554
 555                 cpu7_opp6: opp-1401600000 {
 556                         opp-hz = /bits/ 64 <1401600000>;
 557                         opp-peak-kBps = <4068000 32563200>;
 558                 };
 559
 560                 cpu7_opp7: opp-1516800000 {
 561                         opp-hz = /bits/ 64 <1516800000>;
 562                         opp-peak-kBps = <4068000 36249600>;
 563                 };
 564
 565                 cpu7_opp8: opp-1632000000 {
 566                         opp-hz = /bits/ 64 <1632000000>;
 567                         opp-peak-kBps = <5412000 39321600>;
 568                 };
 569
 570                 cpu7_opp9: opp-1747200000 {
 571                         opp-hz = /bits/ 64 <1708800000>;
 572                         opp-peak-kBps = <5412000 42393600>;
 573                 };
 574
 575                 cpu7_opp10: opp-1862400000 {
 576                         opp-hz = /bits/ 64 <1862400000>;
 577                         opp-peak-kBps = <6220000 45465600>;
 578                 };
 579
 580                 cpu7_opp11: opp-1977600000 {
 581                         opp-hz = /bits/ 64 <1977600000>;
 582                         opp-peak-kBps = <6220000 48537600>;
 583                 };
 584
 585                 cpu7_opp12: opp-2073600000 {
 586                         opp-hz = /bits/ 64 <2073600000>;
 587                         opp-peak-kBps = <7216000 48537600>;
 588                 };
 589
 590                 cpu7_opp13: opp-2169600000 {
 591                         opp-hz = /bits/ 64 <2169600000>;
 592                         opp-peak-kBps = <7216000 51609600>;
 593                 };
 594
 595                 cpu7_opp14: opp-2265600000 {
 596                         opp-hz = /bits/ 64 <2265600000>;
 597                         opp-peak-kBps = <7216000 51609600>;
 598                 };
 599
 600                 cpu7_opp15: opp-2361600000 {
 601                         opp-hz = /bits/ 64 <2361600000>;
 602                         opp-peak-kBps = <8368000 51609600>;
 603                 };
 604
 605                 cpu7_opp16: opp-2457600000 {
 606                         opp-hz = /bits/ 64 <2457600000>;
 607                         opp-peak-kBps = <8368000 51609600>;
 608                 };
 609
 610                 cpu7_opp17: opp-2553600000 {
 611                         opp-hz = /bits/ 64 <2553600000>;
 612                         opp-peak-kBps = <8368000 51609600>;
 613                 };
 614
 615                 cpu7_opp18: opp-2649600000 {
 616                         opp-hz = /bits/ 64 <2649600000>;
 617                         opp-peak-kBps = <8368000 51609600>;
 618                 };
 619
 620                 cpu7_opp19: opp-2745600000 {
 621                         opp-hz = /bits/ 64 <2745600000>;
 622                         opp-peak-kBps = <8368000 51609600>;
 623                 };
 624
 625                 cpu7_opp20: opp-2841600000 {
 626                         opp-hz = /bits/ 64 <2841600000>;
 627                         opp-peak-kBps = <8368000 51609600>;
 628                 };
 629         };
 630
 631         firmware {
 632                 scm: scm {
 633                         compatible = "qcom,scm-sm8250", "qcom,scm";
 634                         #reset-cells = <1>;
 635                 };
 636         };
 637
 638         memory@80000000 {
 639                 device_type = "memory";
 640                 /* We expect the bootloader to fill in the size */
 641                 reg = <0x0 0x80000000 0x0 0x0>;
 642         };
 643
 644         pmu {
 645                 compatible = "arm,armv8-pmuv3";
 646                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 647         };
 648
 649         psci {
 650                 compatible = "arm,psci-1.0";
 651                 method = "smc";
 652
 653                 CPU_PD0: cpu0 {
 654                         #power-domain-cells = <0>;
 655                         power-domains = <&CLUSTER_PD>;
 656                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 657                 };
 658
 659                 CPU_PD1: cpu1 {
 660                         #power-domain-cells = <0>;
 661                         power-domains = <&CLUSTER_PD>;
 662                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 663                 };
 664
 665                 CPU_PD2: cpu2 {
 666                         #power-domain-cells = <0>;
 667                         power-domains = <&CLUSTER_PD>;
 668                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 669                 };
 670
 671                 CPU_PD3: cpu3 {
 672                         #power-domain-cells = <0>;
 673                         power-domains = <&CLUSTER_PD>;
 674                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 675                 };
 676
 677                 CPU_PD4: cpu4 {
 678                         #power-domain-cells = <0>;
 679                         power-domains = <&CLUSTER_PD>;
 680                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 681                 };
 682
 683                 CPU_PD5: cpu5 {
 684                         #power-domain-cells = <0>;
 685                         power-domains = <&CLUSTER_PD>;
 686                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 687                 };
 688
 689                 CPU_PD6: cpu6 {
 690                         #power-domain-cells = <0>;
 691                         power-domains = <&CLUSTER_PD>;
 692                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 693                 };
 694
 695                 CPU_PD7: cpu7 {
 696                         #power-domain-cells = <0>;
 697                         power-domains = <&CLUSTER_PD>;
 698                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 699                 };
 700
 701                 CLUSTER_PD: cpu-cluster0 {
 702                         #power-domain-cells = <0>;
 703                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 704                 };
 705         };
 706
 707         qup_opp_table: opp-table-qup {
 708                 compatible = "operating-points-v2";
 709
 710                 opp-50000000 {
 711                         opp-hz = /bits/ 64 <50000000>;
 712                         required-opps = <&rpmhpd_opp_min_svs>;
 713                 };
 714
 715                 opp-75000000 {
 716                         opp-hz = /bits/ 64 <75000000>;
 717                         required-opps = <&rpmhpd_opp_low_svs>;
 718                 };
 719
 720                 opp-120000000 {
 721                         opp-hz = /bits/ 64 <120000000>;
 722                         required-opps = <&rpmhpd_opp_svs>;
 723                 };
 724         };
 725
 726         reserved-memory {
 727                 #address-cells = <2>;
 728                 #size-cells = <2>;
 729                 ranges;
 730
 731                 hyp_mem: memory@80000000 {
 732                         reg = <0x0 0x80000000 0x0 0x600000>;
 733                         no-map;
 734                 };
 735
 736                 xbl_aop_mem: memory@80700000 {
 737                         reg = <0x0 0x80700000 0x0 0x160000>;
 738                         no-map;
 739                 };
 740
 741                 cmd_db: memory@80860000 {
 742                         compatible = "qcom,cmd-db";
 743                         reg = <0x0 0x80860000 0x0 0x20000>;
 744                         no-map;
 745                 };
 746
 747                 smem_mem: memory@80900000 {
 748                         reg = <0x0 0x80900000 0x0 0x200000>;
 749                         no-map;
 750                 };
 751
 752                 removed_mem: memory@80b00000 {
 753                         reg = <0x0 0x80b00000 0x0 0x5300000>;
 754                         no-map;
 755                 };
 756
 757                 camera_mem: memory@86200000 {
 758                         reg = <0x0 0x86200000 0x0 0x500000>;
 759                         no-map;
 760                 };
 761
 762                 wlan_mem: memory@86700000 {
 763                         reg = <0x0 0x86700000 0x0 0x100000>;
 764                         no-map;
 765                 };
 766
 767                 ipa_fw_mem: memory@86800000 {
 768                         reg = <0x0 0x86800000 0x0 0x10000>;
 769                         no-map;
 770                 };
 771
 772                 ipa_gsi_mem: memory@86810000 {
 773                         reg = <0x0 0x86810000 0x0 0xa000>;
 774                         no-map;
 775                 };
 776
 777                 gpu_mem: memory@8681a000 {
 778                         reg = <0x0 0x8681a000 0x0 0x2000>;
 779                         no-map;
 780                 };
 781
 782                 npu_mem: memory@86900000 {
 783                         reg = <0x0 0x86900000 0x0 0x500000>;
 784                         no-map;
 785                 };
 786
 787                 video_mem: memory@86e00000 {
 788                         reg = <0x0 0x86e00000 0x0 0x500000>;
 789                         no-map;
 790                 };
 791
 792                 cvp_mem: memory@87300000 {
 793                         reg = <0x0 0x87300000 0x0 0x500000>;
 794                         no-map;
 795                 };
 796
 797                 cdsp_mem: memory@87800000 {
 798                         reg = <0x0 0x87800000 0x0 0x1400000>;
 799                         no-map;
 800                 };
 801
 802                 slpi_mem: memory@88c00000 {
 803                         reg = <0x0 0x88c00000 0x0 0x1500000>;
 804                         no-map;
 805                 };
 806
 807                 adsp_mem: memory@8a100000 {
 808                         reg = <0x0 0x8a100000 0x0 0x1d00000>;
 809                         no-map;
 810                 };
 811
 812                 spss_mem: memory@8be00000 {
 813                         reg = <0x0 0x8be00000 0x0 0x100000>;
 814                         no-map;
 815                 };
 816
 817                 cdsp_secure_heap: memory@8bf00000 {
 818                         reg = <0x0 0x8bf00000 0x0 0x4600000>;
 819                         no-map;
 820                 };
 821         };
 822
 823         smem {
 824                 compatible = "qcom,smem";
 825                 memory-region = <&smem_mem>;
 826                 hwlocks = <&tcsr_mutex 3>;
 827         };
 828
 829         smp2p-adsp {
 830                 compatible = "qcom,smp2p";
 831                 qcom,smem = <443>, <429>;
 832                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 833                                              IPCC_MPROC_SIGNAL_SMP2P
 834                                              IRQ_TYPE_EDGE_RISING>;
 835                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 836                                 IPCC_MPROC_SIGNAL_SMP2P>;
 837
 838                 qcom,local-pid = <0>;
 839                 qcom,remote-pid = <2>;
 840
 841                 smp2p_adsp_out: master-kernel {
 842                         qcom,entry-name = "master-kernel";
 843                         #qcom,smem-state-cells = <1>;
 844                 };
 845
 846                 smp2p_adsp_in: slave-kernel {
 847                         qcom,entry-name = "slave-kernel";
 848                         interrupt-controller;
 849                         #interrupt-cells = <2>;
 850                 };
 851         };
 852
 853         smp2p-cdsp {
 854                 compatible = "qcom,smp2p";
 855                 qcom,smem = <94>, <432>;
 856                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 857                                              IPCC_MPROC_SIGNAL_SMP2P
 858                                              IRQ_TYPE_EDGE_RISING>;
 859                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 860                                 IPCC_MPROC_SIGNAL_SMP2P>;
 861
 862                 qcom,local-pid = <0>;
 863                 qcom,remote-pid = <5>;
 864
 865                 smp2p_cdsp_out: master-kernel {
 866                         qcom,entry-name = "master-kernel";
 867                         #qcom,smem-state-cells = <1>;
 868                 };
 869
 870                 smp2p_cdsp_in: slave-kernel {
 871                         qcom,entry-name = "slave-kernel";
 872                         interrupt-controller;
 873                         #interrupt-cells = <2>;
 874                 };
 875         };
 876
 877         smp2p-slpi {
 878                 compatible = "qcom,smp2p";
 879                 qcom,smem = <481>, <430>;
 880                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
 881                                              IPCC_MPROC_SIGNAL_SMP2P
 882                                              IRQ_TYPE_EDGE_RISING>;
 883                 mboxes = <&ipcc IPCC_CLIENT_SLPI
 884                                 IPCC_MPROC_SIGNAL_SMP2P>;
 885
 886                 qcom,local-pid = <0>;
 887                 qcom,remote-pid = <3>;
 888
 889                 smp2p_slpi_out: master-kernel {
 890                         qcom,entry-name = "master-kernel";
 891                         #qcom,smem-state-cells = <1>;
 892                 };
 893
 894                 smp2p_slpi_in: slave-kernel {
 895                         qcom,entry-name = "slave-kernel";
 896                         interrupt-controller;
 897                         #interrupt-cells = <2>;
 898                 };
 899         };
 900
 901         soc: soc@0 {
 902                 #address-cells = <2>;
 903                 #size-cells = <2>;
 904                 ranges = <0 0 0 0 0x10 0>;
 905                 dma-ranges = <0 0 0 0 0x10 0>;
 906                 compatible = "simple-bus";
 907
 908                 gcc: clock-controller@100000 {
 909                         compatible = "qcom,gcc-sm8250";
 910                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 911                         #clock-cells = <1>;
 912                         #reset-cells = <1>;
 913                         #power-domain-cells = <1>;
 914                         clock-names = "bi_tcxo",
 915                                       "bi_tcxo_ao",
 916                                       "sleep_clk";
 917                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 918                                  <&rpmhcc RPMH_CXO_CLK_A>,
 919                                  <&sleep_clk>;
 920                 };
 921
 922                 ipcc: mailbox@408000 {
 923                         compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
 924                         reg = <0 0x00408000 0 0x1000>;
 925                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 926                         interrupt-controller;
 927                         #interrupt-cells = <3>;
 928                         #mbox-cells = <2>;
 929                 };
 930
 931                 rng: rng@793000 {
 932                         compatible = "qcom,prng-ee";
 933                         reg = <0 0x00793000 0 0x1000>;
 934                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 935                         clock-names = "core";
 936                 };
 937
 938                 gpi_dma2: dma-controller@800000 {
 939                         compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
 940                         reg = <0 0x00800000 0 0x70000>;
 941                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
 942                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
 943                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
 944                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
 945                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
 946                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
 947                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
 948                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
 949                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
 950                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
 951                         dma-channels = <10>;
 952                         dma-channel-mask = <0x3f>;
 953                         iommus = <&apps_smmu 0x76 0x0>;
 954                         #dma-cells = <3>;
 955                         status = "disabled";
 956                 };
 957
 958                 qupv3_id_2: geniqup@8c0000 {
 959                         compatible = "qcom,geni-se-qup";
 960                         reg = <0x0 0x008c0000 0x0 0x6000>;
 961                         clock-names = "m-ahb", "s-ahb";
 962                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 963                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 964                         #address-cells = <2>;
 965                         #size-cells = <2>;
 966                         iommus = <&apps_smmu 0x63 0x0>;
 967                         ranges;
 968                         status = "disabled";
 969
 970                         i2c14: i2c@880000 {
 971                                 compatible = "qcom,geni-i2c";
 972                                 reg = <0 0x00880000 0 0x4000>;
 973                                 clock-names = "se";
 974                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 975                                 pinctrl-names = "default";
 976                                 pinctrl-0 = <&qup_i2c14_default>;
 977                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 978                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
 979                                        <&gpi_dma2 1 0 QCOM_GPI_I2C>;
 980                                 dma-names = "tx", "rx";
 981                                 #address-cells = <1>;
 982                                 #size-cells = <0>;
 983                                 status = "disabled";
 984                         };
 985
 986                         spi14: spi@880000 {
 987                                 compatible = "qcom,geni-spi";
 988                                 reg = <0 0x00880000 0 0x4000>;
 989                                 clock-names = "se";
 990                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 991                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 992                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
 993                                        <&gpi_dma2 1 0 QCOM_GPI_SPI>;
 994                                 dma-names = "tx", "rx";
 995                                 power-domains = <&rpmhpd SM8250_CX>;
 996                                 operating-points-v2 = <&qup_opp_table>;
 997                                 #address-cells = <1>;
 998                                 #size-cells = <0>;
 999                                 status = "disabled";
1000                         };
1001
1002                         i2c15: i2c@884000 {
1003                                 compatible = "qcom,geni-i2c";
1004                                 reg = <0 0x00884000 0 0x4000>;
1005                                 clock-names = "se";
1006                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1007                                 pinctrl-names = "default";
1008                                 pinctrl-0 = <&qup_i2c15_default>;
1009                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1010                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1011                                        <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1012                                 dma-names = "tx", "rx";
1013                                 #address-cells = <1>;
1014                                 #size-cells = <0>;
1015                                 status = "disabled";
1016                         };
1017
1018                         spi15: spi@884000 {
1019                                 compatible = "qcom,geni-spi";
1020                                 reg = <0 0x00884000 0 0x4000>;
1021                                 clock-names = "se";
1022                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1023                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1024                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1025                                        <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1026                                 dma-names = "tx", "rx";
1027                                 power-domains = <&rpmhpd SM8250_CX>;
1028                                 operating-points-v2 = <&qup_opp_table>;
1029                                 #address-cells = <1>;
1030                                 #size-cells = <0>;
1031                                 status = "disabled";
1032                         };
1033
1034                         i2c16: i2c@888000 {
1035                                 compatible = "qcom,geni-i2c";
1036                                 reg = <0 0x00888000 0 0x4000>;
1037                                 clock-names = "se";
1038                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1039                                 pinctrl-names = "default";
1040                                 pinctrl-0 = <&qup_i2c16_default>;
1041                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1042                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1043                                        <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1044                                 dma-names = "tx", "rx";
1045                                 #address-cells = <1>;
1046                                 #size-cells = <0>;
1047                                 status = "disabled";
1048                         };
1049
1050                         spi16: spi@888000 {
1051                                 compatible = "qcom,geni-spi";
1052                                 reg = <0 0x00888000 0 0x4000>;
1053                                 clock-names = "se";
1054                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1055                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1056                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1057                                        <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1058                                 dma-names = "tx", "rx";
1059                                 power-domains = <&rpmhpd SM8250_CX>;
1060                                 operating-points-v2 = <&qup_opp_table>;
1061                                 #address-cells = <1>;
1062                                 #size-cells = <0>;
1063                                 status = "disabled";
1064                         };
1065
1066                         i2c17: i2c@88c000 {
1067                                 compatible = "qcom,geni-i2c";
1068                                 reg = <0 0x0088c000 0 0x4000>;
1069                                 clock-names = "se";
1070                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1071                                 pinctrl-names = "default";
1072                                 pinctrl-0 = <&qup_i2c17_default>;
1073                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1074                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1075                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1076                                 dma-names = "tx", "rx";
1077                                 #address-cells = <1>;
1078                                 #size-cells = <0>;
1079                                 status = "disabled";
1080                         };
1081
1082                         spi17: spi@88c000 {
1083                                 compatible = "qcom,geni-spi";
1084                                 reg = <0 0x0088c000 0 0x4000>;
1085                                 clock-names = "se";
1086                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1087                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1088                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1089                                        <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1090                                 dma-names = "tx", "rx";
1091                                 power-domains = <&rpmhpd SM8250_CX>;
1092                                 operating-points-v2 = <&qup_opp_table>;
1093                                 #address-cells = <1>;
1094                                 #size-cells = <0>;
1095                                 status = "disabled";
1096                         };
1097
1098                         uart17: serial@88c000 {
1099                                 compatible = "qcom,geni-uart";
1100                                 reg = <0 0x0088c000 0 0x4000>;
1101                                 clock-names = "se";
1102                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1103                                 pinctrl-names = "default";
1104                                 pinctrl-0 = <&qup_uart17_default>;
1105                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1106                                 power-domains = <&rpmhpd SM8250_CX>;
1107                                 operating-points-v2 = <&qup_opp_table>;
1108                                 status = "disabled";
1109                         };
1110
1111                         i2c18: i2c@890000 {
1112                                 compatible = "qcom,geni-i2c";
1113                                 reg = <0 0x00890000 0 0x4000>;
1114                                 clock-names = "se";
1115                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1116                                 pinctrl-names = "default";
1117                                 pinctrl-0 = <&qup_i2c18_default>;
1118                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1119                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1120                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1121                                 dma-names = "tx", "rx";
1122                                 #address-cells = <1>;
1123                                 #size-cells = <0>;
1124                                 status = "disabled";
1125                         };
1126
1127                         spi18: spi@890000 {
1128                                 compatible = "qcom,geni-spi";
1129                                 reg = <0 0x00890000 0 0x4000>;
1130                                 clock-names = "se";
1131                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1132                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1133                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1134                                        <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1135                                 dma-names = "tx", "rx";
1136                                 power-domains = <&rpmhpd SM8250_CX>;
1137                                 operating-points-v2 = <&qup_opp_table>;
1138                                 #address-cells = <1>;
1139                                 #size-cells = <0>;
1140                                 status = "disabled";
1141                         };
1142
1143                         uart18: serial@890000 {
1144                                 compatible = "qcom,geni-uart";
1145                                 reg = <0 0x00890000 0 0x4000>;
1146                                 clock-names = "se";
1147                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1148                                 pinctrl-names = "default";
1149                                 pinctrl-0 = <&qup_uart18_default>;
1150                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1151                                 power-domains = <&rpmhpd SM8250_CX>;
1152                                 operating-points-v2 = <&qup_opp_table>;
1153                                 status = "disabled";
1154                         };
1155
1156                         i2c19: i2c@894000 {
1157                                 compatible = "qcom,geni-i2c";
1158                                 reg = <0 0x00894000 0 0x4000>;
1159                                 clock-names = "se";
1160                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1161                                 pinctrl-names = "default";
1162                                 pinctrl-0 = <&qup_i2c19_default>;
1163                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1164                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1165                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1166                                 dma-names = "tx", "rx";
1167                                 #address-cells = <1>;
1168                                 #size-cells = <0>;
1169                                 status = "disabled";
1170                         };
1171
1172                         spi19: spi@894000 {
1173                                 compatible = "qcom,geni-spi";
1174                                 reg = <0 0x00894000 0 0x4000>;
1175                                 clock-names = "se";
1176                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1177                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1178                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1179                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1180                                 dma-names = "tx", "rx";
1181                                 power-domains = <&rpmhpd SM8250_CX>;
1182                                 operating-points-v2 = <&qup_opp_table>;
1183                                 #address-cells = <1>;
1184                                 #size-cells = <0>;
1185                                 status = "disabled";
1186                         };
1187                 };
1188
1189                 gpi_dma0: dma-controller@900000 {
1190                         compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1191                         reg = <0 0x00900000 0 0x70000>;
1192                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1193                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1194                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1195                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1196                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1197                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1198                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1199                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1200                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1201                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1202                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1203                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1204                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1205                         dma-channels = <15>;
1206                         dma-channel-mask = <0x7ff>;
1207                         iommus = <&apps_smmu 0x5b6 0x0>;
1208                         #dma-cells = <3>;
1209                         status = "disabled";
1210                 };
1211
1212                 qupv3_id_0: geniqup@9c0000 {
1213                         compatible = "qcom,geni-se-qup";
1214                         reg = <0x0 0x009c0000 0x0 0x6000>;
1215                         clock-names = "m-ahb", "s-ahb";
1216                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1217                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1218                         #address-cells = <2>;
1219                         #size-cells = <2>;
1220                         iommus = <&apps_smmu 0x5a3 0x0>;
1221                         ranges;
1222                         status = "disabled";
1223
1224                         i2c0: i2c@980000 {
1225                                 compatible = "qcom,geni-i2c";
1226                                 reg = <0 0x00980000 0 0x4000>;
1227                                 clock-names = "se";
1228                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1229                                 pinctrl-names = "default";
1230                                 pinctrl-0 = <&qup_i2c0_default>;
1231                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1232                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1233                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1234                                 dma-names = "tx", "rx";
1235                                 #address-cells = <1>;
1236                                 #size-cells = <0>;
1237                                 status = "disabled";
1238                         };
1239
1240                         spi0: spi@980000 {
1241                                 compatible = "qcom,geni-spi";
1242                                 reg = <0 0x00980000 0 0x4000>;
1243                                 clock-names = "se";
1244                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1245                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1246                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1247                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1248                                 dma-names = "tx", "rx";
1249                                 power-domains = <&rpmhpd SM8250_CX>;
1250                                 operating-points-v2 = <&qup_opp_table>;
1251                                 #address-cells = <1>;
1252                                 #size-cells = <0>;
1253                                 status = "disabled";
1254                         };
1255
1256                         i2c1: i2c@984000 {
1257                                 compatible = "qcom,geni-i2c";
1258                                 reg = <0 0x00984000 0 0x4000>;
1259                                 clock-names = "se";
1260                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1261                                 pinctrl-names = "default";
1262                                 pinctrl-0 = <&qup_i2c1_default>;
1263                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1264                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1265                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1266                                 dma-names = "tx", "rx";
1267                                 #address-cells = <1>;
1268                                 #size-cells = <0>;
1269                                 status = "disabled";
1270                         };
1271
1272                         spi1: spi@984000 {
1273                                 compatible = "qcom,geni-spi";
1274                                 reg = <0 0x00984000 0 0x4000>;
1275                                 clock-names = "se";
1276                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1277                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1278                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1279                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1280                                 dma-names = "tx", "rx";
1281                                 power-domains = <&rpmhpd SM8250_CX>;
1282                                 operating-points-v2 = <&qup_opp_table>;
1283                                 #address-cells = <1>;
1284                                 #size-cells = <0>;
1285                                 status = "disabled";
1286                         };
1287
1288                         i2c2: i2c@988000 {
1289                                 compatible = "qcom,geni-i2c";
1290                                 reg = <0 0x00988000 0 0x4000>;
1291                                 clock-names = "se";
1292                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1293                                 pinctrl-names = "default";
1294                                 pinctrl-0 = <&qup_i2c2_default>;
1295                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1296                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1297                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1298                                 dma-names = "tx", "rx";
1299                                 #address-cells = <1>;
1300                                 #size-cells = <0>;
1301                                 status = "disabled";
1302                         };
1303
1304                         spi2: spi@988000 {
1305                                 compatible = "qcom,geni-spi";
1306                                 reg = <0 0x00988000 0 0x4000>;
1307                                 clock-names = "se";
1308                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1309                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1310                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1311                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1312                                 dma-names = "tx", "rx";
1313                                 power-domains = <&rpmhpd SM8250_CX>;
1314                                 operating-points-v2 = <&qup_opp_table>;
1315                                 #address-cells = <1>;
1316                                 #size-cells = <0>;
1317                                 status = "disabled";
1318                         };
1319
1320                         uart2: serial@988000 {
1321                                 compatible = "qcom,geni-debug-uart";
1322                                 reg = <0 0x00988000 0 0x4000>;
1323                                 clock-names = "se";
1324                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1325                                 pinctrl-names = "default";
1326                                 pinctrl-0 = <&qup_uart2_default>;
1327                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1328                                 power-domains = <&rpmhpd SM8250_CX>;
1329                                 operating-points-v2 = <&qup_opp_table>;
1330                                 status = "disabled";
1331                         };
1332
1333                         i2c3: i2c@98c000 {
1334                                 compatible = "qcom,geni-i2c";
1335                                 reg = <0 0x0098c000 0 0x4000>;
1336                                 clock-names = "se";
1337                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1338                                 pinctrl-names = "default";
1339                                 pinctrl-0 = <&qup_i2c3_default>;
1340                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1341                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1342                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1343                                 dma-names = "tx", "rx";
1344                                 #address-cells = <1>;
1345                                 #size-cells = <0>;
1346                                 status = "disabled";
1347                         };
1348
1349                         spi3: spi@98c000 {
1350                                 compatible = "qcom,geni-spi";
1351                                 reg = <0 0x0098c000 0 0x4000>;
1352                                 clock-names = "se";
1353                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1354                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1355                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1356                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1357                                 dma-names = "tx", "rx";
1358                                 power-domains = <&rpmhpd SM8250_CX>;
1359                                 operating-points-v2 = <&qup_opp_table>;
1360                                 #address-cells = <1>;
1361                                 #size-cells = <0>;
1362                                 status = "disabled";
1363                         };
1364
1365                         i2c4: i2c@990000 {
1366                                 compatible = "qcom,geni-i2c";
1367                                 reg = <0 0x00990000 0 0x4000>;
1368                                 clock-names = "se";
1369                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1370                                 pinctrl-names = "default";
1371                                 pinctrl-0 = <&qup_i2c4_default>;
1372                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1373                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1374                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1375                                 dma-names = "tx", "rx";
1376                                 #address-cells = <1>;
1377                                 #size-cells = <0>;
1378                                 status = "disabled";
1379                         };
1380
1381                         spi4: spi@990000 {
1382                                 compatible = "qcom,geni-spi";
1383                                 reg = <0 0x00990000 0 0x4000>;
1384                                 clock-names = "se";
1385                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1386                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1387                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1388                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1389                                 dma-names = "tx", "rx";
1390                                 power-domains = <&rpmhpd SM8250_CX>;
1391                                 operating-points-v2 = <&qup_opp_table>;
1392                                 #address-cells = <1>;
1393                                 #size-cells = <0>;
1394                                 status = "disabled";
1395                         };
1396
1397                         i2c5: i2c@994000 {
1398                                 compatible = "qcom,geni-i2c";
1399                                 reg = <0 0x00994000 0 0x4000>;
1400                                 clock-names = "se";
1401                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1402                                 pinctrl-names = "default";
1403                                 pinctrl-0 = <&qup_i2c5_default>;
1404                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1405                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1406                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1407                                 dma-names = "tx", "rx";
1408                                 #address-cells = <1>;
1409                                 #size-cells = <0>;
1410                                 status = "disabled";
1411                         };
1412
1413                         spi5: spi@994000 {
1414                                 compatible = "qcom,geni-spi";
1415                                 reg = <0 0x00994000 0 0x4000>;
1416                                 clock-names = "se";
1417                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1418                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1419                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1420                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1421                                 dma-names = "tx", "rx";
1422                                 power-domains = <&rpmhpd SM8250_CX>;
1423                                 operating-points-v2 = <&qup_opp_table>;
1424                                 #address-cells = <1>;
1425                                 #size-cells = <0>;
1426                                 status = "disabled";
1427                         };
1428
1429                         i2c6: i2c@998000 {
1430                                 compatible = "qcom,geni-i2c";
1431                                 reg = <0 0x00998000 0 0x4000>;
1432                                 clock-names = "se";
1433                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1434                                 pinctrl-names = "default";
1435                                 pinctrl-0 = <&qup_i2c6_default>;
1436                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1437                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1438                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1439                                 dma-names = "tx", "rx";
1440                                 #address-cells = <1>;
1441                                 #size-cells = <0>;
1442                                 status = "disabled";
1443                         };
1444
1445                         spi6: spi@998000 {
1446                                 compatible = "qcom,geni-spi";
1447                                 reg = <0 0x00998000 0 0x4000>;
1448                                 clock-names = "se";
1449                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1450                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1451                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1452                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1453                                 dma-names = "tx", "rx";
1454                                 power-domains = <&rpmhpd SM8250_CX>;
1455                                 operating-points-v2 = <&qup_opp_table>;
1456                                 #address-cells = <1>;
1457                                 #size-cells = <0>;
1458                                 status = "disabled";
1459                         };
1460
1461                         uart6: serial@998000 {
1462                                 compatible = "qcom,geni-uart";
1463                                 reg = <0 0x00998000 0 0x4000>;
1464                                 clock-names = "se";
1465                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1466                                 pinctrl-names = "default";
1467                                 pinctrl-0 = <&qup_uart6_default>;
1468                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1469                                 power-domains = <&rpmhpd SM8250_CX>;
1470                                 operating-points-v2 = <&qup_opp_table>;
1471                                 status = "disabled";
1472                         };
1473
1474                         i2c7: i2c@99c000 {
1475                                 compatible = "qcom,geni-i2c";
1476                                 reg = <0 0x0099c000 0 0x4000>;
1477                                 clock-names = "se";
1478                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1479                                 pinctrl-names = "default";
1480                                 pinctrl-0 = <&qup_i2c7_default>;
1481                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1482                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1483                                        <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1484                                 dma-names = "tx", "rx";
1485                                 #address-cells = <1>;
1486                                 #size-cells = <0>;
1487                                 status = "disabled";
1488                         };
1489
1490                         spi7: spi@99c000 {
1491                                 compatible = "qcom,geni-spi";
1492                                 reg = <0 0x0099c000 0 0x4000>;
1493                                 clock-names = "se";
1494                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1495                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1496                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1497                                        <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1498                                 dma-names = "tx", "rx";
1499                                 power-domains = <&rpmhpd SM8250_CX>;
1500                                 operating-points-v2 = <&qup_opp_table>;
1501                                 #address-cells = <1>;
1502                                 #size-cells = <0>;
1503                                 status = "disabled";
1504                         };
1505                 };
1506
1507                 gpi_dma1: dma-controller@a00000 {
1508                         compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1509                         reg = <0 0x00a00000 0 0x70000>;
1510                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1511                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1512                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1513                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1514                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1515                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1516                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1517                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1518                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1519                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1520                         dma-channels = <10>;
1521                         dma-channel-mask = <0x3f>;
1522                         iommus = <&apps_smmu 0x56 0x0>;
1523                         #dma-cells = <3>;
1524                         status = "disabled";
1525                 };
1526
1527                 qupv3_id_1: geniqup@ac0000 {
1528                         compatible = "qcom,geni-se-qup";
1529                         reg = <0x0 0x00ac0000 0x0 0x6000>;
1530                         clock-names = "m-ahb", "s-ahb";
1531                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1532                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1533                         #address-cells = <2>;
1534                         #size-cells = <2>;
1535                         iommus = <&apps_smmu 0x43 0x0>;
1536                         ranges;
1537                         status = "disabled";
1538
1539                         i2c8: i2c@a80000 {
1540                                 compatible = "qcom,geni-i2c";
1541                                 reg = <0 0x00a80000 0 0x4000>;
1542                                 clock-names = "se";
1543                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1544                                 pinctrl-names = "default";
1545                                 pinctrl-0 = <&qup_i2c8_default>;
1546                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1547                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1548                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1549                                 dma-names = "tx", "rx";
1550                                 #address-cells = <1>;
1551                                 #size-cells = <0>;
1552                                 status = "disabled";
1553                         };
1554
1555                         spi8: spi@a80000 {
1556                                 compatible = "qcom,geni-spi";
1557                                 reg = <0 0x00a80000 0 0x4000>;
1558                                 clock-names = "se";
1559                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1560                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1561                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1562                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1563                                 dma-names = "tx", "rx";
1564                                 power-domains = <&rpmhpd SM8250_CX>;
1565                                 operating-points-v2 = <&qup_opp_table>;
1566                                 #address-cells = <1>;
1567                                 #size-cells = <0>;
1568                                 status = "disabled";
1569                         };
1570
1571                         i2c9: i2c@a84000 {
1572                                 compatible = "qcom,geni-i2c";
1573                                 reg = <0 0x00a84000 0 0x4000>;
1574                                 clock-names = "se";
1575                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1576                                 pinctrl-names = "default";
1577                                 pinctrl-0 = <&qup_i2c9_default>;
1578                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1579                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1580                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1581                                 dma-names = "tx", "rx";
1582                                 #address-cells = <1>;
1583                                 #size-cells = <0>;
1584                                 status = "disabled";
1585                         };
1586
1587                         spi9: spi@a84000 {
1588                                 compatible = "qcom,geni-spi";
1589                                 reg = <0 0x00a84000 0 0x4000>;
1590                                 clock-names = "se";
1591                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1592                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1593                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1594                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1595                                 dma-names = "tx", "rx";
1596                                 power-domains = <&rpmhpd SM8250_CX>;
1597                                 operating-points-v2 = <&qup_opp_table>;
1598                                 #address-cells = <1>;
1599                                 #size-cells = <0>;
1600                                 status = "disabled";
1601                         };
1602
1603                         i2c10: i2c@a88000 {
1604                                 compatible = "qcom,geni-i2c";
1605                                 reg = <0 0x00a88000 0 0x4000>;
1606                                 clock-names = "se";
1607                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1608                                 pinctrl-names = "default";
1609                                 pinctrl-0 = <&qup_i2c10_default>;
1610                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1611                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1612                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1613                                 dma-names = "tx", "rx";
1614                                 #address-cells = <1>;
1615                                 #size-cells = <0>;
1616                                 status = "disabled";
1617                         };
1618
1619                         spi10: spi@a88000 {
1620                                 compatible = "qcom,geni-spi";
1621                                 reg = <0 0x00a88000 0 0x4000>;
1622                                 clock-names = "se";
1623                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1624                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1625                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1626                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1627                                 dma-names = "tx", "rx";
1628                                 power-domains = <&rpmhpd SM8250_CX>;
1629                                 operating-points-v2 = <&qup_opp_table>;
1630                                 #address-cells = <1>;
1631                                 #size-cells = <0>;
1632                                 status = "disabled";
1633                         };
1634
1635                         i2c11: i2c@a8c000 {
1636                                 compatible = "qcom,geni-i2c";
1637                                 reg = <0 0x00a8c000 0 0x4000>;
1638                                 clock-names = "se";
1639                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1640                                 pinctrl-names = "default";
1641                                 pinctrl-0 = <&qup_i2c11_default>;
1642                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1643                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1644                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1645                                 dma-names = "tx", "rx";
1646                                 #address-cells = <1>;
1647                                 #size-cells = <0>;
1648                                 status = "disabled";
1649                         };
1650
1651                         spi11: spi@a8c000 {
1652                                 compatible = "qcom,geni-spi";
1653                                 reg = <0 0x00a8c000 0 0x4000>;
1654                                 clock-names = "se";
1655                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1656                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1657                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1658                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1659                                 dma-names = "tx", "rx";
1660                                 power-domains = <&rpmhpd SM8250_CX>;
1661                                 operating-points-v2 = <&qup_opp_table>;
1662                                 #address-cells = <1>;
1663                                 #size-cells = <0>;
1664                                 status = "disabled";
1665                         };
1666
1667                         i2c12: i2c@a90000 {
1668                                 compatible = "qcom,geni-i2c";
1669                                 reg = <0 0x00a90000 0 0x4000>;
1670                                 clock-names = "se";
1671                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1672                                 pinctrl-names = "default";
1673                                 pinctrl-0 = <&qup_i2c12_default>;
1674                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1675                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1676                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1677                                 dma-names = "tx", "rx";
1678                                 #address-cells = <1>;
1679                                 #size-cells = <0>;
1680                                 status = "disabled";
1681                         };
1682
1683                         spi12: spi@a90000 {
1684                                 compatible = "qcom,geni-spi";
1685                                 reg = <0 0x00a90000 0 0x4000>;
1686                                 clock-names = "se";
1687                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1688                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1689                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1690                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1691                                 dma-names = "tx", "rx";
1692                                 power-domains = <&rpmhpd SM8250_CX>;
1693                                 operating-points-v2 = <&qup_opp_table>;
1694                                 #address-cells = <1>;
1695                                 #size-cells = <0>;
1696                                 status = "disabled";
1697                         };
1698
1699                         uart12: serial@a90000 {
1700                                 compatible = "qcom,geni-debug-uart";
1701                                 reg = <0x0 0x00a90000 0x0 0x4000>;
1702                                 clock-names = "se";
1703                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1704                                 pinctrl-names = "default";
1705                                 pinctrl-0 = <&qup_uart12_default>;
1706                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1707                                 power-domains = <&rpmhpd SM8250_CX>;
1708                                 operating-points-v2 = <&qup_opp_table>;
1709                                 status = "disabled";
1710                         };
1711
1712                         i2c13: i2c@a94000 {
1713                                 compatible = "qcom,geni-i2c";
1714                                 reg = <0 0x00a94000 0 0x4000>;
1715                                 clock-names = "se";
1716                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1717                                 pinctrl-names = "default";
1718                                 pinctrl-0 = <&qup_i2c13_default>;
1719                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1720                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1721                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1722                                 dma-names = "tx", "rx";
1723                                 #address-cells = <1>;
1724                                 #size-cells = <0>;
1725                                 status = "disabled";
1726                         };
1727
1728                         spi13: spi@a94000 {
1729                                 compatible = "qcom,geni-spi";
1730                                 reg = <0 0x00a94000 0 0x4000>;
1731                                 clock-names = "se";
1732                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1733                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1734                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1735                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1736                                 dma-names = "tx", "rx";
1737                                 power-domains = <&rpmhpd SM8250_CX>;
1738                                 operating-points-v2 = <&qup_opp_table>;
1739                                 #address-cells = <1>;
1740                                 #size-cells = <0>;
1741                                 status = "disabled";
1742                         };
1743                 };
1744
1745                 config_noc: interconnect@1500000 {
1746                         compatible = "qcom,sm8250-config-noc";
1747                         reg = <0 0x01500000 0 0xa580>;
1748                         #interconnect-cells = <1>;
1749                         qcom,bcm-voters = <&apps_bcm_voter>;
1750                 };
1751
1752                 system_noc: interconnect@1620000 {
1753                         compatible = "qcom,sm8250-system-noc";
1754                         reg = <0 0x01620000 0 0x1c200>;
1755                         #interconnect-cells = <1>;
1756                         qcom,bcm-voters = <&apps_bcm_voter>;
1757                 };
1758
1759                 mc_virt: interconnect@163d000 {
1760                         compatible = "qcom,sm8250-mc-virt";
1761                         reg = <0 0x0163d000 0 0x1000>;
1762                         #interconnect-cells = <1>;
1763                         qcom,bcm-voters = <&apps_bcm_voter>;
1764                 };
1765
1766                 aggre1_noc: interconnect@16e0000 {
1767                         compatible = "qcom,sm8250-aggre1-noc";
1768                         reg = <0 0x016e0000 0 0x1f180>;
1769                         #interconnect-cells = <1>;
1770                         qcom,bcm-voters = <&apps_bcm_voter>;
1771                 };
1772
1773                 aggre2_noc: interconnect@1700000 {
1774                         compatible = "qcom,sm8250-aggre2-noc";
1775                         reg = <0 0x01700000 0 0x33000>;
1776                         #interconnect-cells = <1>;
1777                         qcom,bcm-voters = <&apps_bcm_voter>;
1778                 };
1779
1780                 compute_noc: interconnect@1733000 {
1781                         compatible = "qcom,sm8250-compute-noc";
1782                         reg = <0 0x01733000 0 0xa180>;
1783                         #interconnect-cells = <1>;
1784                         qcom,bcm-voters = <&apps_bcm_voter>;
1785                 };
1786
1787                 mmss_noc: interconnect@1740000 {
1788                         compatible = "qcom,sm8250-mmss-noc";
1789                         reg = <0 0x01740000 0 0x1f080>;
1790                         #interconnect-cells = <1>;
1791                         qcom,bcm-voters = <&apps_bcm_voter>;
1792                 };
1793
1794                 pcie0: pci@1c00000 {
1795                         compatible = "qcom,pcie-sm8250";
1796                         reg = <0 0x01c00000 0 0x3000>,
1797                               <0 0x60000000 0 0xf1d>,
1798                               <0 0x60000f20 0 0xa8>,
1799                               <0 0x60001000 0 0x1000>,
1800                               <0 0x60100000 0 0x100000>;
1801                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1802                         device_type = "pci";
1803                         linux,pci-domain = <0>;
1804                         bus-range = <0x00 0xff>;
1805                         num-lanes = <1>;
1806
1807                         #address-cells = <3>;
1808                         #size-cells = <2>;
1809
1810                         ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1811                                  <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1812
1813                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1814                                      <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1815                                      <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1816                                      <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1817                                      <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1818                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1819                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1820                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1821                         interrupt-names = "msi0", "msi1", "msi2", "msi3",
1822                                           "msi4", "msi5", "msi6", "msi7";
1823                         #interrupt-cells = <1>;
1824                         interrupt-map-mask = <0 0 0 0x7>;
1825                         interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1826                                         <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1827                                         <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1828                                         <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1829
1830                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1831                                  <&gcc GCC_PCIE_0_AUX_CLK>,
1832                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1833                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1834                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1835                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1836                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1837                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1838                         clock-names = "pipe",
1839                                       "aux",
1840                                       "cfg",
1841                                       "bus_master",
1842                                       "bus_slave",
1843                                       "slave_q2a",
1844                                       "tbu",
1845                                       "ddrss_sf_tbu";
1846
1847                         iommus = <&apps_smmu 0x1c00 0x7f>;
1848                         iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
1849                                     <0x100 &apps_smmu 0x1c01 0x1>;
1850
1851                         resets = <&gcc GCC_PCIE_0_BCR>;
1852                         reset-names = "pci";
1853
1854                         power-domains = <&gcc PCIE_0_GDSC>;
1855
1856                         phys = <&pcie0_lane>;
1857                         phy-names = "pciephy";
1858
1859                         perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
1860                         wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
1861
1862                         pinctrl-names = "default";
1863                         pinctrl-0 = <&pcie0_default_state>;
1864
1865                         status = "disabled";
1866                 };
1867
1868                 pcie0_phy: phy@1c06000 {
1869                         compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
1870                         reg = <0 0x01c06000 0 0x1c0>;
1871                         #address-cells = <2>;
1872                         #size-cells = <2>;
1873                         ranges;
1874                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1875                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1876                                  <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
1877                                  <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1878                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1879
1880                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1881                         reset-names = "phy";
1882
1883                         assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1884                         assigned-clock-rates = <100000000>;
1885
1886                         status = "disabled";
1887
1888                         pcie0_lane: phy@1c06200 {
1889                                 reg = <0 0x1c06200 0 0x170>, /* tx */
1890                                       <0 0x1c06400 0 0x200>, /* rx */
1891                                       <0 0x1c06800 0 0x1f0>, /* pcs */
1892                                       <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
1893                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1894                                 clock-names = "pipe0";
1895
1896                                 #phy-cells = <0>;
1897
1898                                 #clock-cells = <0>;
1899                                 clock-output-names = "pcie_0_pipe_clk";
1900                         };
1901                 };
1902
1903                 pcie1: pci@1c08000 {
1904                         compatible = "qcom,pcie-sm8250";
1905                         reg = <0 0x01c08000 0 0x3000>,
1906                               <0 0x40000000 0 0xf1d>,
1907                               <0 0x40000f20 0 0xa8>,
1908                               <0 0x40001000 0 0x1000>,
1909                               <0 0x40100000 0 0x100000>;
1910                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1911                         device_type = "pci";
1912                         linux,pci-domain = <1>;
1913                         bus-range = <0x00 0xff>;
1914                         num-lanes = <2>;
1915
1916                         #address-cells = <3>;
1917                         #size-cells = <2>;
1918
1919                         ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1920                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1921
1922                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1923                         interrupt-names = "msi";
1924                         #interrupt-cells = <1>;
1925                         interrupt-map-mask = <0 0 0 0x7>;
1926                         interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1927                                         <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1928                                         <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1929                                         <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1930
1931                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1932                                  <&gcc GCC_PCIE_1_AUX_CLK>,
1933                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1934                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1935                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1936                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1937                                  <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1938                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1939                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1940                         clock-names = "pipe",
1941                                       "aux",
1942                                       "cfg",
1943                                       "bus_master",
1944                                       "bus_slave",
1945                                       "slave_q2a",
1946                                       "ref",
1947                                       "tbu",
1948                                       "ddrss_sf_tbu";
1949
1950                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1951                         assigned-clock-rates = <19200000>;
1952
1953                         iommus = <&apps_smmu 0x1c80 0x7f>;
1954                         iommu-map = <0x0   &apps_smmu 0x1c80 0x1>,
1955                                     <0x100 &apps_smmu 0x1c81 0x1>;
1956
1957                         resets = <&gcc GCC_PCIE_1_BCR>;
1958                         reset-names = "pci";
1959
1960                         power-domains = <&gcc PCIE_1_GDSC>;
1961
1962                         phys = <&pcie1_lane>;
1963                         phy-names = "pciephy";
1964
1965                         perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
1966                         wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
1967
1968                         pinctrl-names = "default";
1969                         pinctrl-0 = <&pcie1_default_state>;
1970
1971                         status = "disabled";
1972                 };
1973
1974                 pcie1_phy: phy@1c0e000 {
1975                         compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
1976                         reg = <0 0x01c0e000 0 0x1c0>;
1977                         #address-cells = <2>;
1978                         #size-cells = <2>;
1979                         ranges;
1980                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1981                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1982                                  <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1983                                  <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1984                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1985
1986                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1987                         reset-names = "phy";
1988
1989                         assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1990                         assigned-clock-rates = <100000000>;
1991
1992                         status = "disabled";
1993
1994                         pcie1_lane: phy@1c0e200 {
1995                                 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
1996                                       <0 0x1c0e400 0 0x200>, /* rx0 */
1997                                       <0 0x1c0ea00 0 0x1f0>, /* pcs */
1998                                       <0 0x1c0e600 0 0x170>, /* tx1 */
1999                                       <0 0x1c0e800 0 0x200>, /* rx1 */
2000                                       <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
2001                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
2002                                 clock-names = "pipe0";
2003
2004                                 #phy-cells = <0>;
2005
2006                                 #clock-cells = <0>;
2007                                 clock-output-names = "pcie_1_pipe_clk";
2008                         };
2009                 };
2010
2011                 pcie2: pci@1c10000 {
2012                         compatible = "qcom,pcie-sm8250";
2013                         reg = <0 0x01c10000 0 0x3000>,
2014                               <0 0x64000000 0 0xf1d>,
2015                               <0 0x64000f20 0 0xa8>,
2016                               <0 0x64001000 0 0x1000>,
2017                               <0 0x64100000 0 0x100000>;
2018                         reg-names = "parf", "dbi", "elbi", "atu", "config";
2019                         device_type = "pci";
2020                         linux,pci-domain = <2>;
2021                         bus-range = <0x00 0xff>;
2022                         num-lanes = <2>;
2023
2024                         #address-cells = <3>;
2025                         #size-cells = <2>;
2026
2027                         ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>,
2028                                  <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2029
2030                         interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2031                         interrupt-names = "msi";
2032                         #interrupt-cells = <1>;
2033                         interrupt-map-mask = <0 0 0 0x7>;
2034                         interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2035                                         <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2036                                         <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2037                                         <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2038
2039                         clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2040                                  <&gcc GCC_PCIE_2_AUX_CLK>,
2041                                  <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2042                                  <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2043                                  <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2044                                  <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2045                                  <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2046                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2047                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2048                         clock-names = "pipe",
2049                                       "aux",
2050                                       "cfg",
2051                                       "bus_master",
2052                                       "bus_slave",
2053                                       "slave_q2a",
2054                                       "ref",
2055                                       "tbu",
2056                                       "ddrss_sf_tbu";
2057
2058                         assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2059                         assigned-clock-rates = <19200000>;
2060
2061                         iommus = <&apps_smmu 0x1d00 0x7f>;
2062                         iommu-map = <0x0   &apps_smmu 0x1d00 0x1>,
2063                                     <0x100 &apps_smmu 0x1d01 0x1>;
2064
2065                         resets = <&gcc GCC_PCIE_2_BCR>;
2066                         reset-names = "pci";
2067
2068                         power-domains = <&gcc PCIE_2_GDSC>;
2069
2070                         phys = <&pcie2_lane>;
2071                         phy-names = "pciephy";
2072
2073                         perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2074                         wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2075
2076                         pinctrl-names = "default";
2077                         pinctrl-0 = <&pcie2_default_state>;
2078
2079                         status = "disabled";
2080                 };
2081
2082                 pcie2_phy: phy@1c16000 {
2083                         compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2084                         reg = <0 0x1c16000 0 0x1c0>;
2085                         #address-cells = <2>;
2086                         #size-cells = <2>;
2087                         ranges;
2088                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2089                                  <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2090                                  <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2091                                  <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2092                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
2093
2094                         resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2095                         reset-names = "phy";
2096
2097                         assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2098                         assigned-clock-rates = <100000000>;
2099
2100                         status = "disabled";
2101
2102                         pcie2_lane: phy@1c16200 {
2103                                 reg = <0 0x1c16200 0 0x170>, /* tx0 */
2104                                       <0 0x1c16400 0 0x200>, /* rx0 */
2105                                       <0 0x1c16a00 0 0x1f0>, /* pcs */
2106                                       <0 0x1c16600 0 0x170>, /* tx1 */
2107                                       <0 0x1c16800 0 0x200>, /* rx1 */
2108                                       <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
2109                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
2110                                 clock-names = "pipe0";
2111
2112                                 #phy-cells = <0>;
2113
2114                                 #clock-cells = <0>;
2115                                 clock-output-names = "pcie_2_pipe_clk";
2116                         };
2117                 };
2118
2119                 ufs_mem_hc: ufshc@1d84000 {
2120                         compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2121                                      "jedec,ufs-2.0";
2122                         reg = <0 0x01d84000 0 0x3000>;
2123                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2124                         phys = <&ufs_mem_phy_lanes>;
2125                         phy-names = "ufsphy";
2126                         lanes-per-direction = <2>;
2127                         #reset-cells = <1>;
2128                         resets = <&gcc GCC_UFS_PHY_BCR>;
2129                         reset-names = "rst";
2130
2131                         power-domains = <&gcc UFS_PHY_GDSC>;
2132
2133                         iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2134
2135                         clock-names =
2136                                 "core_clk",
2137                                 "bus_aggr_clk",
2138                                 "iface_clk",
2139                                 "core_clk_unipro",
2140                                 "ref_clk",
2141                                 "tx_lane0_sync_clk",
2142                                 "rx_lane0_sync_clk",
2143                                 "rx_lane1_sync_clk";
2144                         clocks =
2145                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
2146                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2147                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
2148                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2149                                 <&rpmhcc RPMH_CXO_CLK>,
2150                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2151                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2152                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2153                         freq-table-hz =
2154                                 <37500000 300000000>,
2155                                 <0 0>,
2156                                 <0 0>,
2157                                 <37500000 300000000>,
2158                                 <0 0>,
2159                                 <0 0>,
2160                                 <0 0>,
2161                                 <0 0>;
2162
2163                         status = "disabled";
2164                 };
2165
2166                 ufs_mem_phy: phy@1d87000 {
2167                         compatible = "qcom,sm8250-qmp-ufs-phy";
2168                         reg = <0 0x01d87000 0 0x1c0>;
2169                         #address-cells = <2>;
2170                         #size-cells = <2>;
2171                         ranges;
2172                         clock-names = "ref",
2173                                       "ref_aux";
2174                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2175                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2176
2177                         resets = <&ufs_mem_hc 0>;
2178                         reset-names = "ufsphy";
2179                         status = "disabled";
2180
2181                         ufs_mem_phy_lanes: phy@1d87400 {
2182                                 reg = <0 0x01d87400 0 0x16c>,
2183                                       <0 0x01d87600 0 0x200>,
2184                                       <0 0x01d87c00 0 0x200>,
2185                                       <0 0x01d87800 0 0x16c>,
2186                                       <0 0x01d87a00 0 0x200>;
2187                                 #phy-cells = <0>;
2188                         };
2189                 };
2190
2191                 ipa_virt: interconnect@1e00000 {
2192                         compatible = "qcom,sm8250-ipa-virt";
2193                         reg = <0 0x01e00000 0 0x1000>;
2194                         #interconnect-cells = <1>;
2195                         qcom,bcm-voters = <&apps_bcm_voter>;
2196                 };
2197
2198                 tcsr_mutex: hwlock@1f40000 {
2199                         compatible = "qcom,tcsr-mutex";
2200                         reg = <0x0 0x01f40000 0x0 0x40000>;
2201                         #hwlock-cells = <1>;
2202                 };
2203
2204                 wsamacro: codec@3240000 {
2205                         compatible = "qcom,sm8250-lpass-wsa-macro";
2206                         reg = <0 0x03240000 0 0x1000>;
2207                         clocks = <&audiocc LPASS_CDC_WSA_MCLK>,
2208                                  <&audiocc LPASS_CDC_WSA_NPL>,
2209                                  <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2210                                  <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2211                                  <&aoncc LPASS_CDC_VA_MCLK>,
2212                                  <&vamacro>;
2213
2214                         clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2215
2216                         #clock-cells = <0>;
2217                         clock-frequency = <9600000>;
2218                         clock-output-names = "mclk";
2219                         #sound-dai-cells = <1>;
2220
2221                         pinctrl-names = "default";
2222                         pinctrl-0 = <&wsa_swr_active>;
2223                 };
2224
2225                 swr0: soundwire-controller@3250000 {
2226                         reg = <0 0x03250000 0 0x2000>;
2227                         compatible = "qcom,soundwire-v1.5.1";
2228                         interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2229                         clocks = <&wsamacro>;
2230                         clock-names = "iface";
2231
2232                         qcom,din-ports = <2>;
2233                         qcom,dout-ports = <6>;
2234
2235                         qcom,ports-sinterval-low =      /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2236                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2237                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2238                         qcom,ports-block-pack-mode =    /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2239
2240                         #sound-dai-cells = <1>;
2241                         #address-cells = <2>;
2242                         #size-cells = <0>;
2243                 };
2244
2245                 audiocc: clock-controller@3300000 {
2246                         compatible = "qcom,sm8250-lpass-audiocc";
2247                         reg = <0 0x03300000 0 0x30000>;
2248                         #clock-cells = <1>;
2249                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2250                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2251                                 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2252                         clock-names = "core", "audio", "bus";
2253                 };
2254
2255                 vamacro: codec@3370000 {
2256                         compatible = "qcom,sm8250-lpass-va-macro";
2257                         reg = <0 0x03370000 0 0x1000>;
2258                         clocks = <&aoncc LPASS_CDC_VA_MCLK>,
2259                                 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2260                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2261
2262                         clock-names = "mclk", "macro", "dcodec";
2263
2264                         #clock-cells = <0>;
2265                         clock-frequency = <9600000>;
2266                         clock-output-names = "fsgen";
2267                         #sound-dai-cells = <1>;
2268                 };
2269
2270                 rxmacro: rxmacro@3200000 {
2271                         pinctrl-names = "default";
2272                         pinctrl-0 = <&rx_swr_active>;
2273                         compatible = "qcom,sm8250-lpass-rx-macro";
2274                         reg = <0 0x3200000 0 0x1000>;
2275                         status = "disabled";
2276
2277                         clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2278                                 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK  LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2279                                 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2280                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2281                                 <&vamacro>;
2282
2283                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2284
2285                         #clock-cells = <0>;
2286                         clock-frequency = <9600000>;
2287                         clock-output-names = "mclk";
2288                         #sound-dai-cells = <1>;
2289                 };
2290
2291                 swr1: soundwire-controller@3210000 {
2292                         reg = <0 0x3210000 0 0x2000>;
2293                         compatible = "qcom,soundwire-v1.5.1";
2294                         status = "disabled";
2295                         interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
2296                         clocks = <&rxmacro>;
2297                         clock-names = "iface";
2298                         label = "RX";
2299                         qcom,din-ports = <0>;
2300                         qcom,dout-ports = <5>;
2301
2302                         qcom,ports-sinterval-low =      /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>;
2303                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2304                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2305                         qcom,ports-hstart =             /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>;
2306                         qcom,ports-hstop =              /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>;
2307                         qcom,ports-word-length =        /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>;
2308                         qcom,ports-block-pack-mode =    /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>;
2309                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2310                         qcom,ports-block-group-count =  /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>;
2311
2312                         #sound-dai-cells = <1>;
2313                         #address-cells = <2>;
2314                         #size-cells = <0>;
2315                 };
2316
2317                 txmacro: txmacro@3220000 {
2318                         pinctrl-names = "default";
2319                         pinctrl-0 = <&tx_swr_active>;
2320                         compatible = "qcom,sm8250-lpass-tx-macro";
2321                         reg = <0 0x3220000 0 0x1000>;
2322                         status = "disabled";
2323
2324                         clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2325                                  <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK  LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2326                                  <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2327                                  <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2328                                  <&vamacro>;
2329
2330                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2331
2332                         #clock-cells = <0>;
2333                         clock-frequency = <9600000>;
2334                         clock-output-names = "mclk";
2335                         #address-cells = <2>;
2336                         #size-cells = <2>;
2337                         #sound-dai-cells = <1>;
2338                 };
2339
2340                 /* tx macro */
2341                 swr2: soundwire-controller@3230000 {
2342                         reg = <0 0x3230000 0 0x2000>;
2343                         compatible = "qcom,soundwire-v1.5.1";
2344                         interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
2345                         interrupt-names = "core";
2346                         status = "disabled";
2347
2348                         clocks = <&txmacro>;
2349                         clock-names = "iface";
2350                         label = "TX";
2351
2352                         qcom,din-ports = <5>;
2353                         qcom,dout-ports = <0>;
2354                         qcom,ports-sinterval-low =      /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>;
2355                         qcom,ports-offset1 =            /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>;
2356                         qcom,ports-offset2 =            /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>;
2357                         qcom,ports-block-pack-mode =    /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2358                         qcom,ports-hstart =             /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2359                         qcom,ports-hstop =              /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2360                         qcom,ports-word-length =        /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2361                         qcom,ports-block-group-count =  /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2362                         qcom,ports-lane-control =       /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>;
2363                         #sound-dai-cells = <1>;
2364                         #address-cells = <2>;
2365                         #size-cells = <0>;
2366                 };
2367
2368                 aoncc: clock-controller@3380000 {
2369                         compatible = "qcom,sm8250-lpass-aoncc";
2370                         reg = <0 0x03380000 0 0x40000>;
2371                         #clock-cells = <1>;
2372                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2373                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2374                                 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2375                         clock-names = "core", "audio", "bus";
2376                 };
2377
2378                 lpass_tlmm: pinctrl@33c0000{
2379                         compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2380                         reg = <0 0x033c0000 0x0 0x20000>,
2381                               <0 0x03550000 0x0 0x10000>;
2382                         gpio-controller;
2383                         #gpio-cells = <2>;
2384                         gpio-ranges = <&lpass_tlmm 0 0 14>;
2385
2386                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2387                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2388                         clock-names = "core", "audio";
2389
2390                         wsa_swr_active: wsa-swr-active-state {
2391                                 clk-pins {
2392                                         pins = "gpio10";
2393                                         function = "wsa_swr_clk";
2394                                         drive-strength = <2>;
2395                                         slew-rate = <1>;
2396                                         bias-disable;
2397                                 };
2398
2399                                 data-pins {
2400                                         pins = "gpio11";
2401                                         function = "wsa_swr_data";
2402                                         drive-strength = <2>;
2403                                         slew-rate = <1>;
2404                                         bias-bus-hold;
2405
2406                                 };
2407                         };
2408
2409                         wsa_swr_sleep: wsa-swr-sleep-state {
2410                                 clk-pins {
2411                                         pins = "gpio10";
2412                                         function = "wsa_swr_clk";
2413                                         drive-strength = <2>;
2414                                         input-enable;
2415                                         bias-pull-down;
2416                                 };
2417
2418                                 data-pins {
2419                                         pins = "gpio11";
2420                                         function = "wsa_swr_data";
2421                                         drive-strength = <2>;
2422                                         input-enable;
2423                                         bias-pull-down;
2424
2425                                 };
2426                         };
2427
2428                         dmic01_active: dmic01-active-state {
2429                                 clk-pins {
2430                                         pins = "gpio6";
2431                                         function = "dmic1_clk";
2432                                         drive-strength = <8>;
2433                                         output-high;
2434                                 };
2435                                 data-pins {
2436                                         pins = "gpio7";
2437                                         function = "dmic1_data";
2438                                         drive-strength = <8>;
2439                                         input-enable;
2440                                 };
2441                         };
2442
2443                         dmic01_sleep: dmic01-sleep-state {
2444                                 clk-pins {
2445                                         pins = "gpio6";
2446                                         function = "dmic1_clk";
2447                                         drive-strength = <2>;
2448                                         bias-disable;
2449                                         output-low;
2450                                 };
2451
2452                                 data-pins {
2453                                         pins = "gpio7";
2454                                         function = "dmic1_data";
2455                                         drive-strength = <2>;
2456                                         bias-pull-down;
2457                                         input-enable;
2458                                 };
2459                         };
2460
2461                         rx_swr_active: rx-swr-active-state {
2462                                 clk-pins {
2463                                         pins = "gpio3";
2464                                         function = "swr_rx_clk";
2465                                         drive-strength = <2>;
2466                                         slew-rate = <1>;
2467                                         bias-disable;
2468                                 };
2469
2470                                 data-pins {
2471                                         pins = "gpio4", "gpio5";
2472                                         function = "swr_rx_data";
2473                                         drive-strength = <2>;
2474                                         slew-rate = <1>;
2475                                         bias-bus-hold;
2476                                 };
2477                         };
2478
2479                         tx_swr_active: tx-swr-active-state {
2480                                 clk-pins {
2481                                         pins = "gpio0";
2482                                         function = "swr_tx_clk";
2483                                         drive-strength = <2>;
2484                                         slew-rate = <1>;
2485                                         bias-disable;
2486                                 };
2487
2488                                 data-pins {
2489                                         pins = "gpio1", "gpio2";
2490                                         function = "swr_tx_data";
2491                                         drive-strength = <2>;
2492                                         slew-rate = <1>;
2493                                         bias-bus-hold;
2494                                 };
2495                         };
2496
2497                         tx_swr_sleep: tx-swr-sleep-state {
2498                                 clk-pins {
2499                                         pins = "gpio0";
2500                                         function = "swr_tx_clk";
2501                                         drive-strength = <2>;
2502                                         input-enable;
2503                                         bias-pull-down;
2504                                 };
2505
2506                                 data1-pins {
2507                                         pins = "gpio1";
2508                                         function = "swr_tx_data";
2509                                         drive-strength = <2>;
2510                                         input-enable;
2511                                         bias-bus-hold;
2512                                 };
2513
2514                                 data2-pins {
2515                                         pins = "gpio2";
2516                                         function = "swr_tx_data";
2517                                         drive-strength = <2>;
2518                                         input-enable;
2519                                         bias-pull-down;
2520                                 };
2521                         };
2522                 };
2523
2524                 gpu: gpu@3d00000 {
2525                         compatible = "qcom,adreno-650.2",
2526                                      "qcom,adreno";
2527
2528                         reg = <0 0x03d00000 0 0x40000>;
2529                         reg-names = "kgsl_3d0_reg_memory";
2530
2531                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2532
2533                         iommus = <&adreno_smmu 0 0x401>;
2534
2535                         operating-points-v2 = <&gpu_opp_table>;
2536
2537                         qcom,gmu = <&gmu>;
2538
2539                         status = "disabled";
2540
2541                         zap-shader {
2542                                 memory-region = <&gpu_mem>;
2543                         };
2544
2545                         /* note: downstream checks gpu binning for 670 Mhz */
2546                         gpu_opp_table: opp-table {
2547                                 compatible = "operating-points-v2";
2548
2549                                 opp-670000000 {
2550                                         opp-hz = /bits/ 64 <670000000>;
2551                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2552                                 };
2553
2554                                 opp-587000000 {
2555                                         opp-hz = /bits/ 64 <587000000>;
2556                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2557                                 };
2558
2559                                 opp-525000000 {
2560                                         opp-hz = /bits/ 64 <525000000>;
2561                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2562                                 };
2563
2564                                 opp-490000000 {
2565                                         opp-hz = /bits/ 64 <490000000>;
2566                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2567                                 };
2568
2569                                 opp-441600000 {
2570                                         opp-hz = /bits/ 64 <441600000>;
2571                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2572                                 };
2573
2574                                 opp-400000000 {
2575                                         opp-hz = /bits/ 64 <400000000>;
2576                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2577                                 };
2578
2579                                 opp-305000000 {
2580                                         opp-hz = /bits/ 64 <305000000>;
2581                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2582                                 };
2583                         };
2584                 };
2585
2586                 gmu: gmu@3d6a000 {
2587                         compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2588
2589                         reg = <0 0x03d6a000 0 0x30000>,
2590                               <0 0x3de0000 0 0x10000>,
2591                               <0 0xb290000 0 0x10000>,
2592                               <0 0xb490000 0 0x10000>;
2593                         reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2594
2595                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2596                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2597                         interrupt-names = "hfi", "gmu";
2598
2599                         clocks = <&gpucc GPU_CC_AHB_CLK>,
2600                                  <&gpucc GPU_CC_CX_GMU_CLK>,
2601                                  <&gpucc GPU_CC_CXO_CLK>,
2602                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2603                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2604                         clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2605
2606                         power-domains = <&gpucc GPU_CX_GDSC>,
2607                                         <&gpucc GPU_GX_GDSC>;
2608                         power-domain-names = "cx", "gx";
2609
2610                         iommus = <&adreno_smmu 5 0x400>;
2611
2612                         operating-points-v2 = <&gmu_opp_table>;
2613
2614                         status = "disabled";
2615
2616                         gmu_opp_table: opp-table {
2617                                 compatible = "operating-points-v2";
2618
2619                                 opp-200000000 {
2620                                         opp-hz = /bits/ 64 <200000000>;
2621                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2622                                 };
2623                         };
2624                 };
2625
2626                 gpucc: clock-controller@3d90000 {
2627                         compatible = "qcom,sm8250-gpucc";
2628                         reg = <0 0x03d90000 0 0x9000>;
2629                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2630                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2631                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2632                         clock-names = "bi_tcxo",
2633                                       "gcc_gpu_gpll0_clk_src",
2634                                       "gcc_gpu_gpll0_div_clk_src";
2635                         #clock-cells = <1>;
2636                         #reset-cells = <1>;
2637                         #power-domain-cells = <1>;
2638                 };
2639
2640                 adreno_smmu: iommu@3da0000 {
2641                         compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
2642                         reg = <0 0x03da0000 0 0x10000>;
2643                         #iommu-cells = <2>;
2644                         #global-interrupts = <2>;
2645                         interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
2646                                      <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2647                                      <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2648                                      <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2649                                      <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2650                                      <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2651                                      <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2652                                      <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2653                                      <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2654                                      <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
2655                         clocks = <&gpucc GPU_CC_AHB_CLK>,
2656                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2657                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2658                         clock-names = "ahb", "bus", "iface";
2659
2660                         power-domains = <&gpucc GPU_CX_GDSC>;
2661                 };
2662
2663                 slpi: remoteproc@5c00000 {
2664                         compatible = "qcom,sm8250-slpi-pas";
2665                         reg = <0 0x05c00000 0 0x4000>;
2666
2667                         interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
2668                                               <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2669                                               <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2670                                               <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2671                                               <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2672                         interrupt-names = "wdog", "fatal", "ready",
2673                                           "handover", "stop-ack";
2674
2675                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2676                         clock-names = "xo";
2677
2678                         power-domains = <&rpmhpd SM8250_LCX>,
2679                                         <&rpmhpd SM8250_LMX>;
2680                         power-domain-names = "lcx", "lmx";
2681
2682                         memory-region = <&slpi_mem>;
2683
2684                         qcom,qmp = <&aoss_qmp>;
2685
2686                         qcom,smem-states = <&smp2p_slpi_out 0>;
2687                         qcom,smem-state-names = "stop";
2688
2689                         status = "disabled";
2690
2691                         glink-edge {
2692                                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2693                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2694                                                              IRQ_TYPE_EDGE_RISING>;
2695                                 mboxes = <&ipcc IPCC_CLIENT_SLPI
2696                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2697
2698                                 label = "slpi";
2699                                 qcom,remote-pid = <3>;
2700
2701                                 fastrpc {
2702                                         compatible = "qcom,fastrpc";
2703                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2704                                         label = "sdsp";
2705                                         qcom,non-secure-domain;
2706                                         #address-cells = <1>;
2707                                         #size-cells = <0>;
2708
2709                                         compute-cb@1 {
2710                                                 compatible = "qcom,fastrpc-compute-cb";
2711                                                 reg = <1>;
2712                                                 iommus = <&apps_smmu 0x0541 0x0>;
2713                                         };
2714
2715                                         compute-cb@2 {
2716                                                 compatible = "qcom,fastrpc-compute-cb";
2717                                                 reg = <2>;
2718                                                 iommus = <&apps_smmu 0x0542 0x0>;
2719                                         };
2720
2721                                         compute-cb@3 {
2722                                                 compatible = "qcom,fastrpc-compute-cb";
2723                                                 reg = <3>;
2724                                                 iommus = <&apps_smmu 0x0543 0x0>;
2725                                                 /* note: shared-cb = <4> in downstream */
2726                                         };
2727                                 };
2728                         };
2729                 };
2730
2731                 stm@6002000 {
2732                         compatible = "arm,coresight-stm", "arm,primecell";
2733                         reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>;
2734                         reg-names = "stm-base", "stm-stimulus-base";
2735
2736                         clocks = <&aoss_qmp>;
2737                         clock-names = "apb_pclk";
2738
2739                         out-ports {
2740                                 port {
2741                                         stm_out: endpoint {
2742                                                 remote-endpoint = <&funnel0_in7>;
2743                                         };
2744                                 };
2745                         };
2746                 };
2747
2748                 funnel@6041000 {
2749                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2750                         reg = <0 0x06041000 0 0x1000>;
2751
2752                         clocks = <&aoss_qmp>;
2753                         clock-names = "apb_pclk";
2754
2755                         out-ports {
2756                                 port {
2757                                         funnel_in0_out_funnel_merg: endpoint {
2758                                                 remote-endpoint = <&funnel_merg_in_funnel_in0>;
2759                                         };
2760                                 };
2761                         };
2762
2763                         in-ports {
2764                                 #address-cells = <1>;
2765                                 #size-cells = <0>;
2766
2767                                 port@7 {
2768                                         reg = <7>;
2769                                         funnel0_in7: endpoint {
2770                                                 remote-endpoint = <&stm_out>;
2771                                         };
2772                                 };
2773                         };
2774                 };
2775
2776                 funnel@6042000 {
2777                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2778                         reg = <0 0x06042000 0 0x1000>;
2779
2780                         clocks = <&aoss_qmp>;
2781                         clock-names = "apb_pclk";
2782
2783                         out-ports {
2784                                 #address-cells = <1>;
2785                                 #size-cells = <0>;
2786
2787                                 port@0 {
2788                                         reg = <0>;
2789                                         funnel_in1_out_funnel_merg: endpoint {
2790                                                 remote-endpoint = <&funnel_merg_in_funnel_in1>;
2791                                         };
2792                                 };
2793                         };
2794
2795                         in-ports {
2796                                 #address-cells = <1>;
2797                                 #size-cells = <0>;
2798
2799                                 port@4 {
2800                                         reg = <4>;
2801                                         funnel_in1_in_funnel_apss_merg: endpoint {
2802                                         remote-endpoint = <&funnel_apss_merg_out_funnel_in1>;
2803                                         };
2804                                 };
2805                         };
2806                 };
2807
2808                 funnel@6045000 {
2809                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2810                         reg = <0 0x06045000 0 0x1000>;
2811
2812                         clocks = <&aoss_qmp>;
2813                         clock-names = "apb_pclk";
2814
2815                         out-ports {
2816                                 port {
2817                                         funnel_merg_out_funnel_swao: endpoint {
2818                                         remote-endpoint = <&funnel_swao_in_funnel_merg>;
2819                                         };
2820                                 };
2821                         };
2822
2823                         in-ports {
2824                                 #address-cells = <1>;
2825                                 #size-cells = <0>;
2826
2827                                 port@0 {
2828                                         reg = <0>;
2829                                         funnel_merg_in_funnel_in0: endpoint {
2830                                         remote-endpoint = <&funnel_in0_out_funnel_merg>;
2831                                         };
2832                                 };
2833
2834                                 port@1 {
2835                                         reg = <1>;
2836                                         funnel_merg_in_funnel_in1: endpoint {
2837                                         remote-endpoint = <&funnel_in1_out_funnel_merg>;
2838                                         };
2839                                 };
2840                         };
2841                 };
2842
2843                 replicator@6046000 {
2844                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2845                         reg = <0 0x06046000 0 0x1000>;
2846
2847                         clocks = <&aoss_qmp>;
2848                         clock-names = "apb_pclk";
2849
2850                         out-ports {
2851                                 port {
2852                                         replicator_out: endpoint {
2853                                                 remote-endpoint = <&etr_in>;
2854                                         };
2855                                 };
2856                         };
2857
2858                         in-ports {
2859                                 port {
2860                                         replicator_cx_in_swao_out: endpoint {
2861                                                 remote-endpoint = <&replicator_swao_out_cx_in>;
2862                                         };
2863                                 };
2864                         };
2865                 };
2866
2867                 etr@6048000 {
2868                         compatible = "arm,coresight-tmc", "arm,primecell";
2869                         reg = <0 0x06048000 0 0x1000>;
2870
2871                         clocks = <&aoss_qmp>;
2872                         clock-names = "apb_pclk";
2873                         arm,scatter-gather;
2874
2875                         in-ports {
2876                                 port {
2877                                         etr_in: endpoint {
2878                                                 remote-endpoint = <&replicator_out>;
2879                                         };
2880                                 };
2881                         };
2882                 };
2883
2884                 funnel@6b04000 {
2885                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2886                         arm,primecell-periphid = <0x000bb908>;
2887
2888                         reg = <0 0x06b04000 0 0x1000>;
2889                         reg-names = "funnel-base";
2890
2891                         clocks = <&aoss_qmp>;
2892                         clock-names = "apb_pclk";
2893
2894                         out-ports {
2895                                 port {
2896                                         funnel_swao_out_etf: endpoint {
2897                                                 remote-endpoint = <&etf_in_funnel_swao_out>;
2898                                         };
2899                                 };
2900                         };
2901
2902                         in-ports {
2903                                 #address-cells = <1>;
2904                                 #size-cells = <0>;
2905
2906                                 port@7 {
2907                                         reg = <7>;
2908                                         funnel_swao_in_funnel_merg: endpoint {
2909                                                 remote-endpoint= <&funnel_merg_out_funnel_swao>;
2910                                         };
2911                                 };
2912                         };
2913
2914                 };
2915
2916                 etf@6b05000 {
2917                         compatible = "arm,coresight-tmc", "arm,primecell";
2918                         reg = <0 0x06b05000 0 0x1000>;
2919
2920                         clocks = <&aoss_qmp>;
2921                         clock-names = "apb_pclk";
2922
2923                         out-ports {
2924                                 port {
2925                                         etf_out: endpoint {
2926                                                 remote-endpoint = <&replicator_in>;
2927                                         };
2928                                 };
2929                         };
2930
2931                         in-ports {
2932                                 #address-cells = <1>;
2933                                 #size-cells = <0>;
2934
2935                                 port@0 {
2936                                         reg = <0>;
2937                                         etf_in_funnel_swao_out: endpoint {
2938                                                 remote-endpoint = <&funnel_swao_out_etf>;
2939                                         };
2940                                 };
2941                         };
2942                 };
2943
2944                 replicator@6b06000 {
2945                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2946                         reg = <0 0x06b06000 0 0x1000>;
2947
2948                         clocks = <&aoss_qmp>;
2949                         clock-names = "apb_pclk";
2950
2951                         out-ports {
2952                                 port {
2953                                         replicator_swao_out_cx_in: endpoint {
2954                                                 remote-endpoint = <&replicator_cx_in_swao_out>;
2955                                         };
2956                                 };
2957                         };
2958
2959                         in-ports {
2960                                 port {
2961                                         replicator_in: endpoint {
2962                                                 remote-endpoint = <&etf_out>;
2963                                         };
2964                                 };
2965                         };
2966                 };
2967
2968                 etm@7040000 {
2969                         compatible = "arm,coresight-etm4x", "arm,primecell";
2970                         reg = <0 0x07040000 0 0x1000>;
2971
2972                         cpu = <&CPU0>;
2973
2974                         clocks = <&aoss_qmp>;
2975                         clock-names = "apb_pclk";
2976                         arm,coresight-loses-context-with-cpu;
2977
2978                         out-ports {
2979                                 port {
2980                                         etm0_out: endpoint {
2981                                                 remote-endpoint = <&apss_funnel_in0>;
2982                                         };
2983                                 };
2984                         };
2985                 };
2986
2987                 etm@7140000 {
2988                         compatible = "arm,coresight-etm4x", "arm,primecell";
2989                         reg = <0 0x07140000 0 0x1000>;
2990
2991                         cpu = <&CPU1>;
2992
2993                         clocks = <&aoss_qmp>;
2994                         clock-names = "apb_pclk";
2995                         arm,coresight-loses-context-with-cpu;
2996
2997                         out-ports {
2998                                 port {
2999                                         etm1_out: endpoint {
3000                                                 remote-endpoint = <&apss_funnel_in1>;
3001                                         };
3002                                 };
3003                         };
3004                 };
3005
3006                 etm@7240000 {
3007                         compatible = "arm,coresight-etm4x", "arm,primecell";
3008                         reg = <0 0x07240000 0 0x1000>;
3009
3010                         cpu = <&CPU2>;
3011
3012                         clocks = <&aoss_qmp>;
3013                         clock-names = "apb_pclk";
3014                         arm,coresight-loses-context-with-cpu;
3015
3016                         out-ports {
3017                                 port {
3018                                         etm2_out: endpoint {
3019                                                 remote-endpoint = <&apss_funnel_in2>;
3020                                         };
3021                                 };
3022                         };
3023                 };
3024
3025                 etm@7340000 {
3026                         compatible = "arm,coresight-etm4x", "arm,primecell";
3027                         reg = <0 0x07340000 0 0x1000>;
3028
3029                         cpu = <&CPU3>;
3030
3031                         clocks = <&aoss_qmp>;
3032                         clock-names = "apb_pclk";
3033                         arm,coresight-loses-context-with-cpu;
3034
3035                         out-ports {
3036                                 port {
3037                                         etm3_out: endpoint {
3038                                                 remote-endpoint = <&apss_funnel_in3>;
3039                                         };
3040                                 };
3041                         };
3042                 };
3043
3044                 etm@7440000 {
3045                         compatible = "arm,coresight-etm4x", "arm,primecell";
3046                         reg = <0 0x07440000 0 0x1000>;
3047
3048                         cpu = <&CPU4>;
3049
3050                         clocks = <&aoss_qmp>;
3051                         clock-names = "apb_pclk";
3052                         arm,coresight-loses-context-with-cpu;
3053
3054                         out-ports {
3055                                 port {
3056                                         etm4_out: endpoint {
3057                                                 remote-endpoint = <&apss_funnel_in4>;
3058                                         };
3059                                 };
3060                         };
3061                 };
3062
3063                 etm@7540000 {
3064                         compatible = "arm,coresight-etm4x", "arm,primecell";
3065                         reg = <0 0x07540000 0 0x1000>;
3066
3067                         cpu = <&CPU5>;
3068
3069                         clocks = <&aoss_qmp>;
3070                         clock-names = "apb_pclk";
3071                         arm,coresight-loses-context-with-cpu;
3072
3073                         out-ports {
3074                                 port {
3075                                         etm5_out: endpoint {
3076                                                 remote-endpoint = <&apss_funnel_in5>;
3077                                         };
3078                                 };
3079                         };
3080                 };
3081
3082                 etm@7640000 {
3083                         compatible = "arm,coresight-etm4x", "arm,primecell";
3084                         reg = <0 0x07640000 0 0x1000>;
3085
3086                         cpu = <&CPU6>;
3087
3088                         clocks = <&aoss_qmp>;
3089                         clock-names = "apb_pclk";
3090                         arm,coresight-loses-context-with-cpu;
3091
3092                         out-ports {
3093                                 port {
3094                                         etm6_out: endpoint {
3095                                                 remote-endpoint = <&apss_funnel_in6>;
3096                                         };
3097                                 };
3098                         };
3099                 };
3100
3101                 etm@7740000 {
3102                         compatible = "arm,coresight-etm4x", "arm,primecell";
3103                         reg = <0 0x07740000 0 0x1000>;
3104
3105                         cpu = <&CPU7>;
3106
3107                         clocks = <&aoss_qmp>;
3108                         clock-names = "apb_pclk";
3109                         arm,coresight-loses-context-with-cpu;
3110
3111                         out-ports {
3112                                 port {
3113                                         etm7_out: endpoint {
3114                                                 remote-endpoint = <&apss_funnel_in7>;
3115                                         };
3116                                 };
3117                         };
3118                 };
3119
3120                 funnel@7800000 {
3121                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3122                         reg = <0 0x07800000 0 0x1000>;
3123
3124                         clocks = <&aoss_qmp>;
3125                         clock-names = "apb_pclk";
3126
3127                         out-ports {
3128                                 port {
3129                                         funnel_apss_out_funnel_apss_merg: endpoint {
3130                                         remote-endpoint = <&funnel_apss_merg_in_funnel_apss>;
3131                                         };
3132                                 };
3133                         };
3134
3135                         in-ports {
3136                                 #address-cells = <1>;
3137                                 #size-cells = <0>;
3138
3139                                 port@0 {
3140                                         reg = <0>;
3141                                         apss_funnel_in0: endpoint {
3142                                                 remote-endpoint = <&etm0_out>;
3143                                         };
3144                                 };
3145
3146                                 port@1 {
3147                                         reg = <1>;
3148                                         apss_funnel_in1: endpoint {
3149                                                 remote-endpoint = <&etm1_out>;
3150                                         };
3151                                 };
3152
3153                                 port@2 {
3154                                         reg = <2>;
3155                                         apss_funnel_in2: endpoint {
3156                                                 remote-endpoint = <&etm2_out>;
3157                                         };
3158                                 };
3159
3160                                 port@3 {
3161                                         reg = <3>;
3162                                         apss_funnel_in3: endpoint {
3163                                                 remote-endpoint = <&etm3_out>;
3164                                         };
3165                                 };
3166
3167                                 port@4 {
3168                                         reg = <4>;
3169                                         apss_funnel_in4: endpoint {
3170                                                 remote-endpoint = <&etm4_out>;
3171                                         };
3172                                 };
3173
3174                                 port@5 {
3175                                         reg = <5>;
3176                                         apss_funnel_in5: endpoint {
3177                                                 remote-endpoint = <&etm5_out>;
3178                                         };
3179                                 };
3180
3181                                 port@6 {
3182                                         reg = <6>;
3183                                         apss_funnel_in6: endpoint {
3184                                                 remote-endpoint = <&etm6_out>;
3185                                         };
3186                                 };
3187
3188                                 port@7 {
3189                                         reg = <7>;
3190                                         apss_funnel_in7: endpoint {
3191                                                 remote-endpoint = <&etm7_out>;
3192                                         };
3193                                 };
3194                         };
3195                 };
3196
3197                 funnel@7810000 {
3198                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3199                         reg = <0 0x07810000 0 0x1000>;
3200
3201                         clocks = <&aoss_qmp>;
3202                         clock-names = "apb_pclk";
3203
3204                         out-ports {
3205                                 #address-cells = <1>;
3206                                 #size-cells = <0>;
3207
3208                                 port {
3209                                         funnel_apss_merg_out_funnel_in1: endpoint {
3210                                         remote-endpoint = <&funnel_in1_in_funnel_apss_merg>;
3211                                         };
3212                                 };
3213                         };
3214
3215                         in-ports {
3216                                 #address-cells = <1>;
3217                                 #size-cells = <0>;
3218
3219                                 port@0 {
3220                                         reg = <0>;
3221                                         funnel_apss_merg_in_funnel_apss: endpoint {
3222                                         remote-endpoint = <&funnel_apss_out_funnel_apss_merg>;
3223                                         };
3224                                 };
3225                         };
3226                 };
3227
3228                 cdsp: remoteproc@8300000 {
3229                         compatible = "qcom,sm8250-cdsp-pas";
3230                         reg = <0 0x08300000 0 0x10000>;
3231
3232                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3233                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3234                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3235                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3236                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3237                         interrupt-names = "wdog", "fatal", "ready",
3238                                           "handover", "stop-ack";
3239
3240                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3241                         clock-names = "xo";
3242
3243                         power-domains = <&rpmhpd SM8250_CX>;
3244
3245                         memory-region = <&cdsp_mem>;
3246
3247                         qcom,qmp = <&aoss_qmp>;
3248
3249                         qcom,smem-states = <&smp2p_cdsp_out 0>;
3250                         qcom,smem-state-names = "stop";
3251
3252                         status = "disabled";
3253
3254                         glink-edge {
3255                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3256                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
3257                                                              IRQ_TYPE_EDGE_RISING>;
3258                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
3259                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3260
3261                                 label = "cdsp";
3262                                 qcom,remote-pid = <5>;
3263
3264                                 fastrpc {
3265                                         compatible = "qcom,fastrpc";
3266                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
3267                                         label = "cdsp";
3268                                         qcom,non-secure-domain;
3269                                         #address-cells = <1>;
3270                                         #size-cells = <0>;
3271
3272                                         compute-cb@1 {
3273                                                 compatible = "qcom,fastrpc-compute-cb";
3274                                                 reg = <1>;
3275                                                 iommus = <&apps_smmu 0x1001 0x0460>;
3276                                         };
3277
3278                                         compute-cb@2 {
3279                                                 compatible = "qcom,fastrpc-compute-cb";
3280                                                 reg = <2>;
3281                                                 iommus = <&apps_smmu 0x1002 0x0460>;
3282                                         };
3283
3284                                         compute-cb@3 {
3285                                                 compatible = "qcom,fastrpc-compute-cb";
3286                                                 reg = <3>;
3287                                                 iommus = <&apps_smmu 0x1003 0x0460>;
3288                                         };
3289
3290                                         compute-cb@4 {
3291                                                 compatible = "qcom,fastrpc-compute-cb";
3292                                                 reg = <4>;
3293                                                 iommus = <&apps_smmu 0x1004 0x0460>;
3294                                         };
3295
3296                                         compute-cb@5 {
3297                                                 compatible = "qcom,fastrpc-compute-cb";
3298                                                 reg = <5>;
3299                                                 iommus = <&apps_smmu 0x1005 0x0460>;
3300                                         };
3301
3302                                         compute-cb@6 {
3303                                                 compatible = "qcom,fastrpc-compute-cb";
3304                                                 reg = <6>;
3305                                                 iommus = <&apps_smmu 0x1006 0x0460>;
3306                                         };
3307
3308                                         compute-cb@7 {
3309                                                 compatible = "qcom,fastrpc-compute-cb";
3310                                                 reg = <7>;
3311                                                 iommus = <&apps_smmu 0x1007 0x0460>;
3312                                         };
3313
3314                                         compute-cb@8 {
3315                                                 compatible = "qcom,fastrpc-compute-cb";
3316                                                 reg = <8>;
3317                                                 iommus = <&apps_smmu 0x1008 0x0460>;
3318                                         };
3319
3320                                         /* note: secure cb9 in downstream */
3321                                 };
3322                         };
3323                 };
3324
3325                 sound: sound {
3326                 };
3327
3328                 usb_1_hsphy: phy@88e3000 {
3329                         compatible = "qcom,sm8250-usb-hs-phy",
3330                                      "qcom,usb-snps-hs-7nm-phy";
3331                         reg = <0 0x088e3000 0 0x400>;
3332                         status = "disabled";
3333                         #phy-cells = <0>;
3334
3335                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3336                         clock-names = "ref";
3337
3338                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3339                 };
3340
3341                 usb_2_hsphy: phy@88e4000 {
3342                         compatible = "qcom,sm8250-usb-hs-phy",
3343                                      "qcom,usb-snps-hs-7nm-phy";
3344                         reg = <0 0x088e4000 0 0x400>;
3345                         status = "disabled";
3346                         #phy-cells = <0>;
3347
3348                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3349                         clock-names = "ref";
3350
3351                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3352                 };
3353
3354                 usb_1_qmpphy: phy@88e9000 {
3355                         compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3356                         reg = <0 0x088e9000 0 0x200>,
3357                               <0 0x088e8000 0 0x40>,
3358                               <0 0x088ea000 0 0x200>;
3359                         status = "disabled";
3360                         #address-cells = <2>;
3361                         #size-cells = <2>;
3362                         ranges;
3363
3364                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3365                                  <&rpmhcc RPMH_CXO_CLK>,
3366                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3367                         clock-names = "aux", "ref_clk_src", "com_aux";
3368
3369                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3370                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
3371                         reset-names = "phy", "common";
3372
3373                         usb_1_ssphy: usb3-phy@88e9200 {
3374                                 reg = <0 0x088e9200 0 0x200>,
3375                                       <0 0x088e9400 0 0x200>,
3376                                       <0 0x088e9c00 0 0x400>,
3377                                       <0 0x088e9600 0 0x200>,
3378                                       <0 0x088e9800 0 0x200>,
3379                                       <0 0x088e9a00 0 0x100>;
3380                                 #clock-cells = <0>;
3381                                 #phy-cells = <0>;
3382                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3383                                 clock-names = "pipe0";
3384                                 clock-output-names = "usb3_phy_pipe_clk_src";
3385                         };
3386
3387                         dp_phy: dp-phy@88ea200 {
3388                                 reg = <0 0x088ea200 0 0x200>,
3389                                       <0 0x088ea400 0 0x200>,
3390                                       <0 0x088eaa00 0 0x200>,
3391                                       <0 0x088ea600 0 0x200>,
3392                                       <0 0x088ea800 0 0x200>;
3393                                 #phy-cells = <0>;
3394                                 #clock-cells = <1>;
3395                         };
3396                 };
3397
3398                 usb_2_qmpphy: phy@88eb000 {
3399                         compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3400                         reg = <0 0x088eb000 0 0x200>;
3401                         status = "disabled";
3402                         #address-cells = <2>;
3403                         #size-cells = <2>;
3404                         ranges;
3405
3406                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3407                                  <&rpmhcc RPMH_CXO_CLK>,
3408                                  <&gcc GCC_USB3_SEC_CLKREF_EN>,
3409                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3410                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3411
3412                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3413                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
3414                         reset-names = "phy", "common";
3415
3416                         usb_2_ssphy: phy@88eb200 {
3417                                 reg = <0 0x088eb200 0 0x200>,
3418                                       <0 0x088eb400 0 0x200>,
3419                                       <0 0x088eb800 0 0x800>;
3420                                 #clock-cells = <0>;
3421                                 #phy-cells = <0>;
3422                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3423                                 clock-names = "pipe0";
3424                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3425                         };
3426                 };
3427
3428                 sdhc_2: mmc@8804000 {
3429                         compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3430                         reg = <0 0x08804000 0 0x1000>;
3431
3432                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3433                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3434                         interrupt-names = "hc_irq", "pwr_irq";
3435
3436                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3437                                  <&gcc GCC_SDCC2_APPS_CLK>,
3438                                  <&rpmhcc RPMH_CXO_CLK>;
3439                         clock-names = "iface", "core", "xo";
3440                         iommus = <&apps_smmu 0x4a0 0x0>;
3441                         qcom,dll-config = <0x0007642c>;
3442                         qcom,ddr-config = <0x80040868>;
3443                         power-domains = <&rpmhpd SM8250_CX>;
3444                         operating-points-v2 = <&sdhc2_opp_table>;
3445
3446                         status = "disabled";
3447
3448                         sdhc2_opp_table: opp-table {
3449                                 compatible = "operating-points-v2";
3450
3451                                 opp-19200000 {
3452                                         opp-hz = /bits/ 64 <19200000>;
3453                                         required-opps = <&rpmhpd_opp_min_svs>;
3454                                 };
3455
3456                                 opp-50000000 {
3457                                         opp-hz = /bits/ 64 <50000000>;
3458                                         required-opps = <&rpmhpd_opp_low_svs>;
3459                                 };
3460
3461                                 opp-100000000 {
3462                                         opp-hz = /bits/ 64 <100000000>;
3463                                         required-opps = <&rpmhpd_opp_svs>;
3464                                 };
3465
3466                                 opp-202000000 {
3467                                         opp-hz = /bits/ 64 <202000000>;
3468                                         required-opps = <&rpmhpd_opp_svs_l1>;
3469                                 };
3470                         };
3471                 };
3472
3473                 dc_noc: interconnect@90c0000 {
3474                         compatible = "qcom,sm8250-dc-noc";
3475                         reg = <0 0x090c0000 0 0x4200>;
3476                         #interconnect-cells = <1>;
3477                         qcom,bcm-voters = <&apps_bcm_voter>;
3478                 };
3479
3480                 gem_noc: interconnect@9100000 {
3481                         compatible = "qcom,sm8250-gem-noc";
3482                         reg = <0 0x09100000 0 0xb4000>;
3483                         #interconnect-cells = <1>;
3484                         qcom,bcm-voters = <&apps_bcm_voter>;
3485                 };
3486
3487                 npu_noc: interconnect@9990000 {
3488                         compatible = "qcom,sm8250-npu-noc";
3489                         reg = <0 0x09990000 0 0x1600>;
3490                         #interconnect-cells = <1>;
3491                         qcom,bcm-voters = <&apps_bcm_voter>;
3492                 };
3493
3494                 usb_1: usb@a6f8800 {
3495                         compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
3496                         reg = <0 0x0a6f8800 0 0x400>;
3497                         status = "disabled";
3498                         #address-cells = <2>;
3499                         #size-cells = <2>;
3500                         ranges;
3501                         dma-ranges;
3502
3503                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3504                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3505                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3506                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3507                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3508                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
3509                         clock-names = "cfg_noc",
3510                                       "core",
3511                                       "iface",
3512                                       "sleep",
3513                                       "mock_utmi",
3514                                       "xo";
3515
3516                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3517                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3518                         assigned-clock-rates = <19200000>, <200000000>;
3519
3520                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3521                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
3522                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3523                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
3524                         interrupt-names = "hs_phy_irq",
3525                                           "ss_phy_irq",
3526                                           "dm_hs_phy_irq",
3527                                           "dp_hs_phy_irq";
3528
3529                         power-domains = <&gcc USB30_PRIM_GDSC>;
3530
3531                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3532
3533                         usb_1_dwc3: usb@a600000 {
3534                                 compatible = "snps,dwc3";
3535                                 reg = <0 0x0a600000 0 0xcd00>;
3536                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3537                                 iommus = <&apps_smmu 0x0 0x0>;
3538                                 snps,dis_u2_susphy_quirk;
3539                                 snps,dis_enblslpm_quirk;
3540                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3541                                 phy-names = "usb2-phy", "usb3-phy";
3542                         };
3543                 };
3544
3545                 system-cache-controller@9200000 {
3546                         compatible = "qcom,sm8250-llcc";
3547                         reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
3548                         reg-names = "llcc_base", "llcc_broadcast_base";
3549                 };
3550
3551                 usb_2: usb@a8f8800 {
3552                         compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
3553                         reg = <0 0x0a8f8800 0 0x400>;
3554                         status = "disabled";
3555                         #address-cells = <2>;
3556                         #size-cells = <2>;
3557                         ranges;
3558                         dma-ranges;
3559
3560                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3561                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
3562                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3563                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3564                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3565                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
3566                         clock-names = "cfg_noc",
3567                                       "core",
3568                                       "iface",
3569                                       "sleep",
3570                                       "mock_utmi",
3571                                       "xo";
3572
3573                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3574                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
3575                         assigned-clock-rates = <19200000>, <200000000>;
3576
3577                         interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3578                                               <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
3579                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
3580                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
3581                         interrupt-names = "hs_phy_irq",
3582                                           "ss_phy_irq",
3583                                           "dm_hs_phy_irq",
3584                                           "dp_hs_phy_irq";
3585
3586                         power-domains = <&gcc USB30_SEC_GDSC>;
3587
3588                         resets = <&gcc GCC_USB30_SEC_BCR>;
3589
3590                         usb_2_dwc3: usb@a800000 {
3591                                 compatible = "snps,dwc3";
3592                                 reg = <0 0x0a800000 0 0xcd00>;
3593                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3594                                 iommus = <&apps_smmu 0x20 0>;
3595                                 snps,dis_u2_susphy_quirk;
3596                                 snps,dis_enblslpm_quirk;
3597                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3598                                 phy-names = "usb2-phy", "usb3-phy";
3599                         };
3600                 };
3601
3602                 venus: video-codec@aa00000 {
3603                         compatible = "qcom,sm8250-venus";
3604                         reg = <0 0x0aa00000 0 0x100000>;
3605                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3606                         power-domains = <&videocc MVS0C_GDSC>,
3607                                         <&videocc MVS0_GDSC>,
3608                                         <&rpmhpd SM8250_MX>;
3609                         power-domain-names = "venus", "vcodec0", "mx";
3610                         operating-points-v2 = <&venus_opp_table>;
3611
3612                         clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
3613                                  <&videocc VIDEO_CC_MVS0C_CLK>,
3614                                  <&videocc VIDEO_CC_MVS0_CLK>;
3615                         clock-names = "iface", "core", "vcodec0_core";
3616
3617                         interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>,
3618                                         <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>;
3619                         interconnect-names = "cpu-cfg", "video-mem";
3620
3621                         iommus = <&apps_smmu 0x2100 0x0400>;
3622                         memory-region = <&video_mem>;
3623
3624                         resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
3625                                  <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
3626                         reset-names = "bus", "core";
3627
3628                         status = "disabled";
3629
3630                         video-decoder {
3631                                 compatible = "venus-decoder";
3632                         };
3633
3634                         video-encoder {
3635                                 compatible = "venus-encoder";
3636                         };
3637
3638                         venus_opp_table: opp-table {
3639                                 compatible = "operating-points-v2";
3640
3641                                 opp-720000000 {
3642                                         opp-hz = /bits/ 64 <720000000>;
3643                                         required-opps = <&rpmhpd_opp_low_svs>;
3644                                 };
3645
3646                                 opp-1014000000 {
3647                                         opp-hz = /bits/ 64 <1014000000>;
3648                                         required-opps = <&rpmhpd_opp_svs>;
3649                                 };
3650
3651                                 opp-1098000000 {
3652                                         opp-hz = /bits/ 64 <1098000000>;
3653                                         required-opps = <&rpmhpd_opp_svs_l1>;
3654                                 };
3655
3656                                 opp-1332000000 {
3657                                         opp-hz = /bits/ 64 <1332000000>;
3658                                         required-opps = <&rpmhpd_opp_nom>;
3659                                 };
3660                         };
3661                 };
3662
3663                 videocc: clock-controller@abf0000 {
3664                         compatible = "qcom,sm8250-videocc";
3665                         reg = <0 0x0abf0000 0 0x10000>;
3666                         clocks = <&gcc GCC_VIDEO_AHB_CLK>,
3667                                  <&rpmhcc RPMH_CXO_CLK>,
3668                                  <&rpmhcc RPMH_CXO_CLK_A>;
3669                         power-domains = <&rpmhpd SM8250_MMCX>;
3670                         required-opps = <&rpmhpd_opp_low_svs>;
3671                         clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
3672                         #clock-cells = <1>;
3673                         #reset-cells = <1>;
3674                         #power-domain-cells = <1>;
3675                 };
3676
3677                 cci0: cci@ac4f000 {
3678                         compatible = "qcom,sm8250-cci";
3679                         #address-cells = <1>;
3680                         #size-cells = <0>;
3681
3682                         reg = <0 0x0ac4f000 0 0x1000>;
3683                         interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
3684                         power-domains = <&camcc TITAN_TOP_GDSC>;
3685
3686                         clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3687                                  <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3688                                  <&camcc CAM_CC_CPAS_AHB_CLK>,
3689                                  <&camcc CAM_CC_CCI_0_CLK>,
3690                                  <&camcc CAM_CC_CCI_0_CLK_SRC>;
3691                         clock-names = "camnoc_axi",
3692                                       "slow_ahb_src",
3693                                       "cpas_ahb",
3694                                       "cci",
3695                                       "cci_src";
3696
3697                         pinctrl-0 = <&cci0_default>;
3698                         pinctrl-1 = <&cci0_sleep>;
3699                         pinctrl-names = "default", "sleep";
3700
3701                         status = "disabled";
3702
3703                         cci0_i2c0: i2c-bus@0 {
3704                                 reg = <0>;
3705                                 clock-frequency = <1000000>;
3706                                 #address-cells = <1>;
3707                                 #size-cells = <0>;
3708                         };
3709
3710                         cci0_i2c1: i2c-bus@1 {
3711                                 reg = <1>;
3712                                 clock-frequency = <1000000>;
3713                                 #address-cells = <1>;
3714                                 #size-cells = <0>;
3715                         };
3716                 };
3717
3718                 cci1: cci@ac50000 {
3719                         compatible = "qcom,sm8250-cci";
3720                         #address-cells = <1>;
3721                         #size-cells = <0>;
3722
3723                         reg = <0 0x0ac50000 0 0x1000>;
3724                         interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
3725                         power-domains = <&camcc TITAN_TOP_GDSC>;
3726
3727                         clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3728                                  <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3729                                  <&camcc CAM_CC_CPAS_AHB_CLK>,
3730                                  <&camcc CAM_CC_CCI_1_CLK>,
3731                                  <&camcc CAM_CC_CCI_1_CLK_SRC>;
3732                         clock-names = "camnoc_axi",
3733                                       "slow_ahb_src",
3734                                       "cpas_ahb",
3735                                       "cci",
3736                                       "cci_src";
3737
3738                         pinctrl-0 = <&cci1_default>;
3739                         pinctrl-1 = <&cci1_sleep>;
3740                         pinctrl-names = "default", "sleep";
3741
3742                         status = "disabled";
3743
3744                         cci1_i2c0: i2c-bus@0 {
3745                                 reg = <0>;
3746                                 clock-frequency = <1000000>;
3747                                 #address-cells = <1>;
3748                                 #size-cells = <0>;
3749                         };
3750
3751                         cci1_i2c1: i2c-bus@1 {
3752                                 reg = <1>;
3753                                 clock-frequency = <1000000>;
3754                                 #address-cells = <1>;
3755                                 #size-cells = <0>;
3756                         };
3757                 };
3758
3759                 camss: camss@ac6a000 {
3760                         compatible = "qcom,sm8250-camss";
3761                         status = "disabled";
3762
3763                         reg = <0 0xac6a000 0 0x2000>,
3764                               <0 0xac6c000 0 0x2000>,
3765                               <0 0xac6e000 0 0x1000>,
3766                               <0 0xac70000 0 0x1000>,
3767                               <0 0xac72000 0 0x1000>,
3768                               <0 0xac74000 0 0x1000>,
3769                               <0 0xacb4000 0 0xd000>,
3770                               <0 0xacc3000 0 0xd000>,
3771                               <0 0xacd9000 0 0x2200>,
3772                               <0 0xacdb200 0 0x2200>;
3773                         reg-names = "csiphy0",
3774                                     "csiphy1",
3775                                     "csiphy2",
3776                                     "csiphy3",
3777                                     "csiphy4",
3778                                     "csiphy5",
3779                                     "vfe0",
3780                                     "vfe1",
3781                                     "vfe_lite0",
3782                                     "vfe_lite1";
3783
3784                         interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
3785                                      <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
3786                                      <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
3787                                      <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
3788                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
3789                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
3790                                      <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
3791                                      <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
3792                                      <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
3793                                      <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
3794                                      <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
3795                                      <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
3796                                      <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
3797                                      <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
3798                         interrupt-names = "csiphy0",
3799                                           "csiphy1",
3800                                           "csiphy2",
3801                                           "csiphy3",
3802                                           "csiphy4",
3803                                           "csiphy5",
3804                                           "csid0",
3805                                           "csid1",
3806                                           "csid2",
3807                                           "csid3",
3808                                           "vfe0",
3809                                           "vfe1",
3810                                           "vfe_lite0",
3811                                           "vfe_lite1";
3812
3813                         power-domains = <&camcc IFE_0_GDSC>,
3814                                         <&camcc IFE_1_GDSC>,
3815                                         <&camcc TITAN_TOP_GDSC>;
3816
3817                         clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3818                                  <&gcc GCC_CAMERA_HF_AXI_CLK>,
3819                                  <&gcc GCC_CAMERA_SF_AXI_CLK>,
3820                                  <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3821                                  <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
3822                                  <&camcc CAM_CC_CORE_AHB_CLK>,
3823                                  <&camcc CAM_CC_CPAS_AHB_CLK>,
3824                                  <&camcc CAM_CC_CSIPHY0_CLK>,
3825                                  <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
3826                                  <&camcc CAM_CC_CSIPHY1_CLK>,
3827                                  <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
3828                                  <&camcc CAM_CC_CSIPHY2_CLK>,
3829                                  <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
3830                                  <&camcc CAM_CC_CSIPHY3_CLK>,
3831                                  <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
3832                                  <&camcc CAM_CC_CSIPHY4_CLK>,
3833                                  <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
3834                                  <&camcc CAM_CC_CSIPHY5_CLK>,
3835                                  <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
3836                                  <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3837                                  <&camcc CAM_CC_IFE_0_AHB_CLK>,
3838                                  <&camcc CAM_CC_IFE_0_AXI_CLK>,
3839                                  <&camcc CAM_CC_IFE_0_CLK>,
3840                                  <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
3841                                  <&camcc CAM_CC_IFE_0_CSID_CLK>,
3842                                  <&camcc CAM_CC_IFE_0_AREG_CLK>,
3843                                  <&camcc CAM_CC_IFE_1_AHB_CLK>,
3844                                  <&camcc CAM_CC_IFE_1_AXI_CLK>,
3845                                  <&camcc CAM_CC_IFE_1_CLK>,
3846                                  <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
3847                                  <&camcc CAM_CC_IFE_1_CSID_CLK>,
3848                                  <&camcc CAM_CC_IFE_1_AREG_CLK>,
3849                                  <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
3850                                  <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
3851                                  <&camcc CAM_CC_IFE_LITE_CLK>,
3852                                  <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
3853                                  <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
3854
3855                         clock-names = "cam_ahb_clk",
3856                                       "cam_hf_axi",
3857                                       "cam_sf_axi",
3858                                       "camnoc_axi",
3859                                       "camnoc_axi_src",
3860                                       "core_ahb",
3861                                       "cpas_ahb",
3862                                       "csiphy0",
3863                                       "csiphy0_timer",
3864                                       "csiphy1",
3865                                       "csiphy1_timer",
3866                                       "csiphy2",
3867                                       "csiphy2_timer",
3868                                       "csiphy3",
3869                                       "csiphy3_timer",
3870                                       "csiphy4",
3871                                       "csiphy4_timer",
3872                                       "csiphy5",
3873                                       "csiphy5_timer",
3874                                       "slow_ahb_src",
3875                                       "vfe0_ahb",
3876                                       "vfe0_axi",
3877                                       "vfe0",
3878                                       "vfe0_cphy_rx",
3879                                       "vfe0_csid",
3880                                       "vfe0_areg",
3881                                       "vfe1_ahb",
3882                                       "vfe1_axi",
3883                                       "vfe1",
3884                                       "vfe1_cphy_rx",
3885                                       "vfe1_csid",
3886                                       "vfe1_areg",
3887                                       "vfe_lite_ahb",
3888                                       "vfe_lite_axi",
3889                                       "vfe_lite",
3890                                       "vfe_lite_cphy_rx",
3891                                       "vfe_lite_csid";
3892
3893                         iommus = <&apps_smmu 0x800 0x400>,
3894                                  <&apps_smmu 0x801 0x400>,
3895                                  <&apps_smmu 0x840 0x400>,
3896                                  <&apps_smmu 0x841 0x400>,
3897                                  <&apps_smmu 0xc00 0x400>,
3898                                  <&apps_smmu 0xc01 0x400>,
3899                                  <&apps_smmu 0xc40 0x400>,
3900                                  <&apps_smmu 0xc41 0x400>;
3901
3902                         interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>,
3903                                         <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>,
3904                                         <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>,
3905                                         <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>;
3906                         interconnect-names = "cam_ahb",
3907                                              "cam_hf_0_mnoc",
3908                                              "cam_sf_0_mnoc",
3909                                              "cam_sf_icp_mnoc";
3910
3911                         ports {
3912                                 #address-cells = <1>;
3913                                 #size-cells = <0>;
3914
3915                                 port@0 {
3916                                         reg = <0>;
3917                                 };
3918
3919                                 port@1 {
3920                                         reg = <1>;
3921                                 };
3922
3923                                 port@2 {
3924                                         reg = <2>;
3925                                 };
3926
3927                                 port@3 {
3928                                         reg = <3>;
3929                                 };
3930
3931                                 port@4 {
3932                                         reg = <4>;
3933                                 };
3934
3935                                 port@5 {
3936                                         reg = <5>;
3937                                 };
3938                         };
3939                 };
3940
3941                 camcc: clock-controller@ad00000 {
3942                         compatible = "qcom,sm8250-camcc";
3943                         reg = <0 0x0ad00000 0 0x10000>;
3944                         clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3945                                  <&rpmhcc RPMH_CXO_CLK>,
3946                                  <&rpmhcc RPMH_CXO_CLK_A>,
3947                                  <&sleep_clk>;
3948                         clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
3949                         power-domains = <&rpmhpd SM8250_MMCX>;
3950                         required-opps = <&rpmhpd_opp_low_svs>;
3951                         status = "disabled";
3952                         #clock-cells = <1>;
3953                         #reset-cells = <1>;
3954                         #power-domain-cells = <1>;
3955                 };
3956
3957                 mdss: mdss@ae00000 {
3958                         compatible = "qcom,sm8250-mdss";
3959                         reg = <0 0x0ae00000 0 0x1000>;
3960                         reg-names = "mdss";
3961
3962                         interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
3963                                         <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
3964                         interconnect-names = "mdp0-mem", "mdp1-mem";
3965
3966                         power-domains = <&dispcc MDSS_GDSC>;
3967
3968                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3969                                  <&gcc GCC_DISP_HF_AXI_CLK>,
3970                                  <&gcc GCC_DISP_SF_AXI_CLK>,
3971                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
3972                         clock-names = "iface", "bus", "nrt_bus", "core";
3973
3974                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3975                         interrupt-controller;
3976                         #interrupt-cells = <1>;
3977
3978                         iommus = <&apps_smmu 0x820 0x402>;
3979
3980                         status = "disabled";
3981
3982                         #address-cells = <2>;
3983                         #size-cells = <2>;
3984                         ranges;
3985
3986                         mdss_mdp: display-controller@ae01000 {
3987                                 compatible = "qcom,sm8250-dpu";
3988                                 reg = <0 0x0ae01000 0 0x8f000>,
3989                                       <0 0x0aeb0000 0 0x2008>;
3990                                 reg-names = "mdp", "vbif";
3991
3992                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3993                                          <&gcc GCC_DISP_HF_AXI_CLK>,
3994                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
3995                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3996                                 clock-names = "iface", "bus", "core", "vsync";
3997
3998                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3999                                 assigned-clock-rates = <19200000>;
4000
4001                                 operating-points-v2 = <&mdp_opp_table>;
4002                                 power-domains = <&rpmhpd SM8250_MMCX>;
4003
4004                                 interrupt-parent = <&mdss>;
4005                                 interrupts = <0>;
4006
4007                                 ports {
4008                                         #address-cells = <1>;
4009                                         #size-cells = <0>;
4010
4011                                         port@0 {
4012                                                 reg = <0>;
4013                                                 dpu_intf1_out: endpoint {
4014                                                         remote-endpoint = <&dsi0_in>;
4015                                                 };
4016                                         };
4017
4018                                         port@1 {
4019                                                 reg = <1>;
4020                                                 dpu_intf2_out: endpoint {
4021                                                         remote-endpoint = <&dsi1_in>;
4022                                                 };
4023                                         };
4024                                 };
4025
4026                                 mdp_opp_table: opp-table {
4027                                         compatible = "operating-points-v2";
4028
4029                                         opp-200000000 {
4030                                                 opp-hz = /bits/ 64 <200000000>;
4031                                                 required-opps = <&rpmhpd_opp_low_svs>;
4032                                         };
4033
4034                                         opp-300000000 {
4035                                                 opp-hz = /bits/ 64 <300000000>;
4036                                                 required-opps = <&rpmhpd_opp_svs>;
4037                                         };
4038
4039                                         opp-345000000 {
4040                                                 opp-hz = /bits/ 64 <345000000>;
4041                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4042                                         };
4043
4044                                         opp-460000000 {
4045                                                 opp-hz = /bits/ 64 <460000000>;
4046                                                 required-opps = <&rpmhpd_opp_nom>;
4047                                         };
4048                                 };
4049                         };
4050
4051                         dsi0: dsi@ae94000 {
4052                                 compatible = "qcom,mdss-dsi-ctrl";
4053                                 reg = <0 0x0ae94000 0 0x400>;
4054                                 reg-names = "dsi_ctrl";
4055
4056                                 interrupt-parent = <&mdss>;
4057                                 interrupts = <4>;
4058
4059                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4060                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4061                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4062                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4063                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
4064                                         <&gcc GCC_DISP_HF_AXI_CLK>;
4065                                 clock-names = "byte",
4066                                               "byte_intf",
4067                                               "pixel",
4068                                               "core",
4069                                               "iface",
4070                                               "bus";
4071
4072                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4073                                 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
4074
4075                                 operating-points-v2 = <&dsi_opp_table>;
4076                                 power-domains = <&rpmhpd SM8250_MMCX>;
4077
4078                                 phys = <&dsi0_phy>;
4079
4080                                 status = "disabled";
4081
4082                                 #address-cells = <1>;
4083                                 #size-cells = <0>;
4084
4085                                 ports {
4086                                         #address-cells = <1>;
4087                                         #size-cells = <0>;
4088
4089                                         port@0 {
4090                                                 reg = <0>;
4091                                                 dsi0_in: endpoint {
4092                                                         remote-endpoint = <&dpu_intf1_out>;
4093                                                 };
4094                                         };
4095
4096                                         port@1 {
4097                                                 reg = <1>;
4098                                                 dsi0_out: endpoint {
4099                                                 };
4100                                         };
4101                                 };
4102
4103                                 dsi_opp_table: opp-table {
4104                                         compatible = "operating-points-v2";
4105
4106                                         opp-187500000 {
4107                                                 opp-hz = /bits/ 64 <187500000>;
4108                                                 required-opps = <&rpmhpd_opp_low_svs>;
4109                                         };
4110
4111                                         opp-300000000 {
4112                                                 opp-hz = /bits/ 64 <300000000>;
4113                                                 required-opps = <&rpmhpd_opp_svs>;
4114                                         };
4115
4116                                         opp-358000000 {
4117                                                 opp-hz = /bits/ 64 <358000000>;
4118                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4119                                         };
4120                                 };
4121                         };
4122
4123                         dsi0_phy: phy@ae94400 {
4124                                 compatible = "qcom,dsi-phy-7nm";
4125                                 reg = <0 0x0ae94400 0 0x200>,
4126                                       <0 0x0ae94600 0 0x280>,
4127                                       <0 0x0ae94900 0 0x260>;
4128                                 reg-names = "dsi_phy",
4129                                             "dsi_phy_lane",
4130                                             "dsi_pll";
4131
4132                                 #clock-cells = <1>;
4133                                 #phy-cells = <0>;
4134
4135                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4136                                          <&rpmhcc RPMH_CXO_CLK>;
4137                                 clock-names = "iface", "ref";
4138
4139                                 status = "disabled";
4140                         };
4141
4142                         dsi1: dsi@ae96000 {
4143                                 compatible = "qcom,mdss-dsi-ctrl";
4144                                 reg = <0 0x0ae96000 0 0x400>;
4145                                 reg-names = "dsi_ctrl";
4146
4147                                 interrupt-parent = <&mdss>;
4148                                 interrupts = <5>;
4149
4150                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4151                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4152                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4153                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4154                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
4155                                          <&gcc GCC_DISP_HF_AXI_CLK>;
4156                                 clock-names = "byte",
4157                                               "byte_intf",
4158                                               "pixel",
4159                                               "core",
4160                                               "iface",
4161                                               "bus";
4162
4163                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4164                                 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
4165
4166                                 operating-points-v2 = <&dsi_opp_table>;
4167                                 power-domains = <&rpmhpd SM8250_MMCX>;
4168
4169                                 phys = <&dsi1_phy>;
4170
4171                                 status = "disabled";
4172
4173                                 #address-cells = <1>;
4174                                 #size-cells = <0>;
4175
4176                                 ports {
4177                                         #address-cells = <1>;
4178                                         #size-cells = <0>;
4179
4180                                         port@0 {
4181                                                 reg = <0>;
4182                                                 dsi1_in: endpoint {
4183                                                         remote-endpoint = <&dpu_intf2_out>;
4184                                                 };
4185                                         };
4186
4187                                         port@1 {
4188                                                 reg = <1>;
4189                                                 dsi1_out: endpoint {
4190                                                 };
4191                                         };
4192                                 };
4193                         };
4194
4195                         dsi1_phy: phy@ae96400 {
4196                                 compatible = "qcom,dsi-phy-7nm";
4197                                 reg = <0 0x0ae96400 0 0x200>,
4198                                       <0 0x0ae96600 0 0x280>,
4199                                       <0 0x0ae96900 0 0x260>;
4200                                 reg-names = "dsi_phy",
4201                                             "dsi_phy_lane",
4202                                             "dsi_pll";
4203
4204                                 #clock-cells = <1>;
4205                                 #phy-cells = <0>;
4206
4207                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4208                                          <&rpmhcc RPMH_CXO_CLK>;
4209                                 clock-names = "iface", "ref";
4210
4211                                 status = "disabled";
4212                         };
4213                 };
4214
4215                 dispcc: clock-controller@af00000 {
4216                         compatible = "qcom,sm8250-dispcc";
4217                         reg = <0 0x0af00000 0 0x10000>;
4218                         power-domains = <&rpmhpd SM8250_MMCX>;
4219                         required-opps = <&rpmhpd_opp_low_svs>;
4220                         clocks = <&rpmhcc RPMH_CXO_CLK>,
4221                                  <&dsi0_phy 0>,
4222                                  <&dsi0_phy 1>,
4223                                  <&dsi1_phy 0>,
4224                                  <&dsi1_phy 1>,
4225                                  <&dp_phy 0>,
4226                                  <&dp_phy 1>;
4227                         clock-names = "bi_tcxo",
4228                                       "dsi0_phy_pll_out_byteclk",
4229                                       "dsi0_phy_pll_out_dsiclk",
4230                                       "dsi1_phy_pll_out_byteclk",
4231                                       "dsi1_phy_pll_out_dsiclk",
4232                                       "dp_phy_pll_link_clk",
4233                                       "dp_phy_pll_vco_div_clk";
4234                         #clock-cells = <1>;
4235                         #reset-cells = <1>;
4236                         #power-domain-cells = <1>;
4237                 };
4238
4239                 pdc: interrupt-controller@b220000 {
4240                         compatible = "qcom,sm8250-pdc", "qcom,pdc";
4241                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
4242                         qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4243                                           <125 63 1>, <126 716 12>;
4244                         #interrupt-cells = <2>;
4245                         interrupt-parent = <&intc>;
4246                         interrupt-controller;
4247                 };
4248
4249                 tsens0: thermal-sensor@c263000 {
4250                         compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
4251                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
4252                               <0 0x0c222000 0 0x1ff>; /* SROT */
4253                         #qcom,sensors = <16>;
4254                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4255                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4256                         interrupt-names = "uplow", "critical";
4257                         #thermal-sensor-cells = <1>;
4258                 };
4259
4260                 tsens1: thermal-sensor@c265000 {
4261                         compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
4262                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
4263                               <0 0x0c223000 0 0x1ff>; /* SROT */
4264                         #qcom,sensors = <9>;
4265                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4266                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4267                         interrupt-names = "uplow", "critical";
4268                         #thermal-sensor-cells = <1>;
4269                 };
4270
4271                 aoss_qmp: power-controller@c300000 {
4272                         compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
4273                         reg = <0 0x0c300000 0 0x400>;
4274                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP
4275                                                      IPCC_MPROC_SIGNAL_GLINK_QMP
4276                                                      IRQ_TYPE_EDGE_RISING>;
4277                         mboxes = <&ipcc IPCC_CLIENT_AOP
4278                                         IPCC_MPROC_SIGNAL_GLINK_QMP>;
4279
4280                         #clock-cells = <0>;
4281                 };
4282
4283                 sram@c3f0000 {
4284                         compatible = "qcom,rpmh-stats";
4285                         reg = <0 0x0c3f0000 0 0x400>;
4286                 };
4287
4288                 spmi_bus: spmi@c440000 {
4289                         compatible = "qcom,spmi-pmic-arb";
4290                         reg = <0x0 0x0c440000 0x0 0x0001100>,
4291                               <0x0 0x0c600000 0x0 0x2000000>,
4292                               <0x0 0x0e600000 0x0 0x0100000>,
4293                               <0x0 0x0e700000 0x0 0x00a0000>,
4294                               <0x0 0x0c40a000 0x0 0x0026000>;
4295                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4296                         interrupt-names = "periph_irq";
4297                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4298                         qcom,ee = <0>;
4299                         qcom,channel = <0>;
4300                         #address-cells = <2>;
4301                         #size-cells = <0>;
4302                         interrupt-controller;
4303                         #interrupt-cells = <4>;
4304                 };
4305
4306                 tlmm: pinctrl@f100000 {
4307                         compatible = "qcom,sm8250-pinctrl";
4308                         reg = <0 0x0f100000 0 0x300000>,
4309                               <0 0x0f500000 0 0x300000>,
4310                               <0 0x0f900000 0 0x300000>;
4311                         reg-names = "west", "south", "north";
4312                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
4313                         gpio-controller;
4314                         #gpio-cells = <2>;
4315                         interrupt-controller;
4316                         #interrupt-cells = <2>;
4317                         gpio-ranges = <&tlmm 0 0 181>;
4318                         wakeup-parent = <&pdc>;
4319
4320                         cam2_default: cam2-default-state {
4321                                 rst-pins {
4322                                         pins = "gpio78";
4323                                         function = "gpio";
4324                                         drive-strength = <2>;
4325                                         bias-disable;
4326                                 };
4327
4328                                 mclk-pins {
4329                                         pins = "gpio96";
4330                                         function = "cam_mclk";
4331                                         drive-strength = <16>;
4332                                         bias-disable;
4333                                 };
4334                         };
4335
4336                         cam2_suspend: cam2-suspend-state {
4337                                 rst-pins {
4338                                         pins = "gpio78";
4339                                         function = "gpio";
4340                                         drive-strength = <2>;
4341                                         bias-pull-down;
4342                                         output-low;
4343                                 };
4344
4345                                 mclk-pins {
4346                                         pins = "gpio96";
4347                                         function = "cam_mclk";
4348                                         drive-strength = <2>;
4349                                         bias-disable;
4350                                 };
4351                         };
4352
4353                         cci0_default: cci0-default-state {
4354                                 cci0_i2c0_default: cci0-i2c0-default-pins {
4355                                         /* SDA, SCL */
4356                                         pins = "gpio101", "gpio102";
4357                                         function = "cci_i2c";
4358
4359                                         bias-pull-up;
4360                                         drive-strength = <2>; /* 2 mA */
4361                                 };
4362
4363                                 cci0_i2c1_default: cci0-i2c1-default-pins {
4364                                         /* SDA, SCL */
4365                                         pins = "gpio103", "gpio104";
4366                                         function = "cci_i2c";
4367
4368                                         bias-pull-up;
4369                                         drive-strength = <2>; /* 2 mA */
4370                                 };
4371                         };
4372
4373                         cci0_sleep: cci0-sleep-state {
4374                                 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
4375                                         /* SDA, SCL */
4376                                         pins = "gpio101", "gpio102";
4377                                         function = "cci_i2c";
4378
4379                                         drive-strength = <2>; /* 2 mA */
4380                                         bias-pull-down;
4381                                 };
4382
4383                                 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
4384                                         /* SDA, SCL */
4385                                         pins = "gpio103", "gpio104";
4386                                         function = "cci_i2c";
4387
4388                                         drive-strength = <2>; /* 2 mA */
4389                                         bias-pull-down;
4390                                 };
4391                         };
4392
4393                         cci1_default: cci1-default-state {
4394                                 cci1_i2c0_default: cci1-i2c0-default-pins {
4395                                         /* SDA, SCL */
4396                                         pins = "gpio105","gpio106";
4397                                         function = "cci_i2c";
4398
4399                                         bias-pull-up;
4400                                         drive-strength = <2>; /* 2 mA */
4401                                 };
4402
4403                                 cci1_i2c1_default: cci1-i2c1-default-pins {
4404                                         /* SDA, SCL */
4405                                         pins = "gpio107","gpio108";
4406                                         function = "cci_i2c";
4407
4408                                         bias-pull-up;
4409                                         drive-strength = <2>; /* 2 mA */
4410                                 };
4411                         };
4412
4413                         cci1_sleep: cci1-sleep-state {
4414                                 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
4415                                         /* SDA, SCL */
4416                                         pins = "gpio105","gpio106";
4417                                         function = "cci_i2c";
4418
4419                                         bias-pull-down;
4420                                         drive-strength = <2>; /* 2 mA */
4421                                 };
4422
4423                                 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
4424                                         /* SDA, SCL */
4425                                         pins = "gpio107","gpio108";
4426                                         function = "cci_i2c";
4427
4428                                         bias-pull-down;
4429                                         drive-strength = <2>; /* 2 mA */
4430                                 };
4431                         };
4432
4433                         pri_mi2s_active: pri-mi2s-active-state {
4434                                 sclk-pins {
4435                                         pins = "gpio138";
4436                                         function = "mi2s0_sck";
4437                                         drive-strength = <8>;
4438                                         bias-disable;
4439                                 };
4440
4441                                 ws-pins {
4442                                         pins = "gpio141";
4443                                         function = "mi2s0_ws";
4444                                         drive-strength = <8>;
4445                                         output-high;
4446                                 };
4447
4448                                 data0-pins {
4449                                         pins = "gpio139";
4450                                         function = "mi2s0_data0";
4451                                         drive-strength = <8>;
4452                                         bias-disable;
4453                                         output-high;
4454                                 };
4455
4456                                 data1-pins {
4457                                         pins = "gpio140";
4458                                         function = "mi2s0_data1";
4459                                         drive-strength = <8>;
4460                                         output-high;
4461                                 };
4462                         };
4463
4464                         qup_i2c0_default: qup-i2c0-default-state {
4465                                 pins = "gpio28", "gpio29";
4466                                 function = "qup0";
4467                                 drive-strength = <2>;
4468                                 bias-disable;
4469                         };
4470
4471                         qup_i2c1_default: qup-i2c1-default-state {
4472                                 pins = "gpio4", "gpio5";
4473                                 function = "qup1";
4474                                 drive-strength = <2>;
4475                                 bias-disable;
4476                         };
4477
4478                         qup_i2c2_default: qup-i2c2-default-state {
4479                                 pins = "gpio115", "gpio116";
4480                                 function = "qup2";
4481                                 drive-strength = <2>;
4482                                 bias-disable;
4483                         };
4484
4485                         qup_i2c3_default: qup-i2c3-default-state {
4486                                 pins = "gpio119", "gpio120";
4487                                 function = "qup3";
4488                                 drive-strength = <2>;
4489                                 bias-disable;
4490                         };
4491
4492                         qup_i2c4_default: qup-i2c4-default-state {
4493                                 pins = "gpio8", "gpio9";
4494                                 function = "qup4";
4495                                 drive-strength = <2>;
4496                                 bias-disable;
4497                         };
4498
4499                         qup_i2c5_default: qup-i2c5-default-state {
4500                                 pins = "gpio12", "gpio13";
4501                                 function = "qup5";
4502                                 drive-strength = <2>;
4503                                 bias-disable;
4504                         };
4505
4506                         qup_i2c6_default: qup-i2c6-default-state {
4507                                 pins = "gpio16", "gpio17";
4508                                 function = "qup6";
4509                                 drive-strength = <2>;
4510                                 bias-disable;
4511                         };
4512
4513                         qup_i2c7_default: qup-i2c7-default-state {
4514                                 pins = "gpio20", "gpio21";
4515                                 function = "qup7";
4516                                 drive-strength = <2>;
4517                                 bias-disable;
4518                         };
4519
4520                         qup_i2c8_default: qup-i2c8-default-state {
4521                                 pins = "gpio24", "gpio25";
4522                                 function = "qup8";
4523                                 drive-strength = <2>;
4524                                 bias-disable;
4525                         };
4526
4527                         qup_i2c9_default: qup-i2c9-default-state {
4528                                 pins = "gpio125", "gpio126";
4529                                 function = "qup9";
4530                                 drive-strength = <2>;
4531                                 bias-disable;
4532                         };
4533
4534                         qup_i2c10_default: qup-i2c10-default-state {
4535                                 pins = "gpio129", "gpio130";
4536                                 function = "qup10";
4537                                 drive-strength = <2>;
4538                                 bias-disable;
4539                         };
4540
4541                         qup_i2c11_default: qup-i2c11-default-state {
4542                                 pins = "gpio60", "gpio61";
4543                                 function = "qup11";
4544                                 drive-strength = <2>;
4545                                 bias-disable;
4546                         };
4547
4548                         qup_i2c12_default: qup-i2c12-default-state {
4549                                 pins = "gpio32", "gpio33";
4550                                 function = "qup12";
4551                                 drive-strength = <2>;
4552                                 bias-disable;
4553                         };
4554
4555                         qup_i2c13_default: qup-i2c13-default-state {
4556                                 pins = "gpio36", "gpio37";
4557                                 function = "qup13";
4558                                 drive-strength = <2>;
4559                                 bias-disable;
4560                         };
4561
4562                         qup_i2c14_default: qup-i2c14-default-state {
4563                                 pins = "gpio40", "gpio41";
4564                                 function = "qup14";
4565                                 drive-strength = <2>;
4566                                 bias-disable;
4567                         };
4568
4569                         qup_i2c15_default: qup-i2c15-default-state {
4570                                 pins = "gpio44", "gpio45";
4571                                 function = "qup15";
4572                                 drive-strength = <2>;
4573                                 bias-disable;
4574                         };
4575
4576                         qup_i2c16_default: qup-i2c16-default-state {
4577                                 pins = "gpio48", "gpio49";
4578                                 function = "qup16";
4579                                 drive-strength = <2>;
4580                                 bias-disable;
4581                         };
4582
4583                         qup_i2c17_default: qup-i2c17-default-state {
4584                                 pins = "gpio52", "gpio53";
4585                                 function = "qup17";
4586                                 drive-strength = <2>;
4587                                 bias-disable;
4588                         };
4589
4590                         qup_i2c18_default: qup-i2c18-default-state {
4591                                 pins = "gpio56", "gpio57";
4592                                 function = "qup18";
4593                                 drive-strength = <2>;
4594                                 bias-disable;
4595                         };
4596
4597                         qup_i2c19_default: qup-i2c19-default-state {
4598                                 pins = "gpio0", "gpio1";
4599                                 function = "qup19";
4600                                 drive-strength = <2>;
4601                                 bias-disable;
4602                         };
4603
4604                         qup_spi0_cs: qup-spi0-cs-state {
4605                                 pins = "gpio31";
4606                                 function = "qup0";
4607                         };
4608
4609                         qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
4610                                 pins = "gpio31";
4611                                 function = "gpio";
4612                         };
4613
4614                         qup_spi0_data_clk: qup-spi0-data-clk-state {
4615                                 pins = "gpio28", "gpio29",
4616                                        "gpio30";
4617                                 function = "qup0";
4618                         };
4619
4620                         qup_spi1_cs: qup-spi1-cs-state {
4621                                 pins = "gpio7";
4622                                 function = "qup1";
4623                         };
4624
4625                         qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
4626                                 pins = "gpio7";
4627                                 function = "gpio";
4628                         };
4629
4630                         qup_spi1_data_clk: qup-spi1-data-clk-state {
4631                                 pins = "gpio4", "gpio5",
4632                                        "gpio6";
4633                                 function = "qup1";
4634                         };
4635
4636                         qup_spi2_cs: qup-spi2-cs-state {
4637                                 pins = "gpio118";
4638                                 function = "qup2";
4639                         };
4640
4641                         qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
4642                                 pins = "gpio118";
4643                                 function = "gpio";
4644                         };
4645
4646                         qup_spi2_data_clk: qup-spi2-data-clk-state {
4647                                 pins = "gpio115", "gpio116",
4648                                        "gpio117";
4649                                 function = "qup2";
4650                         };
4651
4652                         qup_spi3_cs: qup-spi3-cs-state {
4653                                 pins = "gpio122";
4654                                 function = "qup3";
4655                         };
4656
4657                         qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
4658                                 pins = "gpio122";
4659                                 function = "gpio";
4660                         };
4661
4662                         qup_spi3_data_clk: qup-spi3-data-clk-state {
4663                                 pins = "gpio119", "gpio120",
4664                                        "gpio121";
4665                                 function = "qup3";
4666                         };
4667
4668                         qup_spi4_cs: qup-spi4-cs-state {
4669                                 pins = "gpio11";
4670                                 function = "qup4";
4671                         };
4672
4673                         qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
4674                                 pins = "gpio11";
4675                                 function = "gpio";
4676                         };
4677
4678                         qup_spi4_data_clk: qup-spi4-data-clk-state {
4679                                 pins = "gpio8", "gpio9",
4680                                        "gpio10";
4681                                 function = "qup4";
4682                         };
4683
4684                         qup_spi5_cs: qup-spi5-cs-state {
4685                                 pins = "gpio15";
4686                                 function = "qup5";
4687                         };
4688
4689                         qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
4690                                 pins = "gpio15";
4691                                 function = "gpio";
4692                         };
4693
4694                         qup_spi5_data_clk: qup-spi5-data-clk-state {
4695                                 pins = "gpio12", "gpio13",
4696                                        "gpio14";
4697                                 function = "qup5";
4698                         };
4699
4700                         qup_spi6_cs: qup-spi6-cs-state {
4701                                 pins = "gpio19";
4702                                 function = "qup6";
4703                         };
4704
4705                         qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
4706                                 pins = "gpio19";
4707                                 function = "gpio";
4708                         };
4709
4710                         qup_spi6_data_clk: qup-spi6-data-clk-state {
4711                                 pins = "gpio16", "gpio17",
4712                                        "gpio18";
4713                                 function = "qup6";
4714                         };
4715
4716                         qup_spi7_cs: qup-spi7-cs-state {
4717                                 pins = "gpio23";
4718                                 function = "qup7";
4719                         };
4720
4721                         qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
4722                                 pins = "gpio23";
4723                                 function = "gpio";
4724                         };
4725
4726                         qup_spi7_data_clk: qup-spi7-data-clk-state {
4727                                 pins = "gpio20", "gpio21",
4728                                        "gpio22";
4729                                 function = "qup7";
4730                         };
4731
4732                         qup_spi8_cs: qup-spi8-cs-state {
4733                                 pins = "gpio27";
4734                                 function = "qup8";
4735                         };
4736
4737                         qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
4738                                 pins = "gpio27";
4739                                 function = "gpio";
4740                         };
4741
4742                         qup_spi8_data_clk: qup-spi8-data-clk-state {
4743                                 pins = "gpio24", "gpio25",
4744                                        "gpio26";
4745                                 function = "qup8";
4746                         };
4747
4748                         qup_spi9_cs: qup-spi9-cs-state {
4749                                 pins = "gpio128";
4750                                 function = "qup9";
4751                         };
4752
4753                         qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
4754                                 pins = "gpio128";
4755                                 function = "gpio";
4756                         };
4757
4758                         qup_spi9_data_clk: qup-spi9-data-clk-state {
4759                                 pins = "gpio125", "gpio126",
4760                                        "gpio127";
4761                                 function = "qup9";
4762                         };
4763
4764                         qup_spi10_cs: qup-spi10-cs-state {
4765                                 pins = "gpio132";
4766                                 function = "qup10";
4767                         };
4768
4769                         qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
4770                                 pins = "gpio132";
4771                                 function = "gpio";
4772                         };
4773
4774                         qup_spi10_data_clk: qup-spi10-data-clk-state {
4775                                 pins = "gpio129", "gpio130",
4776                                        "gpio131";
4777                                 function = "qup10";
4778                         };
4779
4780                         qup_spi11_cs: qup-spi11-cs-state {
4781                                 pins = "gpio63";
4782                                 function = "qup11";
4783                         };
4784
4785                         qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
4786                                 pins = "gpio63";
4787                                 function = "gpio";
4788                         };
4789
4790                         qup_spi11_data_clk: qup-spi11-data-clk-state {
4791                                 pins = "gpio60", "gpio61",
4792                                        "gpio62";
4793                                 function = "qup11";
4794                         };
4795
4796                         qup_spi12_cs: qup-spi12-cs-state {
4797                                 pins = "gpio35";
4798                                 function = "qup12";
4799                         };
4800
4801                         qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
4802                                 pins = "gpio35";
4803                                 function = "gpio";
4804                         };
4805
4806                         qup_spi12_data_clk: qup-spi12-data-clk-state {
4807                                 pins = "gpio32", "gpio33",
4808                                        "gpio34";
4809                                 function = "qup12";
4810                         };
4811
4812                         qup_spi13_cs: qup-spi13-cs-state {
4813                                 pins = "gpio39";
4814                                 function = "qup13";
4815                         };
4816
4817                         qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
4818                                 pins = "gpio39";
4819                                 function = "gpio";
4820                         };
4821
4822                         qup_spi13_data_clk: qup-spi13-data-clk-state {
4823                                 pins = "gpio36", "gpio37",
4824                                        "gpio38";
4825                                 function = "qup13";
4826                         };
4827
4828                         qup_spi14_cs: qup-spi14-cs-state {
4829                                 pins = "gpio43";
4830                                 function = "qup14";
4831                         };
4832
4833                         qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
4834                                 pins = "gpio43";
4835                                 function = "gpio";
4836                         };
4837
4838                         qup_spi14_data_clk: qup-spi14-data-clk-state {
4839                                 pins = "gpio40", "gpio41",
4840                                        "gpio42";
4841                                 function = "qup14";
4842                         };
4843
4844                         qup_spi15_cs: qup-spi15-cs-state {
4845                                 pins = "gpio47";
4846                                 function = "qup15";
4847                         };
4848
4849                         qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
4850                                 pins = "gpio47";
4851                                 function = "gpio";
4852                         };
4853
4854                         qup_spi15_data_clk: qup-spi15-data-clk-state {
4855                                 pins = "gpio44", "gpio45",
4856                                        "gpio46";
4857                                 function = "qup15";
4858                         };
4859
4860                         qup_spi16_cs: qup-spi16-cs-state {
4861                                 pins = "gpio51";
4862                                 function = "qup16";
4863                         };
4864
4865                         qup_spi16_cs_gpio: qup-spi16-cs-gpio-state {
4866                                 pins = "gpio51";
4867                                 function = "gpio";
4868                         };
4869
4870                         qup_spi16_data_clk: qup-spi16-data-clk-state {
4871                                 pins = "gpio48", "gpio49",
4872                                        "gpio50";
4873                                 function = "qup16";
4874                         };
4875
4876                         qup_spi17_cs: qup-spi17-cs-state {
4877                                 pins = "gpio55";
4878                                 function = "qup17";
4879                         };
4880
4881                         qup_spi17_cs_gpio: qup-spi17-cs-gpio-state {
4882                                 pins = "gpio55";
4883                                 function = "gpio";
4884                         };
4885
4886                         qup_spi17_data_clk: qup-spi17-data-clk-state {
4887                                 pins = "gpio52", "gpio53",
4888                                        "gpio54";
4889                                 function = "qup17";
4890                         };
4891
4892                         qup_spi18_cs: qup-spi18-cs-state {
4893                                 pins = "gpio59";
4894                                 function = "qup18";
4895                         };
4896
4897                         qup_spi18_cs_gpio: qup-spi18-cs-gpio-state {
4898                                 pins = "gpio59";
4899                                 function = "gpio";
4900                         };
4901
4902                         qup_spi18_data_clk: qup-spi18-data-clk-state {
4903                                 pins = "gpio56", "gpio57",
4904                                        "gpio58";
4905                                 function = "qup18";
4906                         };
4907
4908                         qup_spi19_cs: qup-spi19-cs-state {
4909                                 pins = "gpio3";
4910                                 function = "qup19";
4911                         };
4912
4913                         qup_spi19_cs_gpio: qup-spi19-cs-gpio-state {
4914                                 pins = "gpio3";
4915                                 function = "gpio";
4916                         };
4917
4918                         qup_spi19_data_clk: qup-spi19-data-clk-state {
4919                                 pins = "gpio0", "gpio1",
4920                                        "gpio2";
4921                                 function = "qup19";
4922                         };
4923
4924                         qup_uart2_default: qup-uart2-default-state {
4925                                 pins = "gpio117", "gpio118";
4926                                 function = "qup2";
4927                         };
4928
4929                         qup_uart6_default: qup-uart6-default-state {
4930                                 pins = "gpio16", "gpio17", "gpio18", "gpio19";
4931                                 function = "qup6";
4932                         };
4933
4934                         qup_uart12_default: qup-uart12-default-state {
4935                                 pins = "gpio34", "gpio35";
4936                                 function = "qup12";
4937                         };
4938
4939                         qup_uart17_default: qup-uart17-default-state {
4940                                 pins = "gpio52", "gpio53", "gpio54", "gpio55";
4941                                 function = "qup17";
4942                         };
4943
4944                         qup_uart18_default: qup-uart18-default-state {
4945                                 pins = "gpio58", "gpio59";
4946                                 function = "qup18";
4947                         };
4948
4949                         tert_mi2s_active: tert-mi2s-active-state {
4950                                 sck-pins {
4951                                         pins = "gpio133";
4952                                         function = "mi2s2_sck";
4953                                         drive-strength = <8>;
4954                                         bias-disable;
4955                                 };
4956
4957                                 data0-pins {
4958                                         pins = "gpio134";
4959                                         function = "mi2s2_data0";
4960                                         drive-strength = <8>;
4961                                         bias-disable;
4962                                         output-high;
4963                                 };
4964
4965                                 ws-pins {
4966                                         pins = "gpio135";
4967                                         function = "mi2s2_ws";
4968                                         drive-strength = <8>;
4969                                         output-high;
4970                                 };
4971                         };
4972
4973                         sdc2_sleep_state: sdc2-sleep-state {
4974                                 clk-pins {
4975                                         pins = "sdc2_clk";
4976                                         drive-strength = <2>;
4977                                         bias-disable;
4978                                 };
4979
4980                                 cmd-pins {
4981                                         pins = "sdc2_cmd";
4982                                         drive-strength = <2>;
4983                                         bias-pull-up;
4984                                 };
4985
4986                                 data-pins {
4987                                         pins = "sdc2_data";
4988                                         drive-strength = <2>;
4989                                         bias-pull-up;
4990                                 };
4991                         };
4992
4993                         pcie0_default_state: pcie0-default-state {
4994                                 perst-pins {
4995                                         pins = "gpio79";
4996                                         function = "gpio";
4997                                         drive-strength = <2>;
4998                                         bias-pull-down;
4999                                 };
5000
5001                                 clkreq-pins {
5002                                         pins = "gpio80";
5003                                         function = "pci_e0";
5004                                         drive-strength = <2>;
5005                                         bias-pull-up;
5006                                 };
5007
5008                                 wake-pins {
5009                                         pins = "gpio81";
5010                                         function = "gpio";
5011                                         drive-strength = <2>;
5012                                         bias-pull-up;
5013                                 };
5014                         };
5015
5016                         pcie1_default_state: pcie1-default-state {
5017                                 perst-pins {
5018                                         pins = "gpio82";
5019                                         function = "gpio";
5020                                         drive-strength = <2>;
5021                                         bias-pull-down;
5022                                 };
5023
5024                                 clkreq-pins {
5025                                         pins = "gpio83";
5026                                         function = "pci_e1";
5027                                         drive-strength = <2>;
5028                                         bias-pull-up;
5029                                 };
5030
5031                                 wake-pins {
5032                                         pins = "gpio84";
5033                                         function = "gpio";
5034                                         drive-strength = <2>;
5035                                         bias-pull-up;
5036                                 };
5037                         };
5038
5039                         pcie2_default_state: pcie2-default-state {
5040                                 perst-pins {
5041                                         pins = "gpio85";
5042                                         function = "gpio";
5043                                         drive-strength = <2>;
5044                                         bias-pull-down;
5045                                 };
5046
5047                                 clkreq-pins {
5048                                         pins = "gpio86";
5049                                         function = "pci_e2";
5050                                         drive-strength = <2>;
5051                                         bias-pull-up;
5052                                 };
5053
5054                                 wake-pins {
5055                                         pins = "gpio87";
5056                                         function = "gpio";
5057                                         drive-strength = <2>;
5058                                         bias-pull-up;
5059                                 };
5060                         };
5061                 };
5062
5063                 apps_smmu: iommu@15000000 {
5064                         compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
5065                         reg = <0 0x15000000 0 0x100000>;
5066                         #iommu-cells = <2>;
5067                         #global-interrupts = <2>;
5068                         interrupts =    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
5069                                         <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5070                                         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5071                                         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5072                                         <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5073                                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5074                                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5075                                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5076                                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5077                                         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5078                                         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5079                                         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5080                                         <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5081                                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5082                                         <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5083                                         <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5084                                         <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5085                                         <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5086                                         <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5087                                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5088                                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5089                                         <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5090                                         <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5091                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5092                                         <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5093                                         <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5094                                         <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5095                                         <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5096                                         <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5097                                         <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5098                                         <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5099                                         <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5100                                         <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5101                                         <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5102                                         <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5103                                         <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5104                                         <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5105                                         <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5106                                         <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5107                                         <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5108                                         <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5109                                         <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5110                                         <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5111                                         <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5112                                         <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5113                                         <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5114                                         <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5115                                         <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5116                                         <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5117                                         <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5118                                         <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5119                                         <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5120                                         <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5121                                         <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5122                                         <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5123                                         <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5124                                         <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5125                                         <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5126                                         <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5127                                         <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5128                                         <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5129                                         <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5130                                         <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5131                                         <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5132                                         <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5133                                         <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5134                                         <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5135                                         <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5136                                         <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5137                                         <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5138                                         <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5139                                         <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5140                                         <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5141                                         <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5142                                         <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5143                                         <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5144                                         <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5145                                         <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5146                                         <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5147                                         <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5148                                         <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5149                                         <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5150                                         <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5151                                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5152                                         <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5153                                         <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5154                                         <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5155                                         <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5156                                         <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5157                                         <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5158                                         <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5159                                         <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5160                                         <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5161                                         <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5162                                         <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5163                                         <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5164                                         <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
5165                                         <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
5166                 };
5167
5168                 adsp: remoteproc@17300000 {
5169                         compatible = "qcom,sm8250-adsp-pas";
5170                         reg = <0 0x17300000 0 0x100>;
5171
5172                         interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
5173                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5174                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5175                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
5176                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
5177                         interrupt-names = "wdog", "fatal", "ready",
5178                                           "handover", "stop-ack";
5179
5180                         clocks = <&rpmhcc RPMH_CXO_CLK>;
5181                         clock-names = "xo";
5182
5183                         power-domains = <&rpmhpd SM8250_LCX>,
5184                                         <&rpmhpd SM8250_LMX>;
5185                         power-domain-names = "lcx", "lmx";
5186
5187                         memory-region = <&adsp_mem>;
5188
5189                         qcom,qmp = <&aoss_qmp>;
5190
5191                         qcom,smem-states = <&smp2p_adsp_out 0>;
5192                         qcom,smem-state-names = "stop";
5193
5194                         status = "disabled";
5195
5196                         glink-edge {
5197                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5198                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
5199                                                              IRQ_TYPE_EDGE_RISING>;
5200                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
5201                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5202
5203                                 label = "lpass";
5204                                 qcom,remote-pid = <2>;
5205
5206                                 apr {
5207                                         compatible = "qcom,apr-v2";
5208                                         qcom,glink-channels = "apr_audio_svc";
5209                                         qcom,domain = <APR_DOMAIN_ADSP>;
5210                                         #address-cells = <1>;
5211                                         #size-cells = <0>;
5212
5213                                         service@3 {
5214                                                 reg = <APR_SVC_ADSP_CORE>;
5215                                                 compatible = "qcom,q6core";
5216                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5217                                         };
5218
5219                                         q6afe: service@4 {
5220                                                 compatible = "qcom,q6afe";
5221                                                 reg = <APR_SVC_AFE>;
5222                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5223                                                 q6afedai: dais {
5224                                                         compatible = "qcom,q6afe-dais";
5225                                                         #address-cells = <1>;
5226                                                         #size-cells = <0>;
5227                                                         #sound-dai-cells = <1>;
5228                                                 };
5229
5230                                                 q6afecc: clock-controller {
5231                                                         compatible = "qcom,q6afe-clocks";
5232                                                         #clock-cells = <2>;
5233                                                 };
5234                                         };
5235
5236                                         q6asm: service@7 {
5237                                                 compatible = "qcom,q6asm";
5238                                                 reg = <APR_SVC_ASM>;
5239                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5240                                                 q6asmdai: dais {
5241                                                         compatible = "qcom,q6asm-dais";
5242                                                         #address-cells = <1>;
5243                                                         #size-cells = <0>;
5244                                                         #sound-dai-cells = <1>;
5245                                                         iommus = <&apps_smmu 0x1801 0x0>;
5246                                                 };
5247                                         };
5248
5249                                         q6adm: service@8 {
5250                                                 compatible = "qcom,q6adm";
5251                                                 reg = <APR_SVC_ADM>;
5252                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5253                                                 q6routing: routing {
5254                                                         compatible = "qcom,q6adm-routing";
5255                                                         #sound-dai-cells = <0>;
5256                                                 };
5257                                         };
5258                                 };
5259
5260                                 fastrpc {
5261                                         compatible = "qcom,fastrpc";
5262                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
5263                                         label = "adsp";
5264                                         qcom,non-secure-domain;
5265                                         #address-cells = <1>;
5266                                         #size-cells = <0>;
5267
5268                                         compute-cb@3 {
5269                                                 compatible = "qcom,fastrpc-compute-cb";
5270                                                 reg = <3>;
5271                                                 iommus = <&apps_smmu 0x1803 0x0>;
5272                                         };
5273
5274                                         compute-cb@4 {
5275                                                 compatible = "qcom,fastrpc-compute-cb";
5276                                                 reg = <4>;
5277                                                 iommus = <&apps_smmu 0x1804 0x0>;
5278                                         };
5279
5280                                         compute-cb@5 {
5281                                                 compatible = "qcom,fastrpc-compute-cb";
5282                                                 reg = <5>;
5283                                                 iommus = <&apps_smmu 0x1805 0x0>;
5284                                         };
5285                                 };
5286                         };
5287                 };
5288
5289                 intc: interrupt-controller@17a00000 {
5290                         compatible = "arm,gic-v3";
5291                         #interrupt-cells = <3>;
5292                         interrupt-controller;
5293                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
5294                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
5295                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5296                 };
5297
5298                 watchdog@17c10000 {
5299                         compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
5300                         reg = <0 0x17c10000 0 0x1000>;
5301                         clocks = <&sleep_clk>;
5302                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
5303                 };
5304
5305                 timer@17c20000 {
5306                         #address-cells = <1>;
5307                         #size-cells = <1>;
5308                         ranges = <0 0 0 0x20000000>;
5309                         compatible = "arm,armv7-timer-mem";
5310                         reg = <0x0 0x17c20000 0x0 0x1000>;
5311                         clock-frequency = <19200000>;
5312
5313                         frame@17c21000 {
5314                                 frame-number = <0>;
5315                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
5316                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5317                                 reg = <0x17c21000 0x1000>,
5318                                       <0x17c22000 0x1000>;
5319                         };
5320
5321                         frame@17c23000 {
5322                                 frame-number = <1>;
5323                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5324                                 reg = <0x17c23000 0x1000>;
5325                                 status = "disabled";
5326                         };
5327
5328                         frame@17c25000 {
5329                                 frame-number = <2>;
5330                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5331                                 reg = <0x17c25000 0x1000>;
5332                                 status = "disabled";
5333                         };
5334
5335                         frame@17c27000 {
5336                                 frame-number = <3>;
5337                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5338                                 reg = <0x17c27000 0x1000>;
5339                                 status = "disabled";
5340                         };
5341
5342                         frame@17c29000 {
5343                                 frame-number = <4>;
5344                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5345                                 reg = <0x17c29000 0x1000>;
5346                                 status = "disabled";
5347                         };
5348
5349                         frame@17c2b000 {
5350                                 frame-number = <5>;
5351                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5352                                 reg = <0x17c2b000 0x1000>;
5353                                 status = "disabled";
5354                         };
5355
5356                         frame@17c2d000 {
5357                                 frame-number = <6>;
5358                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
5359                                 reg = <0x17c2d000 0x1000>;
5360                                 status = "disabled";
5361                         };
5362                 };
5363
5364                 apps_rsc: rsc@18200000 {
5365                         label = "apps_rsc";
5366                         compatible = "qcom,rpmh-rsc";
5367                         reg = <0x0 0x18200000 0x0 0x10000>,
5368                                 <0x0 0x18210000 0x0 0x10000>,
5369                                 <0x0 0x18220000 0x0 0x10000>;
5370                         reg-names = "drv-0", "drv-1", "drv-2";
5371                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5372                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5373                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5374                         qcom,tcs-offset = <0xd00>;
5375                         qcom,drv-id = <2>;
5376                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
5377                                           <WAKE_TCS    3>, <CONTROL_TCS 1>;
5378                         power-domains = <&CLUSTER_PD>;
5379
5380                         rpmhcc: clock-controller {
5381                                 compatible = "qcom,sm8250-rpmh-clk";
5382                                 #clock-cells = <1>;
5383                                 clock-names = "xo";
5384                                 clocks = <&xo_board>;
5385                         };
5386
5387                         rpmhpd: power-controller {
5388                                 compatible = "qcom,sm8250-rpmhpd";
5389                                 #power-domain-cells = <1>;
5390                                 operating-points-v2 = <&rpmhpd_opp_table>;
5391
5392                                 rpmhpd_opp_table: opp-table {
5393                                         compatible = "operating-points-v2";
5394
5395                                         rpmhpd_opp_ret: opp1 {
5396                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5397                                         };
5398
5399                                         rpmhpd_opp_min_svs: opp2 {
5400                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5401                                         };
5402
5403                                         rpmhpd_opp_low_svs: opp3 {
5404                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5405                                         };
5406
5407                                         rpmhpd_opp_svs: opp4 {
5408                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5409                                         };
5410
5411                                         rpmhpd_opp_svs_l1: opp5 {
5412                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5413                                         };
5414
5415                                         rpmhpd_opp_nom: opp6 {
5416                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5417                                         };
5418
5419                                         rpmhpd_opp_nom_l1: opp7 {
5420                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5421                                         };
5422
5423                                         rpmhpd_opp_nom_l2: opp8 {
5424                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5425                                         };
5426
5427                                         rpmhpd_opp_turbo: opp9 {
5428                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5429                                         };
5430
5431                                         rpmhpd_opp_turbo_l1: opp10 {
5432                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5433                                         };
5434                                 };
5435                         };
5436
5437                         apps_bcm_voter: bcm-voter {
5438                                 compatible = "qcom,bcm-voter";
5439                         };
5440                 };
5441
5442                 epss_l3: interconnect@18590000 {
5443                         compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3";
5444                         reg = <0 0x18590000 0 0x1000>;
5445
5446                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5447                         clock-names = "xo", "alternate";
5448
5449                         #interconnect-cells = <1>;
5450                 };
5451
5452                 cpufreq_hw: cpufreq@18591000 {
5453                         compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
5454                         reg = <0 0x18591000 0 0x1000>,
5455                               <0 0x18592000 0 0x1000>,
5456                               <0 0x18593000 0 0x1000>;
5457                         reg-names = "freq-domain0", "freq-domain1",
5458                                     "freq-domain2";
5459
5460                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5461                         clock-names = "xo", "alternate";
5462                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
5463                                      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
5464                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
5465                         interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
5466                         #freq-domain-cells = <1>;
5467                 };
5468         };
5469
5470         timer {
5471                 compatible = "arm,armv8-timer";
5472                 interrupts = <GIC_PPI 13
5473                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5474                              <GIC_PPI 14
5475                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5476                              <GIC_PPI 11
5477                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5478                              <GIC_PPI 10
5479                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5480         };
5481
5482         thermal-zones {
5483                 cpu0-thermal {
5484                         polling-delay-passive = <250>;
5485                         polling-delay = <1000>;
5486
5487                         thermal-sensors = <&tsens0 1>;
5488
5489                         trips {
5490                                 cpu0_alert0: trip-point0 {
5491                                         temperature = <90000>;
5492                                         hysteresis = <2000>;
5493                                         type = "passive";
5494                                 };
5495
5496                                 cpu0_alert1: trip-point1 {
5497                                         temperature = <95000>;
5498                                         hysteresis = <2000>;
5499                                         type = "passive";
5500                                 };
5501
5502                                 cpu0_crit: cpu_crit {
5503                                         temperature = <110000>;
5504                                         hysteresis = <1000>;
5505                                         type = "critical";
5506                                 };
5507                         };
5508
5509                         cooling-maps {
5510                                 map0 {
5511                                         trip = <&cpu0_alert0>;
5512                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5513                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5514                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5515                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5516                                 };
5517                                 map1 {
5518                                         trip = <&cpu0_alert1>;
5519                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5520                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5521                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5522                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5523                                 };
5524                         };
5525                 };
5526
5527                 cpu1-thermal {
5528                         polling-delay-passive = <250>;
5529                         polling-delay = <1000>;
5530
5531                         thermal-sensors = <&tsens0 2>;
5532
5533                         trips {
5534                                 cpu1_alert0: trip-point0 {
5535                                         temperature = <90000>;
5536                                         hysteresis = <2000>;
5537                                         type = "passive";
5538                                 };
5539
5540                                 cpu1_alert1: trip-point1 {
5541                                         temperature = <95000>;
5542                                         hysteresis = <2000>;
5543                                         type = "passive";
5544                                 };
5545
5546                                 cpu1_crit: cpu_crit {
5547                                         temperature = <110000>;
5548                                         hysteresis = <1000>;
5549                                         type = "critical";
5550                                 };
5551                         };
5552
5553                         cooling-maps {
5554                                 map0 {
5555                                         trip = <&cpu1_alert0>;
5556                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5557                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5558                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5559                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5560                                 };
5561                                 map1 {
5562                                         trip = <&cpu1_alert1>;
5563                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5564                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5565                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5566                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5567                                 };
5568                         };
5569                 };
5570
5571                 cpu2-thermal {
5572                         polling-delay-passive = <250>;
5573                         polling-delay = <1000>;
5574
5575                         thermal-sensors = <&tsens0 3>;
5576
5577                         trips {
5578                                 cpu2_alert0: trip-point0 {
5579                                         temperature = <90000>;
5580                                         hysteresis = <2000>;
5581                                         type = "passive";
5582                                 };
5583
5584                                 cpu2_alert1: trip-point1 {
5585                                         temperature = <95000>;
5586                                         hysteresis = <2000>;
5587                                         type = "passive";
5588                                 };
5589
5590                                 cpu2_crit: cpu_crit {
5591                                         temperature = <110000>;
5592                                         hysteresis = <1000>;
5593                                         type = "critical";
5594                                 };
5595                         };
5596
5597                         cooling-maps {
5598                                 map0 {
5599                                         trip = <&cpu2_alert0>;
5600                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5601                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5602                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5603                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5604                                 };
5605                                 map1 {
5606                                         trip = <&cpu2_alert1>;
5607                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5608                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5609                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5610                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5611                                 };
5612                         };
5613                 };
5614
5615                 cpu3-thermal {
5616                         polling-delay-passive = <250>;
5617                         polling-delay = <1000>;
5618
5619                         thermal-sensors = <&tsens0 4>;
5620
5621                         trips {
5622                                 cpu3_alert0: trip-point0 {
5623                                         temperature = <90000>;
5624                                         hysteresis = <2000>;
5625                                         type = "passive";
5626                                 };
5627
5628                                 cpu3_alert1: trip-point1 {
5629                                         temperature = <95000>;
5630                                         hysteresis = <2000>;
5631                                         type = "passive";
5632                                 };
5633
5634                                 cpu3_crit: cpu_crit {
5635                                         temperature = <110000>;
5636                                         hysteresis = <1000>;
5637                                         type = "critical";
5638                                 };
5639                         };
5640
5641                         cooling-maps {
5642                                 map0 {
5643                                         trip = <&cpu3_alert0>;
5644                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5645                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5646                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5647                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5648                                 };
5649                                 map1 {
5650                                         trip = <&cpu3_alert1>;
5651                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5652                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5653                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5654                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5655                                 };
5656                         };
5657                 };
5658
5659                 cpu4-top-thermal {
5660                         polling-delay-passive = <250>;
5661                         polling-delay = <1000>;
5662
5663                         thermal-sensors = <&tsens0 7>;
5664
5665                         trips {
5666                                 cpu4_top_alert0: trip-point0 {
5667                                         temperature = <90000>;
5668                                         hysteresis = <2000>;
5669                                         type = "passive";
5670                                 };
5671
5672                                 cpu4_top_alert1: trip-point1 {
5673                                         temperature = <95000>;
5674                                         hysteresis = <2000>;
5675                                         type = "passive";
5676                                 };
5677
5678                                 cpu4_top_crit: cpu_crit {
5679                                         temperature = <110000>;
5680                                         hysteresis = <1000>;
5681                                         type = "critical";
5682                                 };
5683                         };
5684
5685                         cooling-maps {
5686                                 map0 {
5687                                         trip = <&cpu4_top_alert0>;
5688                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5689                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5690                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5691                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5692                                 };
5693                                 map1 {
5694                                         trip = <&cpu4_top_alert1>;
5695                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5696                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5697                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5698                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5699                                 };
5700                         };
5701                 };
5702
5703                 cpu5-top-thermal {
5704                         polling-delay-passive = <250>;
5705                         polling-delay = <1000>;
5706
5707                         thermal-sensors = <&tsens0 8>;
5708
5709                         trips {
5710                                 cpu5_top_alert0: trip-point0 {
5711                                         temperature = <90000>;
5712                                         hysteresis = <2000>;
5713                                         type = "passive";
5714                                 };
5715
5716                                 cpu5_top_alert1: trip-point1 {
5717                                         temperature = <95000>;
5718                                         hysteresis = <2000>;
5719                                         type = "passive";
5720                                 };
5721
5722                                 cpu5_top_crit: cpu_crit {
5723                                         temperature = <110000>;
5724                                         hysteresis = <1000>;
5725                                         type = "critical";
5726                                 };
5727                         };
5728
5729                         cooling-maps {
5730                                 map0 {
5731                                         trip = <&cpu5_top_alert0>;
5732                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5733                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5734                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5735                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5736                                 };
5737                                 map1 {
5738                                         trip = <&cpu5_top_alert1>;
5739                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5740                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5741                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5742                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5743                                 };
5744                         };
5745                 };
5746
5747                 cpu6-top-thermal {
5748                         polling-delay-passive = <250>;
5749                         polling-delay = <1000>;
5750
5751                         thermal-sensors = <&tsens0 9>;
5752
5753                         trips {
5754                                 cpu6_top_alert0: trip-point0 {
5755                                         temperature = <90000>;
5756                                         hysteresis = <2000>;
5757                                         type = "passive";
5758                                 };
5759
5760                                 cpu6_top_alert1: trip-point1 {
5761                                         temperature = <95000>;
5762                                         hysteresis = <2000>;
5763                                         type = "passive";
5764                                 };
5765
5766                                 cpu6_top_crit: cpu_crit {
5767                                         temperature = <110000>;
5768                                         hysteresis = <1000>;
5769                                         type = "critical";
5770                                 };
5771                         };
5772
5773                         cooling-maps {
5774                                 map0 {
5775                                         trip = <&cpu6_top_alert0>;
5776                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5777                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5778                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5779                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5780                                 };
5781                                 map1 {
5782                                         trip = <&cpu6_top_alert1>;
5783                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5784                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5785                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5786                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5787                                 };
5788                         };
5789                 };
5790
5791                 cpu7-top-thermal {
5792                         polling-delay-passive = <250>;
5793                         polling-delay = <1000>;
5794
5795                         thermal-sensors = <&tsens0 10>;
5796
5797                         trips {
5798                                 cpu7_top_alert0: trip-point0 {
5799                                         temperature = <90000>;
5800                                         hysteresis = <2000>;
5801                                         type = "passive";
5802                                 };
5803
5804                                 cpu7_top_alert1: trip-point1 {
5805                                         temperature = <95000>;
5806                                         hysteresis = <2000>;
5807                                         type = "passive";
5808                                 };
5809
5810                                 cpu7_top_crit: cpu_crit {
5811                                         temperature = <110000>;
5812                                         hysteresis = <1000>;
5813                                         type = "critical";
5814                                 };
5815                         };
5816
5817                         cooling-maps {
5818                                 map0 {
5819                                         trip = <&cpu7_top_alert0>;
5820                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5821                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5822                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5823                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5824                                 };
5825                                 map1 {
5826                                         trip = <&cpu7_top_alert1>;
5827                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5828                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5829                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5830                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5831                                 };
5832                         };
5833                 };
5834
5835                 cpu4-bottom-thermal {
5836                         polling-delay-passive = <250>;
5837                         polling-delay = <1000>;
5838
5839                         thermal-sensors = <&tsens0 11>;
5840
5841                         trips {
5842                                 cpu4_bottom_alert0: trip-point0 {
5843                                         temperature = <90000>;
5844                                         hysteresis = <2000>;
5845                                         type = "passive";
5846                                 };
5847
5848                                 cpu4_bottom_alert1: trip-point1 {
5849                                         temperature = <95000>;
5850                                         hysteresis = <2000>;
5851                                         type = "passive";
5852                                 };
5853
5854                                 cpu4_bottom_crit: cpu_crit {
5855                                         temperature = <110000>;
5856                                         hysteresis = <1000>;
5857                                         type = "critical";
5858                                 };
5859                         };
5860
5861                         cooling-maps {
5862                                 map0 {
5863                                         trip = <&cpu4_bottom_alert0>;
5864                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5865                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5866                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5867                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5868                                 };
5869                                 map1 {
5870                                         trip = <&cpu4_bottom_alert1>;
5871                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5872                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5873                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5874                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5875                                 };
5876                         };
5877                 };
5878
5879                 cpu5-bottom-thermal {
5880                         polling-delay-passive = <250>;
5881                         polling-delay = <1000>;
5882
5883                         thermal-sensors = <&tsens0 12>;
5884
5885                         trips {
5886                                 cpu5_bottom_alert0: trip-point0 {
5887                                         temperature = <90000>;
5888                                         hysteresis = <2000>;
5889                                         type = "passive";
5890                                 };
5891
5892                                 cpu5_bottom_alert1: trip-point1 {
5893                                         temperature = <95000>;
5894                                         hysteresis = <2000>;
5895                                         type = "passive";
5896                                 };
5897
5898                                 cpu5_bottom_crit: cpu_crit {
5899                                         temperature = <110000>;
5900                                         hysteresis = <1000>;
5901                                         type = "critical";
5902                                 };
5903                         };
5904
5905                         cooling-maps {
5906                                 map0 {
5907                                         trip = <&cpu5_bottom_alert0>;
5908                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5909                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5910                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5911                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5912                                 };
5913                                 map1 {
5914                                         trip = <&cpu5_bottom_alert1>;
5915                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5916                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5917                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5918                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5919                                 };
5920                         };
5921                 };
5922
5923                 cpu6-bottom-thermal {
5924                         polling-delay-passive = <250>;
5925                         polling-delay = <1000>;
5926
5927                         thermal-sensors = <&tsens0 13>;
5928
5929                         trips {
5930                                 cpu6_bottom_alert0: trip-point0 {
5931                                         temperature = <90000>;
5932                                         hysteresis = <2000>;
5933                                         type = "passive";
5934                                 };
5935
5936                                 cpu6_bottom_alert1: trip-point1 {
5937                                         temperature = <95000>;
5938                                         hysteresis = <2000>;
5939                                         type = "passive";
5940                                 };
5941
5942                                 cpu6_bottom_crit: cpu_crit {
5943                                         temperature = <110000>;
5944                                         hysteresis = <1000>;
5945                                         type = "critical";
5946                                 };
5947                         };
5948
5949                         cooling-maps {
5950                                 map0 {
5951                                         trip = <&cpu6_bottom_alert0>;
5952                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5953                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5954                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5955                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5956                                 };
5957                                 map1 {
5958                                         trip = <&cpu6_bottom_alert1>;
5959                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5960                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5961                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5962                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5963                                 };
5964                         };
5965                 };
5966
5967                 cpu7-bottom-thermal {
5968                         polling-delay-passive = <250>;
5969                         polling-delay = <1000>;
5970
5971                         thermal-sensors = <&tsens0 14>;
5972
5973                         trips {
5974                                 cpu7_bottom_alert0: trip-point0 {
5975                                         temperature = <90000>;
5976                                         hysteresis = <2000>;
5977                                         type = "passive";
5978                                 };
5979
5980                                 cpu7_bottom_alert1: trip-point1 {
5981                                         temperature = <95000>;
5982                                         hysteresis = <2000>;
5983                                         type = "passive";
5984                                 };
5985
5986                                 cpu7_bottom_crit: cpu_crit {
5987                                         temperature = <110000>;
5988                                         hysteresis = <1000>;
5989                                         type = "critical";
5990                                 };
5991                         };
5992
5993                         cooling-maps {
5994                                 map0 {
5995                                         trip = <&cpu7_bottom_alert0>;
5996                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5997                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5998                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5999                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6000                                 };
6001                                 map1 {
6002                                         trip = <&cpu7_bottom_alert1>;
6003                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6004                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6005                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6006                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6007                                 };
6008                         };
6009                 };
6010
6011                 aoss0-thermal {
6012                         polling-delay-passive = <250>;
6013                         polling-delay = <1000>;
6014
6015                         thermal-sensors = <&tsens0 0>;
6016
6017                         trips {
6018                                 aoss0_alert0: trip-point0 {
6019                                         temperature = <90000>;
6020                                         hysteresis = <2000>;
6021                                         type = "hot";
6022                                 };
6023                         };
6024                 };
6025
6026                 cluster0-thermal {
6027                         polling-delay-passive = <250>;
6028                         polling-delay = <1000>;
6029
6030                         thermal-sensors = <&tsens0 5>;
6031
6032                         trips {
6033                                 cluster0_alert0: trip-point0 {
6034                                         temperature = <90000>;
6035                                         hysteresis = <2000>;
6036                                         type = "hot";
6037                                 };
6038                                 cluster0_crit: cluster0_crit {
6039                                         temperature = <110000>;
6040                                         hysteresis = <2000>;
6041                                         type = "critical";
6042                                 };
6043                         };
6044                 };
6045
6046                 cluster1-thermal {
6047                         polling-delay-passive = <250>;
6048                         polling-delay = <1000>;
6049
6050                         thermal-sensors = <&tsens0 6>;
6051
6052                         trips {
6053                                 cluster1_alert0: trip-point0 {
6054                                         temperature = <90000>;
6055                                         hysteresis = <2000>;
6056                                         type = "hot";
6057                                 };
6058                                 cluster1_crit: cluster1_crit {
6059                                         temperature = <110000>;
6060                                         hysteresis = <2000>;
6061                                         type = "critical";
6062                                 };
6063                         };
6064                 };
6065
6066                 gpu-top-thermal {
6067                         polling-delay-passive = <250>;
6068                         polling-delay = <1000>;
6069
6070                         thermal-sensors = <&tsens0 15>;
6071
6072                         trips {
6073                                 gpu1_alert0: trip-point0 {
6074                                         temperature = <90000>;
6075                                         hysteresis = <2000>;
6076                                         type = "hot";
6077                                 };
6078                         };
6079                 };
6080
6081                 aoss1-thermal {
6082                         polling-delay-passive = <250>;
6083                         polling-delay = <1000>;
6084
6085                         thermal-sensors = <&tsens1 0>;
6086
6087                         trips {
6088                                 aoss1_alert0: trip-point0 {
6089                                         temperature = <90000>;
6090                                         hysteresis = <2000>;
6091                                         type = "hot";
6092                                 };
6093                         };
6094                 };
6095
6096                 wlan-thermal {
6097                         polling-delay-passive = <250>;
6098                         polling-delay = <1000>;
6099
6100                         thermal-sensors = <&tsens1 1>;
6101
6102                         trips {
6103                                 wlan_alert0: trip-point0 {
6104                                         temperature = <90000>;
6105                                         hysteresis = <2000>;
6106                                         type = "hot";
6107                                 };
6108                         };
6109                 };
6110
6111                 video-thermal {
6112                         polling-delay-passive = <250>;
6113                         polling-delay = <1000>;
6114
6115                         thermal-sensors = <&tsens1 2>;
6116
6117                         trips {
6118                                 video_alert0: trip-point0 {
6119                                         temperature = <90000>;
6120                                         hysteresis = <2000>;
6121                                         type = "hot";
6122                                 };
6123                         };
6124                 };
6125
6126                 mem-thermal {
6127                         polling-delay-passive = <250>;
6128                         polling-delay = <1000>;
6129
6130                         thermal-sensors = <&tsens1 3>;
6131
6132                         trips {
6133                                 mem_alert0: trip-point0 {
6134                                         temperature = <90000>;
6135                                         hysteresis = <2000>;
6136                                         type = "hot";
6137                                 };
6138                         };
6139                 };
6140
6141                 q6-hvx-thermal {
6142                         polling-delay-passive = <250>;
6143                         polling-delay = <1000>;
6144
6145                         thermal-sensors = <&tsens1 4>;
6146
6147                         trips {
6148                                 q6_hvx_alert0: trip-point0 {
6149                                         temperature = <90000>;
6150                                         hysteresis = <2000>;
6151                                         type = "hot";
6152                                 };
6153                         };
6154                 };
6155
6156                 camera-thermal {
6157                         polling-delay-passive = <250>;
6158                         polling-delay = <1000>;
6159
6160                         thermal-sensors = <&tsens1 5>;
6161
6162                         trips {
6163                                 camera_alert0: trip-point0 {
6164                                         temperature = <90000>;
6165                                         hysteresis = <2000>;
6166                                         type = "hot";
6167                                 };
6168                         };
6169                 };
6170
6171                 compute-thermal {
6172                         polling-delay-passive = <250>;
6173                         polling-delay = <1000>;
6174
6175                         thermal-sensors = <&tsens1 6>;
6176
6177                         trips {
6178                                 compute_alert0: trip-point0 {
6179                                         temperature = <90000>;
6180                                         hysteresis = <2000>;
6181                                         type = "hot";
6182                                 };
6183                         };
6184                 };
6185
6186                 npu-thermal {
6187                         polling-delay-passive = <250>;
6188                         polling-delay = <1000>;
6189
6190                         thermal-sensors = <&tsens1 7>;
6191
6192                         trips {
6193                                 npu_alert0: trip-point0 {
6194                                         temperature = <90000>;
6195                                         hysteresis = <2000>;
6196                                         type = "hot";
6197                                 };
6198                         };
6199                 };
6200
6201                 gpu-bottom-thermal {
6202                         polling-delay-passive = <250>;
6203                         polling-delay = <1000>;
6204
6205                         thermal-sensors = <&tsens1 8>;
6206
6207                         trips {
6208                                 gpu2_alert0: trip-point0 {
6209                                         temperature = <90000>;
6210                                         hysteresis = <2000>;
6211                                         type = "hot";
6212                                 };
6213                         };
6214                 };
6215         };
6216 };