src/arm64/renesas/r8a77980-condor.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the Condor board
   4  *
   5  * Copyright (C) 2018 Renesas Electronics Corp.
   6  * Copyright (C) 2018 Cogent Embedded, Inc.
   7  */
   8
   9 /dts-v1/;
  10 #include "r8a77980.dtsi"
  11
  12 / {
  13         model = "Renesas Condor board based on r8a77980";
  14         compatible = "renesas,condor", "renesas,r8a77980";
  15
  16         aliases {
  17                 serial0 = &scif0;
  18                 ethernet0 = &avb;
  19         };
  20
  21         chosen {
  22                 stdout-path = "serial0:115200n8";
  23         };
  24
  25         memory@48000000 {
  26                 device_type = "memory";
  27                 /* first 128MB is reserved for secure area. */
  28                 reg = <0 0x48000000 0 0x78000000>;
  29         };
  30
  31         d3_3v: regulator-0 {
  32                 compatible = "regulator-fixed";
  33                 regulator-name = "D3.3V";
  34                 regulator-min-microvolt = <3300000>;
  35                 regulator-max-microvolt = <3300000>;
  36                 regulator-boot-on;
  37                 regulator-always-on;
  38         };
  39
  40         vddq_vin01: regulator-1 {
  41                 compatible = "regulator-fixed";
  42                 regulator-name = "VDDQ_VIN01";
  43                 regulator-min-microvolt = <1800000>;
  44                 regulator-max-microvolt = <1800000>;
  45                 regulator-boot-on;
  46                 regulator-always-on;
  47         };
  48 };
  49
  50 &avb {
  51         pinctrl-0 = <&avb_pins>;
  52         pinctrl-names = "default";
  53
  54         phy-mode = "rgmii-id";
  55         phy-handle = <&phy0>;
  56         renesas,no-ether-link;
  57         status = "okay";
  58
  59         phy0: ethernet-phy@0 {
  60                 rxc-skew-ps = <1500>;
  61                 reg = <0>;
  62         };
  63 };
  64
  65 &canfd {
  66         pinctrl-0 = <&canfd0_pins>;
  67         pinctrl-names = "default";
  68         status = "okay";
  69
  70         channel0 {
  71                 status = "okay";
  72         };
  73 };
  74
  75 &extal_clk {
  76         clock-frequency = <16666666>;
  77 };
  78
  79 &extalr_clk {
  80         clock-frequency = <32768>;
  81 };
  82
  83 &mmc0 {
  84         pinctrl-0 = <&mmc_pins>;
  85         pinctrl-1 = <&mmc_pins_uhs>;
  86         pinctrl-names = "default", "state_uhs";
  87
  88         vmmc-supply = <&d3_3v>;
  89         vqmmc-supply = <&vddq_vin01>;
  90         mmc-hs200-1_8v;
  91         bus-width = <8>;
  92         non-removable;
  93         status = "okay";
  94 };
  95
  96 &pfc {
  97         avb_pins: avb {
  98                 groups = "avb_mdio", "avb_rgmii";
  99                 function = "avb";
 100         };
 101
 102         canfd0_pins: canfd0 {
 103                 groups = "canfd0_data_a";
 104                 function = "canfd0";
 105         };
 106
 107         mmc_pins: mmc {
 108                 groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
 109                 function = "mmc";
 110                 power-source = <3300>;
 111         };
 112
 113         mmc_pins_uhs: mmc_uhs {
 114                 groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
 115                 function = "mmc";
 116                 power-source = <1800>;
 117         };
 118
 119         scif0_pins: scif0 {
 120                 groups = "scif0_data";
 121                 function = "scif0";
 122         };
 123
 124         scif_clk_pins: scif_clk {
 125                 groups = "scif_clk_b";
 126                 function = "scif_clk";
 127         };
 128 };
 129
 130 &scif0 {
 131         pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
 132         pinctrl-names = "default";
 133
 134         status = "okay";
 135 };
 136
 137 &scif_clk {
 138         clock-frequency = <14745600>;
 139 };