src/arm64/renesas/r9a07g044.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 /*
   3  * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
   4  *
   5  * Copyright (C) 2021 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/r9a07g044-cpg.h>
  10
  11 / {
  12         compatible = "renesas,r9a07g044";
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         audio_clk1: audio1-clk {
  17                 compatible = "fixed-clock";
  18                 #clock-cells = <0>;
  19                 /* This value must be overridden by boards that provide it */
  20                 clock-frequency = <0>;
  21         };
  22
  23         audio_clk2: audio2-clk {
  24                 compatible = "fixed-clock";
  25                 #clock-cells = <0>;
  26                 /* This value must be overridden by boards that provide it */
  27                 clock-frequency = <0>;
  28         };
  29
  30         /* External CAN clock - to be overridden by boards that provide it */
  31         can_clk: can-clk {
  32                 compatible = "fixed-clock";
  33                 #clock-cells = <0>;
  34                 clock-frequency = <0>;
  35         };
  36
  37         /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
  38         extal_clk: extal-clk {
  39                 compatible = "fixed-clock";
  40                 #clock-cells = <0>;
  41                 /* This value must be overridden by the board */
  42                 clock-frequency = <0>;
  43         };
  44
  45         cluster0_opp: opp-table-0 {
  46                 compatible = "operating-points-v2";
  47                 opp-shared;
  48
  49                 opp-150000000 {
  50                         opp-hz = /bits/ 64 <150000000>;
  51                         opp-microvolt = <1100000>;
  52                         clock-latency-ns = <300000>;
  53                 };
  54                 opp-300000000 {
  55                         opp-hz = /bits/ 64 <300000000>;
  56                         opp-microvolt = <1100000>;
  57                         clock-latency-ns = <300000>;
  58                 };
  59                 opp-600000000 {
  60                         opp-hz = /bits/ 64 <600000000>;
  61                         opp-microvolt = <1100000>;
  62                         clock-latency-ns = <300000>;
  63                 };
  64                 opp-1200000000 {
  65                         opp-hz = /bits/ 64 <1200000000>;
  66                         opp-microvolt = <1100000>;
  67                         clock-latency-ns = <300000>;
  68                         opp-suspend;
  69                 };
  70         };
  71
  72         cpus {
  73                 #address-cells = <1>;
  74                 #size-cells = <0>;
  75
  76                 cpu-map {
  77                         cluster0 {
  78                                 core0 {
  79                                         cpu = <&cpu0>;
  80                                 };
  81                                 core1 {
  82                                         cpu = <&cpu1>;
  83                                 };
  84                         };
  85                 };
  86
  87                 cpu0: cpu@0 {
  88                         compatible = "arm,cortex-a55";
  89                         reg = <0>;
  90                         device_type = "cpu";
  91                         #cooling-cells = <2>;
  92                         next-level-cache = <&L3_CA55>;
  93                         enable-method = "psci";
  94                         clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
  95                         operating-points-v2 = <&cluster0_opp>;
  96                 };
  97
  98                 cpu1: cpu@100 {
  99                         compatible = "arm,cortex-a55";
 100                         reg = <0x100>;
 101                         device_type = "cpu";
 102                         next-level-cache = <&L3_CA55>;
 103                         enable-method = "psci";
 104                         clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
 105                         operating-points-v2 = <&cluster0_opp>;
 106                 };
 107
 108                 L3_CA55: cache-controller-0 {
 109                         compatible = "cache";
 110                         cache-unified;
 111                         cache-size = <0x40000>;
 112                         cache-level = <3>;
 113                 };
 114         };
 115
 116         gpu_opp_table: opp-table-1 {
 117                 compatible = "operating-points-v2";
 118
 119                 opp-500000000 {
 120                         opp-hz = /bits/ 64 <500000000>;
 121                         opp-microvolt = <1100000>;
 122                 };
 123
 124                 opp-400000000 {
 125                         opp-hz = /bits/ 64 <400000000>;
 126                         opp-microvolt = <1100000>;
 127                 };
 128
 129                 opp-250000000 {
 130                         opp-hz = /bits/ 64 <250000000>;
 131                         opp-microvolt = <1100000>;
 132                 };
 133
 134                 opp-200000000 {
 135                         opp-hz = /bits/ 64 <200000000>;
 136                         opp-microvolt = <1100000>;
 137                 };
 138
 139                 opp-125000000 {
 140                         opp-hz = /bits/ 64 <125000000>;
 141                         opp-microvolt = <1100000>;
 142                 };
 143
 144                 opp-100000000 {
 145                         opp-hz = /bits/ 64 <100000000>;
 146                         opp-microvolt = <1100000>;
 147                 };
 148
 149                 opp-62500000 {
 150                         opp-hz = /bits/ 64 <62500000>;
 151                         opp-microvolt = <1100000>;
 152                 };
 153
 154                 opp-50000000 {
 155                         opp-hz = /bits/ 64 <50000000>;
 156                         opp-microvolt = <1100000>;
 157                 };
 158         };
 159
 160         psci {
 161                 compatible = "arm,psci-1.0", "arm,psci-0.2";
 162                 method = "smc";
 163         };
 164
 165         soc: soc {
 166                 compatible = "simple-bus";
 167                 interrupt-parent = <&gic>;
 168                 #address-cells = <2>;
 169                 #size-cells = <2>;
 170                 ranges;
 171
 172                 ssi0: ssi@10049c00 {
 173                         compatible = "renesas,r9a07g044-ssi",
 174                                      "renesas,rz-ssi";
 175                         reg = <0 0x10049c00 0 0x400>;
 176                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
 177                                      <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
 178                                      <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
 179                                      <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
 180                         interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
 181                         clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
 182                                  <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
 183                                  <&audio_clk1>, <&audio_clk2>;
 184                         clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
 185                         resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
 186                         dmas = <&dmac 0x2655>, <&dmac 0x2656>;
 187                         dma-names = "tx", "rx";
 188                         power-domains = <&cpg>;
 189                         #sound-dai-cells = <0>;
 190                         status = "disabled";
 191                 };
 192
 193                 ssi1: ssi@1004a000 {
 194                         compatible = "renesas,r9a07g044-ssi",
 195                                      "renesas,rz-ssi";
 196                         reg = <0 0x1004a000 0 0x400>;
 197                         interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
 198                                      <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
 199                                      <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
 200                                      <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
 201                         interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
 202                         clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,
 203                                  <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,
 204                                  <&audio_clk1>, <&audio_clk2>;
 205                         clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
 206                         resets = <&cpg R9A07G044_SSI1_RST_M2_REG>;
 207                         dmas = <&dmac 0x2659>, <&dmac 0x265a>;
 208                         dma-names = "tx", "rx";
 209                         power-domains = <&cpg>;
 210                         #sound-dai-cells = <0>;
 211                         status = "disabled";
 212                 };
 213
 214                 ssi2: ssi@1004a400 {
 215                         compatible = "renesas,r9a07g044-ssi",
 216                                      "renesas,rz-ssi";
 217                         reg = <0 0x1004a400 0 0x400>;
 218                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
 219                                      <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
 220                                      <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
 221                                      <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
 222                         interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
 223                         clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>,
 224                                  <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>,
 225                                  <&audio_clk1>, <&audio_clk2>;
 226                         clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
 227                         resets = <&cpg R9A07G044_SSI2_RST_M2_REG>;
 228                         dmas = <&dmac 0x265f>;
 229                         dma-names = "rt";
 230                         power-domains = <&cpg>;
 231                         #sound-dai-cells = <0>;
 232                         status = "disabled";
 233                 };
 234
 235                 ssi3: ssi@1004a800 {
 236                         compatible = "renesas,r9a07g044-ssi",
 237                                      "renesas,rz-ssi";
 238                         reg = <0 0x1004a800 0 0x400>;
 239                         interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
 240                                      <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
 241                                      <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
 242                                      <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
 243                         interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
 244                         clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>,
 245                                  <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>,
 246                                  <&audio_clk1>, <&audio_clk2>;
 247                         clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
 248                         resets = <&cpg R9A07G044_SSI3_RST_M2_REG>;
 249                         dmas = <&dmac 0x2661>, <&dmac 0x2662>;
 250                         dma-names = "tx", "rx";
 251                         power-domains = <&cpg>;
 252                         #sound-dai-cells = <0>;
 253                         status = "disabled";
 254                 };
 255
 256                 spi0: spi@1004ac00 {
 257                         compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
 258                         reg = <0 0x1004ac00 0 0x400>;
 259                         interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
 260                                      <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
 261                                      <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
 262                         interrupt-names = "error", "rx", "tx";
 263                         clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>;
 264                         resets = <&cpg R9A07G044_RSPI0_RST>;
 265                         dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
 266                         dma-names = "tx", "rx";
 267                         power-domains = <&cpg>;
 268                         num-cs = <1>;
 269                         #address-cells = <1>;
 270                         #size-cells = <0>;
 271                         status = "disabled";
 272                 };
 273
 274                 spi1: spi@1004b000 {
 275                         compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
 276                         reg = <0 0x1004b000 0 0x400>;
 277                         interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
 278                                      <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
 279                                      <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
 280                         interrupt-names = "error", "rx", "tx";
 281                         clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>;
 282                         resets = <&cpg R9A07G044_RSPI1_RST>;
 283                         dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
 284                         dma-names = "tx", "rx";
 285                         power-domains = <&cpg>;
 286                         num-cs = <1>;
 287                         #address-cells = <1>;
 288                         #size-cells = <0>;
 289                         status = "disabled";
 290                 };
 291
 292                 spi2: spi@1004b400 {
 293                         compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
 294                         reg = <0 0x1004b400 0 0x400>;
 295                         interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
 296                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
 297                                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
 298                         interrupt-names = "error", "rx", "tx";
 299                         clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>;
 300                         resets = <&cpg R9A07G044_RSPI2_RST>;
 301                         dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
 302                         dma-names = "tx", "rx";
 303                         power-domains = <&cpg>;
 304                         num-cs = <1>;
 305                         #address-cells = <1>;
 306                         #size-cells = <0>;
 307                         status = "disabled";
 308                 };
 309
 310                 scif0: serial@1004b800 {
 311                         compatible = "renesas,scif-r9a07g044";
 312                         reg = <0 0x1004b800 0 0x400>;
 313                         interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
 314                                      <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
 315                                      <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
 316                                      <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
 317                                      <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
 318                                      <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
 319                         interrupt-names = "eri", "rxi", "txi",
 320                                           "bri", "dri", "tei";
 321                         clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
 322                         clock-names = "fck";
 323                         power-domains = <&cpg>;
 324                         resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
 325                         status = "disabled";
 326                 };
 327
 328                 scif1: serial@1004bc00 {
 329                         compatible = "renesas,scif-r9a07g044";
 330                         reg = <0 0x1004bc00 0 0x400>;
 331                         interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
 332                                      <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
 333                                      <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
 334                                      <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
 335                                      <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
 336                                      <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
 337                         interrupt-names = "eri", "rxi", "txi",
 338                                           "bri", "dri", "tei";
 339                         clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>;
 340                         clock-names = "fck";
 341                         power-domains = <&cpg>;
 342                         resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>;
 343                         status = "disabled";
 344                 };
 345
 346                 scif2: serial@1004c000 {
 347                         compatible = "renesas,scif-r9a07g044";
 348                         reg = <0 0x1004c000 0 0x400>;
 349                         interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
 350                                      <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
 351                                      <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
 352                                      <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
 353                                      <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
 354                                      <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
 355                         interrupt-names = "eri", "rxi", "txi",
 356                                           "bri", "dri", "tei";
 357                         clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>;
 358                         clock-names = "fck";
 359                         power-domains = <&cpg>;
 360                         resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>;
 361                         status = "disabled";
 362                 };
 363
 364                 scif3: serial@1004c400 {
 365                         compatible = "renesas,scif-r9a07g044";
 366                         reg = <0 0x1004c400 0 0x400>;
 367                         interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
 368                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
 369                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
 370                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
 371                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
 372                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
 373                         interrupt-names = "eri", "rxi", "txi",
 374                                           "bri", "dri", "tei";
 375                         clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>;
 376                         clock-names = "fck";
 377                         power-domains = <&cpg>;
 378                         resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>;
 379                         status = "disabled";
 380                 };
 381
 382                 scif4: serial@1004c800 {
 383                         compatible = "renesas,scif-r9a07g044";
 384                         reg = <0 0x1004c800 0 0x400>;
 385                         interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
 386                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
 387                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
 388                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
 389                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
 390                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
 391                         interrupt-names = "eri", "rxi", "txi",
 392                                           "bri", "dri", "tei";
 393                         clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>;
 394                         clock-names = "fck";
 395                         power-domains = <&cpg>;
 396                         resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>;
 397                         status = "disabled";
 398                 };
 399
 400                 sci0: serial@1004d000 {
 401                         compatible = "renesas,r9a07g044-sci", "renesas,sci";
 402                         reg = <0 0x1004d000 0 0x400>;
 403                         interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
 404                                      <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
 405                                      <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
 406                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
 407                         interrupt-names = "eri", "rxi", "txi", "tei";
 408                         clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
 409                         clock-names = "fck";
 410                         power-domains = <&cpg>;
 411                         resets = <&cpg R9A07G044_SCI0_RST>;
 412                         status = "disabled";
 413                 };
 414
 415                 sci1: serial@1004d400 {
 416                         compatible = "renesas,r9a07g044-sci", "renesas,sci";
 417                         reg = <0 0x1004d400 0 0x400>;
 418                         interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
 419                                      <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
 420                                      <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
 421                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
 422                         interrupt-names = "eri", "rxi", "txi", "tei";
 423                         clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>;
 424                         clock-names = "fck";
 425                         power-domains = <&cpg>;
 426                         resets = <&cpg R9A07G044_SCI1_RST>;
 427                         status = "disabled";
 428                 };
 429
 430                 canfd: can@10050000 {
 431                         compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
 432                         reg = <0 0x10050000 0 0x8000>;
 433                         interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
 434                                      <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
 435                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
 436                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
 437                                      <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
 438                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
 439                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
 440                                      <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
 441                         interrupt-names = "g_err", "g_recc",
 442                                           "ch0_err", "ch0_rec", "ch0_trx",
 443                                           "ch1_err", "ch1_rec", "ch1_trx";
 444                         clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
 445                                  <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
 446                                  <&can_clk>;
 447                         clock-names = "fck", "canfd", "can_clk";
 448                         assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
 449                         assigned-clock-rates = <50000000>;
 450                         resets = <&cpg R9A07G044_CANFD_RSTP_N>,
 451                                  <&cpg R9A07G044_CANFD_RSTC_N>;
 452                         reset-names = "rstp_n", "rstc_n";
 453                         power-domains = <&cpg>;
 454                         status = "disabled";
 455
 456                         channel0 {
 457                                 status = "disabled";
 458                         };
 459                         channel1 {
 460                                 status = "disabled";
 461                         };
 462                 };
 463
 464                 i2c0: i2c@10058000 {
 465                         #address-cells = <1>;
 466                         #size-cells = <0>;
 467                         compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
 468                         reg = <0 0x10058000 0 0x400>;
 469                         interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
 470                                      <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
 471                                      <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
 472                                      <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
 473                                      <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
 474                                      <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
 475                                      <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
 476                                      <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
 477                         interrupt-names = "tei", "ri", "ti", "spi", "sti",
 478                                           "naki", "ali", "tmoi";
 479                         clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>;
 480                         clock-frequency = <100000>;
 481                         resets = <&cpg R9A07G044_I2C0_MRST>;
 482                         power-domains = <&cpg>;
 483                         status = "disabled";
 484                 };
 485
 486                 i2c1: i2c@10058400 {
 487                         #address-cells = <1>;
 488                         #size-cells = <0>;
 489                         compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
 490                         reg = <0 0x10058400 0 0x400>;
 491                         interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
 492                                      <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
 493                                      <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
 494                                      <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
 495                                      <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
 496                                      <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
 497                                      <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
 498                                      <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
 499                         interrupt-names = "tei", "ri", "ti", "spi", "sti",
 500                                           "naki", "ali", "tmoi";
 501                         clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>;
 502                         clock-frequency = <100000>;
 503                         resets = <&cpg R9A07G044_I2C1_MRST>;
 504                         power-domains = <&cpg>;
 505                         status = "disabled";
 506                 };
 507
 508                 i2c2: i2c@10058800 {
 509                         #address-cells = <1>;
 510                         #size-cells = <0>;
 511                         compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
 512                         reg = <0 0x10058800 0 0x400>;
 513                         interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
 514                                      <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
 515                                      <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
 516                                      <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
 517                                      <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
 518                                      <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
 519                                      <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
 520                                      <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
 521                         interrupt-names = "tei", "ri", "ti", "spi", "sti",
 522                                           "naki", "ali", "tmoi";
 523                         clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>;
 524                         clock-frequency = <100000>;
 525                         resets = <&cpg R9A07G044_I2C2_MRST>;
 526                         power-domains = <&cpg>;
 527                         status = "disabled";
 528                 };
 529
 530                 i2c3: i2c@10058c00 {
 531                         #address-cells = <1>;
 532                         #size-cells = <0>;
 533                         compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
 534                         reg = <0 0x10058c00 0 0x400>;
 535                         interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
 536                                      <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
 537                                      <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
 538                                      <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
 539                                      <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
 540                                      <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
 541                                      <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
 542                                      <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
 543                         interrupt-names = "tei", "ri", "ti", "spi", "sti",
 544                                           "naki", "ali", "tmoi";
 545                         clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>;
 546                         clock-frequency = <100000>;
 547                         resets = <&cpg R9A07G044_I2C3_MRST>;
 548                         power-domains = <&cpg>;
 549                         status = "disabled";
 550                 };
 551
 552                 adc: adc@10059000 {
 553                         compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
 554                         reg = <0 0x10059000 0 0x400>;
 555                         interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
 556                         clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
 557                                  <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
 558                         clock-names = "adclk", "pclk";
 559                         resets = <&cpg R9A07G044_ADC_PRESETN>,
 560                                  <&cpg R9A07G044_ADC_ADRST_N>;
 561                         reset-names = "presetn", "adrst-n";
 562                         power-domains = <&cpg>;
 563                         status = "disabled";
 564
 565                         #address-cells = <1>;
 566                         #size-cells = <0>;
 567
 568                         channel@0 {
 569                                 reg = <0>;
 570                         };
 571                         channel@1 {
 572                                 reg = <1>;
 573                         };
 574                         channel@2 {
 575                                 reg = <2>;
 576                         };
 577                         channel@3 {
 578                                 reg = <3>;
 579                         };
 580                         channel@4 {
 581                                 reg = <4>;
 582                         };
 583                         channel@5 {
 584                                 reg = <5>;
 585                         };
 586                         channel@6 {
 587                                 reg = <6>;
 588                         };
 589                         channel@7 {
 590                                 reg = <7>;
 591                         };
 592                 };
 593
 594                 tsu: thermal@10059400 {
 595                         compatible = "renesas,r9a07g044-tsu",
 596                                      "renesas,rzg2l-tsu";
 597                         reg = <0 0x10059400 0 0x400>;
 598                         clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>;
 599                         resets = <&cpg R9A07G044_TSU_PRESETN>;
 600                         power-domains = <&cpg>;
 601                         #thermal-sensor-cells = <1>;
 602                 };
 603
 604                 sbc: spi@10060000 {
 605                         compatible = "renesas,r9a07g044-rpc-if",
 606                                      "renesas,rzg2l-rpc-if";
 607                         reg = <0 0x10060000 0 0x10000>,
 608                               <0 0x20000000 0 0x10000000>,
 609                               <0 0x10070000 0 0x10000>;
 610                         reg-names = "regs", "dirmap", "wbuf";
 611                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 612                         clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>,
 613                                  <&cpg CPG_MOD R9A07G044_SPI_CLK>;
 614                         resets = <&cpg R9A07G044_SPI_RST>;
 615                         power-domains = <&cpg>;
 616                         #address-cells = <1>;
 617                         #size-cells = <0>;
 618                         status = "disabled";
 619                 };
 620
 621                 cpg: clock-controller@11010000 {
 622                         compatible = "renesas,r9a07g044-cpg";
 623                         reg = <0 0x11010000 0 0x10000>;
 624                         clocks = <&extal_clk>;
 625                         clock-names = "extal";
 626                         #clock-cells = <2>;
 627                         #reset-cells = <1>;
 628                         #power-domain-cells = <0>;
 629                 };
 630
 631                 sysc: system-controller@11020000 {
 632                         compatible = "renesas,r9a07g044-sysc";
 633                         reg = <0 0x11020000 0 0x10000>;
 634                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 635                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 636                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 637                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 638                         interrupt-names = "lpm_int", "ca55stbydone_int",
 639                                           "cm33stbyr_int", "ca55_deny";
 640                         status = "disabled";
 641                 };
 642
 643                 pinctrl: pinctrl@11030000 {
 644                         compatible = "renesas,r9a07g044-pinctrl";
 645                         reg = <0 0x11030000 0 0x10000>;
 646                         gpio-controller;
 647                         #gpio-cells = <2>;
 648                         #interrupt-cells = <2>;
 649                         interrupt-parent = <&irqc>;
 650                         interrupt-controller;
 651                         gpio-ranges = <&pinctrl 0 0 392>;
 652                         clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
 653                         power-domains = <&cpg>;
 654                         resets = <&cpg R9A07G044_GPIO_RSTN>,
 655                                  <&cpg R9A07G044_GPIO_PORT_RESETN>,
 656                                  <&cpg R9A07G044_GPIO_SPARE_RESETN>;
 657                 };
 658
 659                 irqc: interrupt-controller@110a0000 {
 660                         compatible = "renesas,r9a07g044-irqc",
 661                                      "renesas,rzg2l-irqc";
 662                         #interrupt-cells = <2>;
 663                         #address-cells = <0>;
 664                         interrupt-controller;
 665                         reg = <0 0x110a0000 0 0x10000>;
 666                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 667                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 668                                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 669                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 670                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 671                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 672                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 673                                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 674                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 675                                      <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
 676                                      <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
 677                                      <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
 678                                      <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
 679                                      <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
 680                                      <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
 681                                      <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
 682                                      <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
 683                                      <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
 684                                      <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
 685                                      <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
 686                                      <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
 687                                      <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
 688                                      <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
 689                                      <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
 690                                      <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
 691                                      <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
 692                                      <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
 693                                      <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
 694                                      <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
 695                                      <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
 696                                      <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
 697                                      <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
 698                                      <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
 699                                      <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
 700                                      <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
 701                                      <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
 702                                      <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
 703                                      <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
 704                                      <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
 705                                      <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
 706                                      <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
 707                         clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
 708                                  <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
 709                         clock-names = "clk", "pclk";
 710                         power-domains = <&cpg>;
 711                         resets = <&cpg R9A07G044_IA55_RESETN>;
 712                 };
 713
 714                 dmac: dma-controller@11820000 {
 715                         compatible = "renesas,r9a07g044-dmac",
 716                                      "renesas,rz-dmac";
 717                         reg = <0 0x11820000 0 0x10000>,
 718                               <0 0x11830000 0 0x10000>;
 719                         interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
 720                                      <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
 721                                      <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
 722                                      <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
 723                                      <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
 724                                      <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
 725                                      <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
 726                                      <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
 727                                      <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
 728                                      <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
 729                                      <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
 730                                      <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
 731                                      <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
 732                                      <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
 733                                      <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
 734                                      <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
 735                                      <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
 736                         interrupt-names = "error",
 737                                           "ch0", "ch1", "ch2", "ch3",
 738                                           "ch4", "ch5", "ch6", "ch7",
 739                                           "ch8", "ch9", "ch10", "ch11",
 740                                           "ch12", "ch13", "ch14", "ch15";
 741                         clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
 742                                  <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
 743                         power-domains = <&cpg>;
 744                         resets = <&cpg R9A07G044_DMAC_ARESETN>,
 745                                  <&cpg R9A07G044_DMAC_RST_ASYNC>;
 746                         #dma-cells = <1>;
 747                         dma-channels = <16>;
 748                 };
 749
 750                 gpu: gpu@11840000 {
 751                         compatible = "renesas,r9a07g044-mali",
 752                                      "arm,mali-bifrost";
 753                         reg = <0x0 0x11840000 0x0 0x10000>;
 754                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 755                                      <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 756                                      <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 757                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 758                         interrupt-names = "job", "mmu", "gpu", "event";
 759                         clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>,
 760                                  <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>,
 761                                  <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>;
 762                         clock-names = "gpu", "bus", "bus_ace";
 763                         power-domains = <&cpg>;
 764                         resets = <&cpg R9A07G044_GPU_RESETN>,
 765                                  <&cpg R9A07G044_GPU_AXI_RESETN>,
 766                                  <&cpg R9A07G044_GPU_ACE_RESETN>;
 767                         reset-names = "rst", "axi_rst", "ace_rst";
 768                         operating-points-v2 = <&gpu_opp_table>;
 769                 };
 770
 771                 gic: interrupt-controller@11900000 {
 772                         compatible = "arm,gic-v3";
 773                         #interrupt-cells = <3>;
 774                         #address-cells = <0>;
 775                         interrupt-controller;
 776                         reg = <0x0 0x11900000 0 0x40000>,
 777                               <0x0 0x11940000 0 0x60000>;
 778                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 779                 };
 780
 781                 sdhi0: mmc@11c00000 {
 782                         compatible = "renesas,sdhi-r9a07g044",
 783                                      "renesas,rcar-gen3-sdhi";
 784                         reg = <0x0 0x11c00000 0 0x10000>;
 785                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 786                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 787                         clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
 788                                  <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
 789                                  <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
 790                                  <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
 791                         clock-names = "core", "clkh", "cd", "aclk";
 792                         resets = <&cpg R9A07G044_SDHI0_IXRST>;
 793                         power-domains = <&cpg>;
 794                         status = "disabled";
 795                 };
 796
 797                 sdhi1: mmc@11c10000 {
 798                         compatible = "renesas,sdhi-r9a07g044",
 799                                      "renesas,rcar-gen3-sdhi";
 800                         reg = <0x0 0x11c10000 0 0x10000>;
 801                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 802                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 803                         clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
 804                                  <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
 805                                  <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
 806                                  <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
 807                         clock-names = "core", "clkh", "cd", "aclk";
 808                         resets = <&cpg R9A07G044_SDHI1_IXRST>;
 809                         power-domains = <&cpg>;
 810                         status = "disabled";
 811                 };
 812
 813                 eth0: ethernet@11c20000 {
 814                         compatible = "renesas,r9a07g044-gbeth",
 815                                      "renesas,rzg2l-gbeth";
 816                         reg = <0 0x11c20000 0 0x10000>;
 817                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 818                                      <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 819                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 820                         interrupt-names = "mux", "fil", "arp_ns";
 821                         phy-mode = "rgmii";
 822                         clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>,
 823                                  <&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>,
 824                                  <&cpg CPG_CORE R9A07G044_CLK_HP>;
 825                         clock-names = "axi", "chi", "refclk";
 826                         resets = <&cpg R9A07G044_ETH0_RST_HW_N>;
 827                         power-domains = <&cpg>;
 828                         #address-cells = <1>;
 829                         #size-cells = <0>;
 830                         status = "disabled";
 831                 };
 832
 833                 eth1: ethernet@11c30000 {
 834                         compatible = "renesas,r9a07g044-gbeth",
 835                                      "renesas,rzg2l-gbeth";
 836                         reg = <0 0x11c30000 0 0x10000>;
 837                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 838                                      <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 839                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 840                         interrupt-names = "mux", "fil", "arp_ns";
 841                         phy-mode = "rgmii";
 842                         clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>,
 843                                  <&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>,
 844                                  <&cpg CPG_CORE R9A07G044_CLK_HP>;
 845                         clock-names = "axi", "chi", "refclk";
 846                         resets = <&cpg R9A07G044_ETH1_RST_HW_N>;
 847                         power-domains = <&cpg>;
 848                         #address-cells = <1>;
 849                         #size-cells = <0>;
 850                         status = "disabled";
 851                 };
 852
 853                 phyrst: usbphy-ctrl@11c40000 {
 854                         compatible = "renesas,r9a07g044-usbphy-ctrl",
 855                                      "renesas,rzg2l-usbphy-ctrl";
 856                         reg = <0 0x11c40000 0 0x10000>;
 857                         clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
 858                         resets = <&cpg R9A07G044_USB_PRESETN>;
 859                         power-domains = <&cpg>;
 860                         #reset-cells = <1>;
 861                         status = "disabled";
 862                 };
 863
 864                 ohci0: usb@11c50000 {
 865                         compatible = "generic-ohci";
 866                         reg = <0 0x11c50000 0 0x100>;
 867                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 868                         clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
 869                                  <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
 870                         resets = <&phyrst 0>,
 871                                  <&cpg R9A07G044_USB_U2H0_HRESETN>;
 872                         phys = <&usb2_phy0 1>;
 873                         phy-names = "usb";
 874                         power-domains = <&cpg>;
 875                         status = "disabled";
 876                 };
 877
 878                 ohci1: usb@11c70000 {
 879                         compatible = "generic-ohci";
 880                         reg = <0 0x11c70000 0 0x100>;
 881                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 882                         clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
 883                                  <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
 884                         resets = <&phyrst 1>,
 885                                  <&cpg R9A07G044_USB_U2H1_HRESETN>;
 886                         phys = <&usb2_phy1 1>;
 887                         phy-names = "usb";
 888                         power-domains = <&cpg>;
 889                         status = "disabled";
 890                 };
 891
 892                 ehci0: usb@11c50100 {
 893                         compatible = "generic-ehci";
 894                         reg = <0 0x11c50100 0 0x100>;
 895                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 896                         clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
 897                                  <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
 898                         resets = <&phyrst 0>,
 899                                  <&cpg R9A07G044_USB_U2H0_HRESETN>;
 900                         phys = <&usb2_phy0 2>;
 901                         phy-names = "usb";
 902                         companion = <&ohci0>;
 903                         power-domains = <&cpg>;
 904                         status = "disabled";
 905                 };
 906
 907                 ehci1: usb@11c70100 {
 908                         compatible = "generic-ehci";
 909                         reg = <0 0x11c70100 0 0x100>;
 910                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 911                         clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
 912                                  <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
 913                         resets = <&phyrst 1>,
 914                                  <&cpg R9A07G044_USB_U2H1_HRESETN>;
 915                         phys = <&usb2_phy1 2>;
 916                         phy-names = "usb";
 917                         companion = <&ohci1>;
 918                         power-domains = <&cpg>;
 919                         status = "disabled";
 920                 };
 921
 922                 usb2_phy0: usb-phy@11c50200 {
 923                         compatible = "renesas,usb2-phy-r9a07g044",
 924                                      "renesas,rzg2l-usb2-phy";
 925                         reg = <0 0x11c50200 0 0x700>;
 926                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 927                         clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
 928                                  <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
 929                         resets = <&phyrst 0>;
 930                         #phy-cells = <1>;
 931                         power-domains = <&cpg>;
 932                         status = "disabled";
 933                 };
 934
 935                 usb2_phy1: usb-phy@11c70200 {
 936                         compatible = "renesas,usb2-phy-r9a07g044",
 937                                      "renesas,rzg2l-usb2-phy";
 938                         reg = <0 0x11c70200 0 0x700>;
 939                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 940                         clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
 941                                  <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
 942                         resets = <&phyrst 1>;
 943                         #phy-cells = <1>;
 944                         power-domains = <&cpg>;
 945                         status = "disabled";
 946                 };
 947
 948                 hsusb: usb@11c60000 {
 949                         compatible = "renesas,usbhs-r9a07g044",
 950                                      "renesas,rza2-usbhs";
 951                         reg = <0 0x11c60000 0 0x10000>;
 952                         interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
 953                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 954                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 955                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 956                         clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
 957                                  <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
 958                         resets = <&phyrst 0>,
 959                                  <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
 960                         renesas,buswait = <7>;
 961                         phys = <&usb2_phy0 3>;
 962                         phy-names = "usb";
 963                         power-domains = <&cpg>;
 964                         status = "disabled";
 965                 };
 966
 967                 wdt0: watchdog@12800800 {
 968                         compatible = "renesas,r9a07g044-wdt",
 969                                      "renesas,rzg2l-wdt";
 970                         reg = <0 0x12800800 0 0x400>;
 971                         clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>,
 972                                  <&cpg CPG_MOD R9A07G044_WDT0_CLK>;
 973                         clock-names = "pclk", "oscclk";
 974                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 975                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 976                         interrupt-names = "wdt", "perrout";
 977                         resets = <&cpg R9A07G044_WDT0_PRESETN>;
 978                         power-domains = <&cpg>;
 979                         status = "disabled";
 980                 };
 981
 982                 wdt1: watchdog@12800c00 {
 983                         compatible = "renesas,r9a07g044-wdt",
 984                                      "renesas,rzg2l-wdt";
 985                         reg = <0 0x12800C00 0 0x400>;
 986                         clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>,
 987                                  <&cpg CPG_MOD R9A07G044_WDT1_CLK>;
 988                         clock-names = "pclk", "oscclk";
 989                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 990                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 991                         interrupt-names = "wdt", "perrout";
 992                         resets = <&cpg R9A07G044_WDT1_PRESETN>;
 993                         power-domains = <&cpg>;
 994                         status = "disabled";
 995                 };
 996
 997                 ostm0: timer@12801000 {
 998                         compatible = "renesas,r9a07g044-ostm",
 999                                      "renesas,ostm";
1000                         reg = <0x0 0x12801000 0x0 0x400>;
1001                         interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
1002                         clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>;
1003                         resets = <&cpg R9A07G044_OSTM0_PRESETZ>;
1004                         power-domains = <&cpg>;
1005                         status = "disabled";
1006                 };
1007
1008                 ostm1: timer@12801400 {
1009                         compatible = "renesas,r9a07g044-ostm",
1010                                      "renesas,ostm";
1011                         reg = <0x0 0x12801400 0x0 0x400>;
1012                         interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
1013                         clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>;
1014                         resets = <&cpg R9A07G044_OSTM1_PRESETZ>;
1015                         power-domains = <&cpg>;
1016                         status = "disabled";
1017                 };
1018
1019                 ostm2: timer@12801800 {
1020                         compatible = "renesas,r9a07g044-ostm",
1021                                      "renesas,ostm";
1022                         reg = <0x0 0x12801800 0x0 0x400>;
1023                         interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
1024                         clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>;
1025                         resets = <&cpg R9A07G044_OSTM2_PRESETZ>;
1026                         power-domains = <&cpg>;
1027                         status = "disabled";
1028                 };
1029         };
1030
1031         thermal-zones {
1032                 cpu-thermal {
1033                         polling-delay-passive = <250>;
1034                         polling-delay = <1000>;
1035                         thermal-sensors = <&tsu 0>;
1036                         sustainable-power = <717>;
1037
1038                         cooling-maps {
1039                                 map0 {
1040                                         trip = <&target>;
1041                                         cooling-device = <&cpu0 0 2>;
1042                                         contribution = <1024>;
1043                                 };
1044                         };
1045
1046                         trips {
1047                                 sensor_crit: sensor-crit {
1048                                         temperature = <125000>;
1049                                         hysteresis = <1000>;
1050                                         type = "critical";
1051                                 };
1052
1053                                 target: trip-point {
1054                                         temperature = <100000>;
1055                                         hysteresis = <1000>;
1056                                         type = "passive";
1057                                 };
1058                         };
1059                 };
1060         };
1061
1062         timer {
1063                 compatible = "arm,armv8-timer";
1064                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1065                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1066                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1067                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1068         };
1069 };