src/arm64/renesas/rzg2l-smarc-som.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 /*
   3  * Device Tree Source for the RZ/{G2L,V2L} SMARC SOM common parts
   4  *
   5  * Copyright (C) 2021 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
  10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
  11
  12 /* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
  13 #define EMMC    1
  14
  15 /*
  16  * To enable uSD card on CN3,
  17  * SW1[2] should be at position 3/ON.
  18  * Disable eMMC by setting "#define EMMC        0" above.
  19  */
  20 #define SDHI    (!EMMC)
  21
  22 / {
  23         aliases {
  24                 ethernet0 = &eth0;
  25                 ethernet1 = &eth1;
  26         };
  27
  28         chosen {
  29                 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
  30         };
  31
  32         memory@48000000 {
  33                 device_type = "memory";
  34                 /* first 128MB is reserved for secure area. */
  35                 reg = <0x0 0x48000000 0x0 0x78000000>;
  36         };
  37
  38         reg_1p8v: regulator-1p8v {
  39                 compatible = "regulator-fixed";
  40                 regulator-name = "fixed-1.8V";
  41                 regulator-min-microvolt = <1800000>;
  42                 regulator-max-microvolt = <1800000>;
  43                 regulator-boot-on;
  44                 regulator-always-on;
  45         };
  46
  47         reg_3p3v: regulator-3p3v {
  48                 compatible = "regulator-fixed";
  49                 regulator-name = "fixed-3.3V";
  50                 regulator-min-microvolt = <3300000>;
  51                 regulator-max-microvolt = <3300000>;
  52                 regulator-boot-on;
  53                 regulator-always-on;
  54         };
  55
  56         reg_1p1v: regulator-vdd-core {
  57                 compatible = "regulator-fixed";
  58                 regulator-name = "fixed-1.1V";
  59                 regulator-min-microvolt = <1100000>;
  60                 regulator-max-microvolt = <1100000>;
  61                 regulator-boot-on;
  62                 regulator-always-on;
  63         };
  64
  65         vccq_sdhi0: regulator-vccq-sdhi0 {
  66                 compatible = "regulator-gpio";
  67
  68                 regulator-name = "SDHI0 VccQ";
  69                 regulator-min-microvolt = <1800000>;
  70                 regulator-max-microvolt = <3300000>;
  71                 states = <3300000 1>, <1800000 0>;
  72                 regulator-boot-on;
  73                 gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
  74                 regulator-always-on;
  75         };
  76 };
  77
  78 &adc {
  79         pinctrl-0 = <&adc_pins>;
  80         pinctrl-names = "default";
  81         status = "okay";
  82
  83         /delete-node/ channel@6;
  84         /delete-node/ channel@7;
  85 };
  86
  87 &eth0 {
  88         pinctrl-0 = <&eth0_pins>;
  89         pinctrl-names = "default";
  90         phy-handle = <&phy0>;
  91         phy-mode = "rgmii-id";
  92         status = "okay";
  93
  94         phy0: ethernet-phy@7 {
  95                 compatible = "ethernet-phy-id0022.1640",
  96                              "ethernet-phy-ieee802.3-c22";
  97                 reg = <7>;
  98                 interrupt-parent = <&irqc>;
  99                 interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
 100                 rxc-skew-psec = <2400>;
 101                 txc-skew-psec = <2400>;
 102                 rxdv-skew-psec = <0>;
 103                 txdv-skew-psec = <0>;
 104                 rxd0-skew-psec = <0>;
 105                 rxd1-skew-psec = <0>;
 106                 rxd2-skew-psec = <0>;
 107                 rxd3-skew-psec = <0>;
 108                 txd0-skew-psec = <0>;
 109                 txd1-skew-psec = <0>;
 110                 txd2-skew-psec = <0>;
 111                 txd3-skew-psec = <0>;
 112         };
 113 };
 114
 115 &eth1 {
 116         pinctrl-0 = <&eth1_pins>;
 117         pinctrl-names = "default";
 118         phy-handle = <&phy1>;
 119         phy-mode = "rgmii-id";
 120         status = "okay";
 121
 122         phy1: ethernet-phy@7 {
 123                 compatible = "ethernet-phy-id0022.1640",
 124                              "ethernet-phy-ieee802.3-c22";
 125                 reg = <7>;
 126                 interrupt-parent = <&irqc>;
 127                 interrupts = <RZG2L_IRQ3 IRQ_TYPE_LEVEL_LOW>;
 128                 rxc-skew-psec = <2400>;
 129                 txc-skew-psec = <2400>;
 130                 rxdv-skew-psec = <0>;
 131                 txdv-skew-psec = <0>;
 132                 rxd0-skew-psec = <0>;
 133                 rxd1-skew-psec = <0>;
 134                 rxd2-skew-psec = <0>;
 135                 rxd3-skew-psec = <0>;
 136                 txd0-skew-psec = <0>;
 137                 txd1-skew-psec = <0>;
 138                 txd2-skew-psec = <0>;
 139                 txd3-skew-psec = <0>;
 140         };
 141 };
 142
 143 &extal_clk {
 144         clock-frequency = <24000000>;
 145 };
 146
 147 &gpu {
 148         mali-supply = <&reg_1p1v>;
 149 };
 150
 151 &ostm1 {
 152         status = "okay";
 153 };
 154
 155 &ostm2 {
 156         status = "okay";
 157 };
 158
 159 &pinctrl {
 160         adc_pins: adc {
 161                 pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */
 162         };
 163
 164         eth0_pins: eth0 {
 165                 pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
 166                          <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
 167                          <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
 168                          <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
 169                          <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
 170                          <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
 171                          <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
 172                          <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
 173                          <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
 174                          <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
 175                          <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
 176                          <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
 177                          <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
 178                          <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
 179                          <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */
 180                          <RZG2L_PORT_PINMUX(1, 0, 1)>;  /* IRQ2 */
 181         };
 182
 183         eth1_pins: eth1 {
 184                 pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
 185                          <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
 186                          <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
 187                          <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
 188                          <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
 189                          <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
 190                          <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
 191                          <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
 192                          <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
 193                          <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
 194                          <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
 195                          <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
 196                          <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
 197                          <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
 198                          <RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */
 199                          <RZG2L_PORT_PINMUX(1, 1, 1)>;  /* IRQ3 */
 200         };
 201
 202         gpio-sd0-pwr-en-hog {
 203                 gpio-hog;
 204                 gpios = <RZG2L_GPIO(4, 1) GPIO_ACTIVE_HIGH>;
 205                 output-high;
 206                 line-name = "gpio_sd0_pwr_en";
 207         };
 208
 209         qspi0_pins: qspi0 {
 210                 qspi0-data {
 211                         pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
 212                         power-source = <1800>;
 213                 };
 214
 215                 qspi0-ctrl {
 216                         pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
 217                         power-source = <1800>;
 218                 };
 219         };
 220
 221         /*
 222          * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
 223          * The below switch logic can be used to select the device between
 224          * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
 225          * SW1[2] should be at position 2/OFF to enable 64 GB eMMC
 226          * SW1[2] should be at position 3/ON to enable uSD card CN3
 227          */
 228         sd0-dev-sel-hog {
 229                 gpio-hog;
 230                 gpios = <RZG2L_GPIO(41, 1) GPIO_ACTIVE_HIGH>;
 231                 output-high;
 232                 line-name = "sd0_dev_sel";
 233         };
 234
 235         sdhi0_emmc_pins: sd0emmc {
 236                 sd0_emmc_data {
 237                         pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
 238                                "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
 239                         power-source = <1800>;
 240                 };
 241
 242                 sd0_emmc_ctrl {
 243                         pins = "SD0_CLK", "SD0_CMD";
 244                         power-source = <1800>;
 245                 };
 246
 247                 sd0_emmc_rst {
 248                         pins = "SD0_RST#";
 249                         power-source = <1800>;
 250                 };
 251         };
 252
 253         sdhi0_pins: sd0 {
 254                 sd0_data {
 255                         pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
 256                         power-source = <3300>;
 257                 };
 258
 259                 sd0_ctrl {
 260                         pins = "SD0_CLK", "SD0_CMD";
 261                         power-source = <3300>;
 262                 };
 263
 264                 sd0_mux {
 265                         pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
 266                 };
 267         };
 268
 269         sdhi0_pins_uhs: sd0_uhs {
 270                 sd0_data_uhs {
 271                         pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
 272                         power-source = <1800>;
 273                 };
 274
 275                 sd0_ctrl_uhs {
 276                         pins = "SD0_CLK", "SD0_CMD";
 277                         power-source = <1800>;
 278                 };
 279
 280                 sd0_mux_uhs {
 281                         pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
 282                 };
 283         };
 284 };
 285
 286 &sbc {
 287         pinctrl-0 = <&qspi0_pins>;
 288         pinctrl-names = "default";
 289         status = "okay";
 290
 291         flash@0 {
 292                 compatible = "micron,mt25qu512a", "jedec,spi-nor";
 293                 reg = <0>;
 294                 m25p,fast-read;
 295                 spi-max-frequency = <50000000>;
 296                 spi-rx-bus-width = <4>;
 297
 298                 partitions {
 299                         compatible = "fixed-partitions";
 300                         #address-cells = <1>;
 301                         #size-cells = <1>;
 302
 303                         boot@0 {
 304                                 reg = <0x00000000 0x2000000>;
 305                                 read-only;
 306                         };
 307                         user@2000000 {
 308                                 reg = <0x2000000 0x2000000>;
 309                         };
 310                 };
 311         };
 312 };
 313
 314 #if SDHI
 315 &sdhi0 {
 316         pinctrl-0 = <&sdhi0_pins>;
 317         pinctrl-1 = <&sdhi0_pins_uhs>;
 318         pinctrl-names = "default", "state_uhs";
 319
 320         vmmc-supply = <&reg_3p3v>;
 321         vqmmc-supply = <&vccq_sdhi0>;
 322         bus-width = <4>;
 323         sd-uhs-sdr50;
 324         sd-uhs-sdr104;
 325         status = "okay";
 326 };
 327 #endif
 328
 329 #if EMMC
 330 &sdhi0 {
 331         pinctrl-0 = <&sdhi0_emmc_pins>;
 332         pinctrl-1 = <&sdhi0_emmc_pins>;
 333         pinctrl-names = "default", "state_uhs";
 334
 335         vmmc-supply = <&reg_3p3v>;
 336         vqmmc-supply = <&reg_1p8v>;
 337         bus-width = <8>;
 338         mmc-hs200-1_8v;
 339         non-removable;
 340         fixed-emmc-driver-type = <1>;
 341         status = "okay";
 342 };
 343 #endif
 344
 345 &wdt0 {
 346         status = "okay";
 347         timeout-sec = <60>;
 348 };
 349
 350 &wdt1 {
 351         status = "okay";
 352         timeout-sec = <60>;
 353 };