src/arm64/rockchip/rk3308.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
   4  *
   5  */
   6
   7 #include <dt-bindings/clock/rk3308-cru.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/pinctrl/rockchip.h>
  12 #include <dt-bindings/soc/rockchip,boot-mode.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         compatible = "rockchip,rk3308";
  17
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 serial0 = &uart0;
  28                 serial1 = &uart1;
  29                 serial2 = &uart2;
  30                 serial3 = &uart3;
  31                 serial4 = &uart4;
  32                 spi0 = &spi0;
  33                 spi1 = &spi1;
  34                 spi2 = &spi2;
  35         };
  36
  37         cpus {
  38                 #address-cells = <2>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a35";
  44                         reg = <0x0 0x0>;
  45                         enable-method = "psci";
  46                         clocks = <&cru ARMCLK>;
  47                         #cooling-cells = <2>;
  48                         dynamic-power-coefficient = <90>;
  49                         operating-points-v2 = <&cpu0_opp_table>;
  50                         cpu-idle-states = <&CPU_SLEEP>;
  51                         next-level-cache = <&l2>;
  52                 };
  53
  54                 cpu1: cpu@1 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a35";
  57                         reg = <0x0 0x1>;
  58                         enable-method = "psci";
  59                         operating-points-v2 = <&cpu0_opp_table>;
  60                         cpu-idle-states = <&CPU_SLEEP>;
  61                         next-level-cache = <&l2>;
  62                 };
  63
  64                 cpu2: cpu@2 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a35";
  67                         reg = <0x0 0x2>;
  68                         enable-method = "psci";
  69                         operating-points-v2 = <&cpu0_opp_table>;
  70                         cpu-idle-states = <&CPU_SLEEP>;
  71                         next-level-cache = <&l2>;
  72                 };
  73
  74                 cpu3: cpu@3 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a35";
  77                         reg = <0x0 0x3>;
  78                         enable-method = "psci";
  79                         operating-points-v2 = <&cpu0_opp_table>;
  80                         cpu-idle-states = <&CPU_SLEEP>;
  81                         next-level-cache = <&l2>;
  82                 };
  83
  84                 idle-states {
  85                         entry-method = "psci";
  86
  87                         CPU_SLEEP: cpu-sleep {
  88                                 compatible = "arm,idle-state";
  89                                 local-timer-stop;
  90                                 arm,psci-suspend-param = <0x0010000>;
  91                                 entry-latency-us = <120>;
  92                                 exit-latency-us = <250>;
  93                                 min-residency-us = <900>;
  94                         };
  95                 };
  96
  97                 l2: l2-cache {
  98                         compatible = "cache";
  99                         cache-level = <2>;
 100                 };
 101         };
 102
 103         cpu0_opp_table: opp-table-0 {
 104                 compatible = "operating-points-v2";
 105                 opp-shared;
 106
 107                 opp-408000000 {
 108                         opp-hz = /bits/ 64 <408000000>;
 109                         opp-microvolt = <950000 950000 1340000>;
 110                         clock-latency-ns = <40000>;
 111                         opp-suspend;
 112                 };
 113                 opp-600000000 {
 114                         opp-hz = /bits/ 64 <600000000>;
 115                         opp-microvolt = <950000 950000 1340000>;
 116                         clock-latency-ns = <40000>;
 117                 };
 118                 opp-816000000 {
 119                         opp-hz = /bits/ 64 <816000000>;
 120                         opp-microvolt = <1025000 1025000 1340000>;
 121                         clock-latency-ns = <40000>;
 122                 };
 123                 opp-1008000000 {
 124                         opp-hz = /bits/ 64 <1008000000>;
 125                         opp-microvolt = <1125000 1125000 1340000>;
 126                         clock-latency-ns = <40000>;
 127                 };
 128         };
 129
 130         arm-pmu {
 131                 compatible = "arm,cortex-a35-pmu";
 132                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
 133                              <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 134                              <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 135                              <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 136                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 137         };
 138
 139         mac_clkin: external-mac-clock {
 140                 compatible = "fixed-clock";
 141                 clock-frequency = <50000000>;
 142                 clock-output-names = "mac_clkin";
 143                 #clock-cells = <0>;
 144         };
 145
 146         psci {
 147                 compatible = "arm,psci-1.0";
 148                 method = "smc";
 149         };
 150
 151         timer {
 152                 compatible = "arm,armv8-timer";
 153                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 154                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 155                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 156                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 157         };
 158
 159         xin24m: xin24m {
 160                 compatible = "fixed-clock";
 161                 #clock-cells = <0>;
 162                 clock-frequency = <24000000>;
 163                 clock-output-names = "xin24m";
 164         };
 165
 166         grf: grf@ff000000 {
 167                 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
 168                 reg = <0x0 0xff000000 0x0 0x08000>;
 169
 170                 reboot-mode {
 171                         compatible = "syscon-reboot-mode";
 172                         offset = <0x500>;
 173                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
 174                         mode-loader = <BOOT_BL_DOWNLOAD>;
 175                         mode-normal = <BOOT_NORMAL>;
 176                         mode-recovery = <BOOT_RECOVERY>;
 177                         mode-fastboot = <BOOT_FASTBOOT>;
 178                 };
 179         };
 180
 181         usb2phy_grf: syscon@ff008000 {
 182                 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd";
 183                 reg = <0x0 0xff008000 0x0 0x4000>;
 184                 #address-cells = <1>;
 185                 #size-cells = <1>;
 186
 187                 u2phy: usb2phy@100 {
 188                         compatible = "rockchip,rk3308-usb2phy";
 189                         reg = <0x100 0x10>;
 190                         assigned-clocks = <&cru USB480M>;
 191                         assigned-clock-parents = <&u2phy>;
 192                         clocks = <&cru SCLK_USBPHY_REF>;
 193                         clock-names = "phyclk";
 194                         clock-output-names = "usb480m_phy";
 195                         #clock-cells = <0>;
 196                         status = "disabled";
 197
 198                         u2phy_otg: otg-port {
 199                                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 200                                              <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 201                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 202                                 interrupt-names = "otg-bvalid", "otg-id",
 203                                                   "linestate";
 204                                 #phy-cells = <0>;
 205                                 status = "disabled";
 206                         };
 207
 208                         u2phy_host: host-port {
 209                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 210                                 interrupt-names = "linestate";
 211                                 #phy-cells = <0>;
 212                                 status = "disabled";
 213                         };
 214                 };
 215         };
 216
 217         detect_grf: syscon@ff00b000 {
 218                 compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
 219                 reg = <0x0 0xff00b000 0x0 0x1000>;
 220                 #address-cells = <1>;
 221                 #size-cells = <1>;
 222         };
 223
 224         core_grf: syscon@ff00c000 {
 225                 compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd";
 226                 reg = <0x0 0xff00c000 0x0 0x1000>;
 227                 #address-cells = <1>;
 228                 #size-cells = <1>;
 229         };
 230
 231         i2c0: i2c@ff040000 {
 232                 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
 233                 reg = <0x0 0xff040000 0x0 0x1000>;
 234                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 235                 clock-names = "i2c", "pclk";
 236                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 237                 pinctrl-names = "default";
 238                 pinctrl-0 = <&i2c0_xfer>;
 239                 #address-cells = <1>;
 240                 #size-cells = <0>;
 241                 status = "disabled";
 242         };
 243
 244         i2c1: i2c@ff050000 {
 245                 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
 246                 reg = <0x0 0xff050000 0x0 0x1000>;
 247                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 248                 clock-names = "i2c", "pclk";
 249                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 250                 pinctrl-names = "default";
 251                 pinctrl-0 = <&i2c1_xfer>;
 252                 #address-cells = <1>;
 253                 #size-cells = <0>;
 254                 status = "disabled";
 255         };
 256
 257         i2c2: i2c@ff060000 {
 258                 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
 259                 reg = <0x0 0xff060000 0x0 0x1000>;
 260                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 261                 clock-names = "i2c", "pclk";
 262                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 263                 pinctrl-names = "default";
 264                 pinctrl-0 = <&i2c2_xfer>;
 265                 #address-cells = <1>;
 266                 #size-cells = <0>;
 267                 status = "disabled";
 268         };
 269
 270         i2c3: i2c@ff070000 {
 271                 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
 272                 reg = <0x0 0xff070000 0x0 0x1000>;
 273                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 274                 clock-names = "i2c", "pclk";
 275                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 276                 pinctrl-names = "default";
 277                 pinctrl-0 = <&i2c3m0_xfer>;
 278                 #address-cells = <1>;
 279                 #size-cells = <0>;
 280                 status = "disabled";
 281         };
 282
 283         wdt: watchdog@ff080000 {
 284                 compatible = "rockchip,rk3308-wdt", "snps,dw-wdt";
 285                 reg = <0x0 0xff080000 0x0 0x100>;
 286                 clocks = <&cru PCLK_WDT>;
 287                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 288                 status = "disabled";
 289         };
 290
 291         uart0: serial@ff0a0000 {
 292                 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
 293                 reg = <0x0 0xff0a0000 0x0 0x100>;
 294                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 295                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 296                 clock-names = "baudclk", "apb_pclk";
 297                 reg-shift = <2>;
 298                 reg-io-width = <4>;
 299                 pinctrl-names = "default";
 300                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 301                 status = "disabled";
 302         };
 303
 304         uart1: serial@ff0b0000 {
 305                 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
 306                 reg = <0x0 0xff0b0000 0x0 0x100>;
 307                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 308                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 309                 clock-names = "baudclk", "apb_pclk";
 310                 reg-shift = <2>;
 311                 reg-io-width = <4>;
 312                 pinctrl-names = "default";
 313                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 314                 status = "disabled";
 315         };
 316
 317         uart2: serial@ff0c0000 {
 318                 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
 319                 reg = <0x0 0xff0c0000 0x0 0x100>;
 320                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 321                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 322                 clock-names = "baudclk", "apb_pclk";
 323                 reg-shift = <2>;
 324                 reg-io-width = <4>;
 325                 pinctrl-names = "default";
 326                 pinctrl-0 = <&uart2m0_xfer>;
 327                 status = "disabled";
 328         };
 329
 330         uart3: serial@ff0d0000 {
 331                 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
 332                 reg = <0x0 0xff0d0000 0x0 0x100>;
 333                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 334                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 335                 clock-names = "baudclk", "apb_pclk";
 336                 reg-shift = <2>;
 337                 reg-io-width = <4>;
 338                 pinctrl-names = "default";
 339                 pinctrl-0 = <&uart3_xfer>;
 340                 status = "disabled";
 341         };
 342
 343         uart4: serial@ff0e0000 {
 344                 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
 345                 reg = <0x0 0xff0e0000 0x0 0x100>;
 346                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 347                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 348                 clock-names = "baudclk", "apb_pclk";
 349                 reg-shift = <2>;
 350                 reg-io-width = <4>;
 351                 pinctrl-names = "default";
 352                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 353                 status = "disabled";
 354         };
 355
 356         spi0: spi@ff120000 {
 357                 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
 358                 reg = <0x0 0xff120000 0x0 0x1000>;
 359                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 360                 #address-cells = <1>;
 361                 #size-cells = <0>;
 362                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 363                 clock-names = "spiclk", "apb_pclk";
 364                 dmas = <&dmac0 0>, <&dmac0 1>;
 365                 dma-names = "tx", "rx";
 366                 pinctrl-names = "default";
 367                 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
 368                 status = "disabled";
 369         };
 370
 371         spi1: spi@ff130000 {
 372                 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
 373                 reg = <0x0 0xff130000 0x0 0x1000>;
 374                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 375                 #address-cells = <1>;
 376                 #size-cells = <0>;
 377                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 378                 clock-names = "spiclk", "apb_pclk";
 379                 dmas = <&dmac0 2>, <&dmac0 3>;
 380                 dma-names = "tx", "rx";
 381                 pinctrl-names = "default";
 382                 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
 383                 status = "disabled";
 384         };
 385
 386         spi2: spi@ff140000 {
 387                 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
 388                 reg = <0x0 0xff140000 0x0 0x1000>;
 389                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 390                 #address-cells = <1>;
 391                 #size-cells = <0>;
 392                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 393                 clock-names = "spiclk", "apb_pclk";
 394                 dmas = <&dmac1 16>, <&dmac1 17>;
 395                 dma-names = "tx", "rx";
 396                 pinctrl-names = "default";
 397                 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
 398                 status = "disabled";
 399         };
 400
 401         pwm8: pwm@ff160000 {
 402                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 403                 reg = <0x0 0xff160000 0x0 0x10>;
 404                 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
 405                 clock-names = "pwm", "pclk";
 406                 pinctrl-names = "default";
 407                 pinctrl-0 = <&pwm8_pin>;
 408                 #pwm-cells = <3>;
 409                 status = "disabled";
 410         };
 411
 412         pwm9: pwm@ff160010 {
 413                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 414                 reg = <0x0 0xff160010 0x0 0x10>;
 415                 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
 416                 clock-names = "pwm", "pclk";
 417                 pinctrl-names = "default";
 418                 pinctrl-0 = <&pwm9_pin>;
 419                 #pwm-cells = <3>;
 420                 status = "disabled";
 421         };
 422
 423         pwm10: pwm@ff160020 {
 424                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 425                 reg = <0x0 0xff160020 0x0 0x10>;
 426                 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
 427                 clock-names = "pwm", "pclk";
 428                 pinctrl-names = "default";
 429                 pinctrl-0 = <&pwm10_pin>;
 430                 #pwm-cells = <3>;
 431                 status = "disabled";
 432         };
 433
 434         pwm11: pwm@ff160030 {
 435                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 436                 reg = <0x0 0xff160030 0x0 0x10>;
 437                 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
 438                 clock-names = "pwm", "pclk";
 439                 pinctrl-names = "default";
 440                 pinctrl-0 = <&pwm11_pin>;
 441                 #pwm-cells = <3>;
 442                 status = "disabled";
 443         };
 444
 445         pwm4: pwm@ff170000 {
 446                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 447                 reg = <0x0 0xff170000 0x0 0x10>;
 448                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 449                 clock-names = "pwm", "pclk";
 450                 pinctrl-names = "default";
 451                 pinctrl-0 = <&pwm4_pin>;
 452                 #pwm-cells = <3>;
 453                 status = "disabled";
 454         };
 455
 456         pwm5: pwm@ff170010 {
 457                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 458                 reg = <0x0 0xff170010 0x0 0x10>;
 459                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 460                 clock-names = "pwm", "pclk";
 461                 pinctrl-names = "default";
 462                 pinctrl-0 = <&pwm5_pin>;
 463                 #pwm-cells = <3>;
 464                 status = "disabled";
 465         };
 466
 467         pwm6: pwm@ff170020 {
 468                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 469                 reg = <0x0 0xff170020 0x0 0x10>;
 470                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 471                 clock-names = "pwm", "pclk";
 472                 pinctrl-names = "default";
 473                 pinctrl-0 = <&pwm6_pin>;
 474                 #pwm-cells = <3>;
 475                 status = "disabled";
 476         };
 477
 478         pwm7: pwm@ff170030 {
 479                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 480                 reg = <0x0 0xff170030 0x0 0x10>;
 481                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 482                 clock-names = "pwm", "pclk";
 483                 pinctrl-names = "default";
 484                 pinctrl-0 = <&pwm7_pin>;
 485                 #pwm-cells = <3>;
 486                 status = "disabled";
 487         };
 488
 489         pwm0: pwm@ff180000 {
 490                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 491                 reg = <0x0 0xff180000 0x0 0x10>;
 492                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 493                 clock-names = "pwm", "pclk";
 494                 pinctrl-names = "default";
 495                 pinctrl-0 = <&pwm0_pin>;
 496                 #pwm-cells = <3>;
 497                 status = "disabled";
 498         };
 499
 500         pwm1: pwm@ff180010 {
 501                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 502                 reg = <0x0 0xff180010 0x0 0x10>;
 503                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 504                 clock-names = "pwm", "pclk";
 505                 pinctrl-names = "default";
 506                 pinctrl-0 = <&pwm1_pin>;
 507                 #pwm-cells = <3>;
 508                 status = "disabled";
 509         };
 510
 511         pwm2: pwm@ff180020 {
 512                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 513                 reg = <0x0 0xff180020 0x0 0x10>;
 514                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 515                 clock-names = "pwm", "pclk";
 516                 pinctrl-names = "default";
 517                 pinctrl-0 = <&pwm2_pin>;
 518                 #pwm-cells = <3>;
 519                 status = "disabled";
 520         };
 521
 522         pwm3: pwm@ff180030 {
 523                 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
 524                 reg = <0x0 0xff180030 0x0 0x10>;
 525                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 526                 clock-names = "pwm", "pclk";
 527                 pinctrl-names = "default";
 528                 pinctrl-0 = <&pwm3_pin>;
 529                 #pwm-cells = <3>;
 530                 status = "disabled";
 531         };
 532
 533         rktimer: rktimer@ff1a0000 {
 534                 compatible = "rockchip,rk3288-timer";
 535                 reg = <0x0 0xff1a0000 0x0 0x20>;
 536                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 537                 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
 538                 clock-names = "pclk", "timer";
 539         };
 540
 541         saradc: saradc@ff1e0000 {
 542                 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
 543                 reg = <0x0 0xff1e0000 0x0 0x100>;
 544                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 545                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 546                 clock-names = "saradc", "apb_pclk";
 547                 #io-channel-cells = <1>;
 548                 resets = <&cru SRST_SARADC_P>;
 549                 reset-names = "saradc-apb";
 550                 status = "disabled";
 551         };
 552
 553         dmac0: dma-controller@ff2c0000 {
 554                 compatible = "arm,pl330", "arm,primecell";
 555                 reg = <0x0 0xff2c0000 0x0 0x4000>;
 556                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 557                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 558                 arm,pl330-periph-burst;
 559                 clocks = <&cru ACLK_DMAC0>;
 560                 clock-names = "apb_pclk";
 561                 #dma-cells = <1>;
 562         };
 563
 564         dmac1: dma-controller@ff2d0000 {
 565                 compatible = "arm,pl330", "arm,primecell";
 566                 reg = <0x0 0xff2d0000 0x0 0x4000>;
 567                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 568                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 569                 arm,pl330-periph-burst;
 570                 clocks = <&cru ACLK_DMAC1>;
 571                 clock-names = "apb_pclk";
 572                 #dma-cells = <1>;
 573         };
 574
 575         i2s_2ch_0: i2s@ff350000 {
 576                 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
 577                 reg = <0x0 0xff350000 0x0 0x1000>;
 578                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 579                 clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>;
 580                 clock-names = "i2s_clk", "i2s_hclk";
 581                 dmas = <&dmac1 8>, <&dmac1 9>;
 582                 dma-names = "tx", "rx";
 583                 resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>;
 584                 reset-names = "reset-m", "reset-h";
 585                 pinctrl-names = "default";
 586                 pinctrl-0 = <&i2s_2ch_0_sclk
 587                              &i2s_2ch_0_lrck
 588                              &i2s_2ch_0_sdi
 589                              &i2s_2ch_0_sdo>;
 590                 status = "disabled";
 591         };
 592
 593         i2s_2ch_1: i2s@ff360000 {
 594                 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
 595                 reg = <0x0 0xff360000 0x0 0x1000>;
 596                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 597                 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>;
 598                 clock-names = "i2s_clk", "i2s_hclk";
 599                 dmas = <&dmac1 11>;
 600                 dma-names = "rx";
 601                 resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>;
 602                 reset-names = "reset-m", "reset-h";
 603                 status = "disabled";
 604         };
 605
 606         spdif_tx: spdif-tx@ff3a0000 {
 607                 compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif";
 608                 reg = <0x0 0xff3a0000 0x0 0x1000>;
 609                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 610                 clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>;
 611                 clock-names = "mclk", "hclk";
 612                 dmas = <&dmac1 13>;
 613                 dma-names = "tx";
 614                 pinctrl-names = "default";
 615                 pinctrl-0 = <&spdif_out>;
 616                 status = "disabled";
 617         };
 618
 619         usb20_otg: usb@ff400000 {
 620                 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb",
 621                              "snps,dwc2";
 622                 reg = <0x0 0xff400000 0x0 0x40000>;
 623                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 624                 clocks = <&cru HCLK_OTG>;
 625                 clock-names = "otg";
 626                 dr_mode = "otg";
 627                 g-np-tx-fifo-size = <16>;
 628                 g-rx-fifo-size = <280>;
 629                 g-tx-fifo-size = <256 128 128 64 32 16>;
 630                 phys = <&u2phy_otg>;
 631                 phy-names = "usb2-phy";
 632                 status = "disabled";
 633         };
 634
 635         usb_host_ehci: usb@ff440000 {
 636                 compatible = "generic-ehci";
 637                 reg = <0x0 0xff440000 0x0 0x10000>;
 638                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 639                 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
 640                 phys = <&u2phy_host>;
 641                 phy-names = "usb";
 642                 status = "disabled";
 643         };
 644
 645         usb_host_ohci: usb@ff450000 {
 646                 compatible = "generic-ohci";
 647                 reg = <0x0 0xff450000 0x0 0x10000>;
 648                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 649                 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
 650                 phys = <&u2phy_host>;
 651                 phy-names = "usb";
 652                 status = "disabled";
 653         };
 654
 655         sdmmc: mmc@ff480000 {
 656                 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
 657                 reg = <0x0 0xff480000 0x0 0x4000>;
 658                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 659                 bus-width = <4>;
 660                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 661                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 662                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 663                 fifo-depth = <0x100>;
 664                 max-frequency = <150000000>;
 665                 pinctrl-names = "default";
 666                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
 667                 status = "disabled";
 668         };
 669
 670         emmc: mmc@ff490000 {
 671                 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
 672                 reg = <0x0 0xff490000 0x0 0x4000>;
 673                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 674                 bus-width = <8>;
 675                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 676                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 677                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 678                 fifo-depth = <0x100>;
 679                 max-frequency = <150000000>;
 680                 status = "disabled";
 681         };
 682
 683         sdio: mmc@ff4a0000 {
 684                 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
 685                 reg = <0x0 0xff4a0000 0x0 0x4000>;
 686                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 687                 bus-width = <4>;
 688                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 689                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 690                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 691                 fifo-depth = <0x100>;
 692                 max-frequency = <150000000>;
 693                 pinctrl-names = "default";
 694                 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
 695                 status = "disabled";
 696         };
 697
 698         nfc: nand-controller@ff4b0000 {
 699                 compatible = "rockchip,rk3308-nfc",
 700                              "rockchip,rv1108-nfc";
 701                 reg = <0x0 0xff4b0000 0x0 0x4000>;
 702                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 703                 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
 704                 clock-names = "ahb", "nfc";
 705                 assigned-clocks = <&cru SCLK_NANDC>;
 706                 assigned-clock-rates = <150000000>;
 707                 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
 708                              &flash_rdn &flash_rdy &flash_wrn>;
 709                 pinctrl-names = "default";
 710                 status = "disabled";
 711         };
 712
 713         gmac: ethernet@ff4e0000 {
 714                 compatible = "rockchip,rk3308-gmac";
 715                 reg = <0x0 0xff4e0000 0x0 0x10000>;
 716                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 717                 interrupt-names = "macirq";
 718                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>,
 719                          <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>,
 720                          <&cru SCLK_MAC>, <&cru ACLK_MAC>,
 721                          <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>;
 722                 clock-names = "stmmaceth", "mac_clk_rx",
 723                               "mac_clk_tx", "clk_mac_ref",
 724                               "clk_mac_refout", "aclk_mac",
 725                               "pclk_mac", "clk_mac_speed";
 726                 phy-mode = "rmii";
 727                 pinctrl-names = "default";
 728                 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
 729                 resets = <&cru SRST_MAC_A>;
 730                 reset-names = "stmmaceth";
 731                 rockchip,grf = <&grf>;
 732                 status = "disabled";
 733         };
 734
 735         sfc: spi@ff4c0000 {
 736                 compatible = "rockchip,sfc";
 737                 reg = <0x0 0xff4c0000 0x0 0x4000>;
 738                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 739                 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
 740                 clock-names = "clk_sfc", "hclk_sfc";
 741                 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
 742                 pinctrl-names = "default";
 743                 status = "disabled";
 744         };
 745
 746         cru: clock-controller@ff500000 {
 747                 compatible = "rockchip,rk3308-cru";
 748                 reg = <0x0 0xff500000 0x0 0x1000>;
 749                 clocks = <&xin24m>;
 750                 clock-names = "xin24m";
 751                 rockchip,grf = <&grf>;
 752                 #clock-cells = <1>;
 753                 #reset-cells = <1>;
 754                 assigned-clocks = <&cru SCLK_RTC32K>;
 755                 assigned-clock-rates = <32768>;
 756         };
 757
 758         gic: interrupt-controller@ff580000 {
 759                 compatible = "arm,gic-400";
 760                 reg = <0x0 0xff581000 0x0 0x1000>,
 761                       <0x0 0xff582000 0x0 0x2000>,
 762                       <0x0 0xff584000 0x0 0x2000>,
 763                       <0x0 0xff586000 0x0 0x2000>;
 764                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 765                 #interrupt-cells = <3>;
 766                 interrupt-controller;
 767                 #address-cells = <0>;
 768         };
 769
 770         sram: sram@fff80000 {
 771                 compatible = "mmio-sram";
 772                 reg = <0x0 0xfff80000 0x0 0x40000>;
 773                 ranges = <0 0x0 0xfff80000 0x40000>;
 774                 #address-cells = <1>;
 775                 #size-cells = <1>;
 776
 777                 /* reserved for ddr dvfs and system suspend/resume */
 778                 ddr-sram@0 {
 779                         reg = <0x0 0x8000>;
 780                 };
 781
 782                 /* reserved for vad audio buffer */
 783                 vad_sram: vad-sram@8000 {
 784                         reg = <0x8000 0x38000>;
 785                 };
 786         };
 787
 788         pinctrl: pinctrl {
 789                 compatible = "rockchip,rk3308-pinctrl";
 790                 rockchip,grf = <&grf>;
 791                 #address-cells = <2>;
 792                 #size-cells = <2>;
 793                 ranges;
 794
 795                 gpio0: gpio@ff220000 {
 796                         compatible = "rockchip,gpio-bank";
 797                         reg = <0x0 0xff220000 0x0 0x100>;
 798                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 799                         clocks = <&cru PCLK_GPIO0>;
 800                         gpio-controller;
 801                         #gpio-cells = <2>;
 802                         interrupt-controller;
 803                         #interrupt-cells = <2>;
 804                 };
 805
 806                 gpio1: gpio@ff230000 {
 807                         compatible = "rockchip,gpio-bank";
 808                         reg = <0x0 0xff230000 0x0 0x100>;
 809                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 810                         clocks = <&cru PCLK_GPIO1>;
 811                         gpio-controller;
 812                         #gpio-cells = <2>;
 813                         interrupt-controller;
 814                         #interrupt-cells = <2>;
 815                 };
 816
 817                 gpio2: gpio@ff240000 {
 818                         compatible = "rockchip,gpio-bank";
 819                         reg = <0x0 0xff240000 0x0 0x100>;
 820                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 821                         clocks = <&cru PCLK_GPIO2>;
 822                         gpio-controller;
 823                         #gpio-cells = <2>;
 824                         interrupt-controller;
 825                         #interrupt-cells = <2>;
 826                 };
 827
 828                 gpio3: gpio@ff250000 {
 829                         compatible = "rockchip,gpio-bank";
 830                         reg = <0x0 0xff250000 0x0 0x100>;
 831                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 832                         clocks = <&cru PCLK_GPIO3>;
 833                         gpio-controller;
 834                         #gpio-cells = <2>;
 835                         interrupt-controller;
 836                         #interrupt-cells = <2>;
 837                 };
 838
 839                 gpio4: gpio@ff260000 {
 840                         compatible = "rockchip,gpio-bank";
 841                         reg = <0x0 0xff260000 0x0 0x100>;
 842                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 843                         clocks = <&cru PCLK_GPIO4>;
 844                         gpio-controller;
 845                         #gpio-cells = <2>;
 846                         interrupt-controller;
 847                         #interrupt-cells = <2>;
 848                 };
 849
 850                 pcfg_pull_up: pcfg-pull-up {
 851                         bias-pull-up;
 852                 };
 853
 854                 pcfg_pull_down: pcfg-pull-down {
 855                         bias-pull-down;
 856                 };
 857
 858                 pcfg_pull_none: pcfg-pull-none {
 859                         bias-disable;
 860                 };
 861
 862                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 863                         bias-disable;
 864                         drive-strength = <2>;
 865                 };
 866
 867                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 868                         bias-pull-up;
 869                         drive-strength = <2>;
 870                 };
 871
 872                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
 873                         bias-pull-up;
 874                         drive-strength = <4>;
 875                 };
 876
 877                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
 878                         bias-disable;
 879                         drive-strength = <4>;
 880                 };
 881
 882                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 883                         bias-pull-down;
 884                         drive-strength = <4>;
 885                 };
 886
 887                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 888                         bias-disable;
 889                         drive-strength = <8>;
 890                 };
 891
 892                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 893                         bias-pull-up;
 894                         drive-strength = <8>;
 895                 };
 896
 897                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 898                         bias-disable;
 899                         drive-strength = <12>;
 900                 };
 901
 902                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
 903                         bias-pull-up;
 904                         drive-strength = <12>;
 905                 };
 906
 907                 pcfg_pull_none_smt: pcfg-pull-none-smt {
 908                         bias-disable;
 909                         input-schmitt-enable;
 910                 };
 911
 912                 pcfg_output_high: pcfg-output-high {
 913                         output-high;
 914                 };
 915
 916                 pcfg_output_low: pcfg-output-low {
 917                         output-low;
 918                 };
 919
 920                 pcfg_input_high: pcfg-input-high {
 921                         bias-pull-up;
 922                         input-enable;
 923                 };
 924
 925                 pcfg_input: pcfg-input {
 926                         input-enable;
 927                 };
 928
 929                 emmc {
 930                         emmc_clk: emmc-clk {
 931                                 rockchip,pins =
 932                                         <3 RK_PB1 2 &pcfg_pull_none_8ma>;
 933                         };
 934
 935                         emmc_cmd: emmc-cmd {
 936                                 rockchip,pins =
 937                                         <3 RK_PB0 2 &pcfg_pull_up_8ma>;
 938                         };
 939
 940                         emmc_pwren: emmc-pwren {
 941                                 rockchip,pins =
 942                                         <3 RK_PB3 2 &pcfg_pull_none>;
 943                         };
 944
 945                         emmc_rstn: emmc-rstn {
 946                                 rockchip,pins =
 947                                         <3 RK_PB2 2 &pcfg_pull_none>;
 948                         };
 949
 950                         emmc_bus1: emmc-bus1 {
 951                                 rockchip,pins =
 952                                         <3 RK_PA0 2 &pcfg_pull_up_8ma>;
 953                         };
 954
 955                         emmc_bus4: emmc-bus4 {
 956                                 rockchip,pins =
 957                                         <3 RK_PA0 2 &pcfg_pull_up_8ma>,
 958                                         <3 RK_PA1 2 &pcfg_pull_up_8ma>,
 959                                         <3 RK_PA2 2 &pcfg_pull_up_8ma>,
 960                                         <3 RK_PA3 2 &pcfg_pull_up_8ma>;
 961                         };
 962
 963                         emmc_bus8: emmc-bus8 {
 964                                 rockchip,pins =
 965                                         <3 RK_PA0 2 &pcfg_pull_up_8ma>,
 966                                         <3 RK_PA1 2 &pcfg_pull_up_8ma>,
 967                                         <3 RK_PA2 2 &pcfg_pull_up_8ma>,
 968                                         <3 RK_PA3 2 &pcfg_pull_up_8ma>,
 969                                         <3 RK_PA4 2 &pcfg_pull_up_8ma>,
 970                                         <3 RK_PA5 2 &pcfg_pull_up_8ma>,
 971                                         <3 RK_PA6 2 &pcfg_pull_up_8ma>,
 972                                         <3 RK_PA7 2 &pcfg_pull_up_8ma>;
 973                         };
 974                 };
 975
 976                 flash {
 977                         flash_csn0: flash-csn0 {
 978                                 rockchip,pins =
 979                                         <3 RK_PB5 1 &pcfg_pull_none>;
 980                         };
 981
 982                         flash_rdy: flash-rdy {
 983                                 rockchip,pins =
 984                                         <3 RK_PB4 1 &pcfg_pull_none>;
 985                         };
 986
 987                         flash_ale: flash-ale {
 988                                 rockchip,pins =
 989                                         <3 RK_PB3 1 &pcfg_pull_none>;
 990                         };
 991
 992                         flash_cle: flash-cle {
 993                                 rockchip,pins =
 994                                         <3 RK_PB1 1 &pcfg_pull_none>;
 995                         };
 996
 997                         flash_wrn: flash-wrn {
 998                                 rockchip,pins =
 999                                         <3 RK_PB0 1 &pcfg_pull_none>;
1000                         };
1001
1002                         flash_rdn: flash-rdn {
1003                                 rockchip,pins =
1004                                         <3 RK_PB2 1 &pcfg_pull_none>;
1005                         };
1006
1007                         flash_bus8: flash-bus8 {
1008                                 rockchip,pins =
1009                                         <3 RK_PA0 1 &pcfg_pull_up_12ma>,
1010                                         <3 RK_PA1 1 &pcfg_pull_up_12ma>,
1011                                         <3 RK_PA2 1 &pcfg_pull_up_12ma>,
1012                                         <3 RK_PA3 1 &pcfg_pull_up_12ma>,
1013                                         <3 RK_PA4 1 &pcfg_pull_up_12ma>,
1014                                         <3 RK_PA5 1 &pcfg_pull_up_12ma>,
1015                                         <3 RK_PA6 1 &pcfg_pull_up_12ma>,
1016                                         <3 RK_PA7 1 &pcfg_pull_up_12ma>;
1017                         };
1018                 };
1019
1020                 sfc {
1021                         sfc_bus4: sfc-bus4 {
1022                                 rockchip,pins =
1023                                         <3 RK_PA0 3 &pcfg_pull_none>,
1024                                         <3 RK_PA1 3 &pcfg_pull_none>,
1025                                         <3 RK_PA2 3 &pcfg_pull_none>,
1026                                         <3 RK_PA3 3 &pcfg_pull_none>;
1027                         };
1028
1029                         sfc_bus2: sfc-bus2 {
1030                                 rockchip,pins =
1031                                         <3 RK_PA0 3 &pcfg_pull_none>,
1032                                         <3 RK_PA1 3 &pcfg_pull_none>;
1033                         };
1034
1035                         sfc_cs0: sfc-cs0 {
1036                                 rockchip,pins =
1037                                         <3 RK_PA4 3 &pcfg_pull_none>;
1038                         };
1039
1040                         sfc_clk: sfc-clk {
1041                                 rockchip,pins =
1042                                         <3 RK_PA5 3 &pcfg_pull_none>;
1043                         };
1044                 };
1045
1046                 gmac {
1047                         rmii_pins: rmii-pins {
1048                                 rockchip,pins =
1049                                         /* mac_txen */
1050                                         <1 RK_PC1 3 &pcfg_pull_none_12ma>,
1051                                         /* mac_txd1 */
1052                                         <1 RK_PC3 3 &pcfg_pull_none_12ma>,
1053                                         /* mac_txd0 */
1054                                         <1 RK_PC2 3 &pcfg_pull_none_12ma>,
1055                                         /* mac_rxd0 */
1056                                         <1 RK_PC4 3 &pcfg_pull_none>,
1057                                         /* mac_rxd1 */
1058                                         <1 RK_PC5 3 &pcfg_pull_none>,
1059                                         /* mac_rxer */
1060                                         <1 RK_PB7 3 &pcfg_pull_none>,
1061                                         /* mac_rxdv */
1062                                         <1 RK_PC0 3 &pcfg_pull_none>,
1063                                         /* mac_mdio */
1064                                         <1 RK_PB6 3 &pcfg_pull_none>,
1065                                         /* mac_mdc */
1066                                         <1 RK_PB5 3 &pcfg_pull_none>;
1067                         };
1068
1069                         mac_refclk_12ma: mac-refclk-12ma {
1070                                 rockchip,pins =
1071                                         <1 RK_PB4 3 &pcfg_pull_none_12ma>;
1072                         };
1073
1074                         mac_refclk: mac-refclk {
1075                                 rockchip,pins =
1076                                         <1 RK_PB4 3 &pcfg_pull_none>;
1077                         };
1078                 };
1079
1080                 gmac-m1 {
1081                         rmiim1_pins: rmiim1-pins {
1082                                 rockchip,pins =
1083                                         /* mac_txen */
1084                                         <4 RK_PB7 2 &pcfg_pull_none_12ma>,
1085                                         /* mac_txd1 */
1086                                         <4 RK_PA5 2 &pcfg_pull_none_12ma>,
1087                                         /* mac_txd0 */
1088                                         <4 RK_PA4 2 &pcfg_pull_none_12ma>,
1089                                         /* mac_rxd0 */
1090                                         <4 RK_PA2 2 &pcfg_pull_none>,
1091                                         /* mac_rxd1 */
1092                                         <4 RK_PA3 2 &pcfg_pull_none>,
1093                                         /* mac_rxer */
1094                                         <4 RK_PA0 2 &pcfg_pull_none>,
1095                                         /* mac_rxdv */
1096                                         <4 RK_PA1 2 &pcfg_pull_none>,
1097                                         /* mac_mdio */
1098                                         <4 RK_PB6 2 &pcfg_pull_none>,
1099                                         /* mac_mdc */
1100                                         <4 RK_PB5 2 &pcfg_pull_none>;
1101                         };
1102
1103                         macm1_refclk_12ma: macm1-refclk-12ma {
1104                                 rockchip,pins =
1105                                         <4 RK_PB4 2 &pcfg_pull_none_12ma>;
1106                         };
1107
1108                         macm1_refclk: macm1-refclk {
1109                                 rockchip,pins =
1110                                         <4 RK_PB4 2 &pcfg_pull_none>;
1111                         };
1112                 };
1113
1114                 i2c0 {
1115                         i2c0_xfer: i2c0-xfer {
1116                                 rockchip,pins =
1117                                         <1 RK_PD0 2 &pcfg_pull_none_smt>,
1118                                         <1 RK_PD1 2 &pcfg_pull_none_smt>;
1119                         };
1120                 };
1121
1122                 i2c1 {
1123                         i2c1_xfer: i2c1-xfer {
1124                                 rockchip,pins =
1125                                         <0 RK_PB3 1 &pcfg_pull_none_smt>,
1126                                         <0 RK_PB4 1 &pcfg_pull_none_smt>;
1127                         };
1128                 };
1129
1130                 i2c2 {
1131                         i2c2_xfer: i2c2-xfer {
1132                                 rockchip,pins =
1133                                         <2 RK_PA2 3 &pcfg_pull_none_smt>,
1134                                         <2 RK_PA3 3 &pcfg_pull_none_smt>;
1135                         };
1136                 };
1137
1138                 i2c3-m0 {
1139                         i2c3m0_xfer: i2c3m0-xfer {
1140                                 rockchip,pins =
1141                                         <0 RK_PB7 2 &pcfg_pull_none_smt>,
1142                                         <0 RK_PC0 2 &pcfg_pull_none_smt>;
1143                         };
1144                 };
1145
1146                 i2c3-m1 {
1147                         i2c3m1_xfer: i2c3m1-xfer {
1148                                 rockchip,pins =
1149                                         <3 RK_PB4 2 &pcfg_pull_none_smt>,
1150                                         <3 RK_PB5 2 &pcfg_pull_none_smt>;
1151                         };
1152                 };
1153
1154                 i2c3-m2 {
1155                         i2c3m2_xfer: i2c3m2-xfer {
1156                                 rockchip,pins =
1157                                         <2 RK_PA1 3 &pcfg_pull_none_smt>,
1158                                         <2 RK_PA0 3 &pcfg_pull_none_smt>;
1159                         };
1160                 };
1161
1162                 i2s_2ch_0 {
1163                         i2s_2ch_0_mclk: i2s-2ch-0-mclk {
1164                                 rockchip,pins =
1165                                         <4 RK_PB4 1 &pcfg_pull_none>;
1166                         };
1167
1168                         i2s_2ch_0_sclk: i2s-2ch-0-sclk {
1169                                 rockchip,pins =
1170                                         <4 RK_PB5 1 &pcfg_pull_none>;
1171                         };
1172
1173                         i2s_2ch_0_lrck: i2s-2ch-0-lrck {
1174                                 rockchip,pins =
1175                                         <4 RK_PB6 1 &pcfg_pull_none>;
1176                         };
1177
1178                         i2s_2ch_0_sdo: i2s-2ch-0-sdo {
1179                                 rockchip,pins =
1180                                         <4 RK_PB7 1 &pcfg_pull_none>;
1181                         };
1182
1183                         i2s_2ch_0_sdi: i2s-2ch-0-sdi {
1184                                 rockchip,pins =
1185                                         <4 RK_PC0 1 &pcfg_pull_none>;
1186                         };
1187                 };
1188
1189                 i2s_8ch_0 {
1190                         i2s_8ch_0_mclk: i2s-8ch-0-mclk {
1191                                 rockchip,pins =
1192                                         <2 RK_PA4 1 &pcfg_pull_none>;
1193                         };
1194
1195                         i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
1196                                 rockchip,pins =
1197                                         <2 RK_PA5 1 &pcfg_pull_none>;
1198                         };
1199
1200                         i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
1201                                 rockchip,pins =
1202                                         <2 RK_PA6 1 &pcfg_pull_none>;
1203                         };
1204
1205                         i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
1206                                 rockchip,pins =
1207                                         <2 RK_PA7 1 &pcfg_pull_none>;
1208                         };
1209
1210                         i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
1211                                 rockchip,pins =
1212                                         <2 RK_PB0 1 &pcfg_pull_none>;
1213                         };
1214
1215                         i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
1216                                 rockchip,pins =
1217                                         <2 RK_PB1 1 &pcfg_pull_none>;
1218                         };
1219
1220                         i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
1221                                 rockchip,pins =
1222                                         <2 RK_PB2 1 &pcfg_pull_none>;
1223                         };
1224
1225                         i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
1226                                 rockchip,pins =
1227                                         <2 RK_PB3 1 &pcfg_pull_none>;
1228                         };
1229
1230                         i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 {
1231                                 rockchip,pins =
1232                                         <2 RK_PB4 1 &pcfg_pull_none>;
1233                         };
1234
1235                         i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 {
1236                                 rockchip,pins =
1237                                         <2 RK_PB5 1 &pcfg_pull_none>;
1238                         };
1239
1240                         i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 {
1241                                 rockchip,pins =
1242                                         <2 RK_PB6 1 &pcfg_pull_none>;
1243                         };
1244
1245                         i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 {
1246                                 rockchip,pins =
1247                                         <2 RK_PB7 1 &pcfg_pull_none>;
1248                         };
1249
1250                         i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 {
1251                                 rockchip,pins =
1252                                         <2 RK_PC0 1 &pcfg_pull_none>;
1253                         };
1254                 };
1255
1256                 i2s_8ch_1_m0 {
1257                         i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk {
1258                                 rockchip,pins =
1259                                         <1 RK_PA2 2 &pcfg_pull_none>;
1260                         };
1261
1262                         i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx {
1263                                 rockchip,pins =
1264                                         <1 RK_PA3 2 &pcfg_pull_none>;
1265                         };
1266
1267                         i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx {
1268                                 rockchip,pins =
1269                                         <1 RK_PA4 2 &pcfg_pull_none>;
1270                         };
1271
1272                         i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx {
1273                                 rockchip,pins =
1274                                         <1 RK_PA5 2 &pcfg_pull_none>;
1275                         };
1276
1277                         i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx {
1278                                 rockchip,pins =
1279                                         <1 RK_PA6 2 &pcfg_pull_none>;
1280                         };
1281
1282                         i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 {
1283                                 rockchip,pins =
1284                                         <1 RK_PA7 2 &pcfg_pull_none>;
1285                         };
1286
1287                         i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 {
1288                                 rockchip,pins =
1289                                         <1 RK_PB0 2 &pcfg_pull_none>;
1290                         };
1291
1292                         i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 {
1293                                 rockchip,pins =
1294                                         <1 RK_PB1 2 &pcfg_pull_none>;
1295                         };
1296
1297                         i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 {
1298                                 rockchip,pins =
1299                                         <1 RK_PB2 2 &pcfg_pull_none>;
1300                         };
1301
1302                         i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 {
1303                                 rockchip,pins =
1304                                         <1 RK_PB3 2 &pcfg_pull_none>;
1305                         };
1306                 };
1307
1308                 i2s_8ch_1_m1 {
1309                         i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk {
1310                                 rockchip,pins =
1311                                         <1 RK_PB4 2 &pcfg_pull_none>;
1312                         };
1313
1314                         i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx {
1315                                 rockchip,pins =
1316                                         <1 RK_PB5 2 &pcfg_pull_none>;
1317                         };
1318
1319                         i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx {
1320                                 rockchip,pins =
1321                                         <1 RK_PB6 2 &pcfg_pull_none>;
1322                         };
1323
1324                         i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx {
1325                                 rockchip,pins =
1326                                         <1 RK_PB7 2 &pcfg_pull_none>;
1327                         };
1328
1329                         i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx {
1330                                 rockchip,pins =
1331                                         <1 RK_PC0 2 &pcfg_pull_none>;
1332                         };
1333
1334                         i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 {
1335                                 rockchip,pins =
1336                                         <1 RK_PC1 2 &pcfg_pull_none>;
1337                         };
1338
1339                         i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 {
1340                                 rockchip,pins =
1341                                         <1 RK_PC2 2 &pcfg_pull_none>;
1342                         };
1343
1344                         i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 {
1345                                 rockchip,pins =
1346                                         <1 RK_PC3 2 &pcfg_pull_none>;
1347                         };
1348
1349                         i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 {
1350                                 rockchip,pins =
1351                                         <1 RK_PC4 2 &pcfg_pull_none>;
1352                         };
1353
1354                         i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 {
1355                                 rockchip,pins =
1356                                         <1 RK_PC5 2 &pcfg_pull_none>;
1357                         };
1358                 };
1359
1360                 pdm_m0 {
1361                         pdm_m0_clk: pdm-m0-clk {
1362                                 rockchip,pins =
1363                                         <1 RK_PA4 3 &pcfg_pull_none>;
1364                         };
1365
1366                         pdm_m0_sdi0: pdm-m0-sdi0 {
1367                                 rockchip,pins =
1368                                         <1 RK_PB3 3 &pcfg_pull_none>;
1369                         };
1370
1371                         pdm_m0_sdi1: pdm-m0-sdi1 {
1372                                 rockchip,pins =
1373                                         <1 RK_PB2 3 &pcfg_pull_none>;
1374                         };
1375
1376                         pdm_m0_sdi2: pdm-m0-sdi2 {
1377                                 rockchip,pins =
1378                                         <1 RK_PB1 3 &pcfg_pull_none>;
1379                         };
1380
1381                         pdm_m0_sdi3: pdm-m0-sdi3 {
1382                                 rockchip,pins =
1383                                         <1 RK_PB0 3 &pcfg_pull_none>;
1384                         };
1385                 };
1386
1387                 pdm_m1 {
1388                         pdm_m1_clk: pdm-m1-clk {
1389                                 rockchip,pins =
1390                                         <1 RK_PB6 4 &pcfg_pull_none>;
1391                         };
1392
1393                         pdm_m1_sdi0: pdm-m1-sdi0 {
1394                                 rockchip,pins =
1395                                         <1 RK_PC5 4 &pcfg_pull_none>;
1396                         };
1397
1398                         pdm_m1_sdi1: pdm-m1-sdi1 {
1399                                 rockchip,pins =
1400                                         <1 RK_PC4 4 &pcfg_pull_none>;
1401                         };
1402
1403                         pdm_m1_sdi2: pdm-m1-sdi2 {
1404                                 rockchip,pins =
1405                                         <1 RK_PC3 4 &pcfg_pull_none>;
1406                         };
1407
1408                         pdm_m1_sdi3: pdm-m1-sdi3 {
1409                                 rockchip,pins =
1410                                         <1 RK_PC2 4 &pcfg_pull_none>;
1411                         };
1412                 };
1413
1414                 pdm_m2 {
1415                         pdm_m2_clkm: pdm-m2-clkm {
1416                                 rockchip,pins =
1417                                         <2 RK_PA4 3 &pcfg_pull_none>;
1418                         };
1419
1420                         pdm_m2_clk: pdm-m2-clk {
1421                                 rockchip,pins =
1422                                         <2 RK_PA6 2 &pcfg_pull_none>;
1423                         };
1424
1425                         pdm_m2_sdi0: pdm-m2-sdi0 {
1426                                 rockchip,pins =
1427                                         <2 RK_PB5 2 &pcfg_pull_none>;
1428                         };
1429
1430                         pdm_m2_sdi1: pdm-m2-sdi1 {
1431                                 rockchip,pins =
1432                                         <2 RK_PB6 2 &pcfg_pull_none>;
1433                         };
1434
1435                         pdm_m2_sdi2: pdm-m2-sdi2 {
1436                                 rockchip,pins =
1437                                         <2 RK_PB7 2 &pcfg_pull_none>;
1438                         };
1439
1440                         pdm_m2_sdi3: pdm-m2-sdi3 {
1441                                 rockchip,pins =
1442                                         <2 RK_PC0 2 &pcfg_pull_none>;
1443                         };
1444                 };
1445
1446                 pwm0 {
1447                         pwm0_pin: pwm0-pin {
1448                                 rockchip,pins =
1449                                         <0 RK_PB5 1 &pcfg_pull_none>;
1450                         };
1451
1452                         pwm0_pin_pull_down: pwm0-pin-pull-down {
1453                                 rockchip,pins =
1454                                         <0 RK_PB5 1 &pcfg_pull_down>;
1455                         };
1456                 };
1457
1458                 pwm1 {
1459                         pwm1_pin: pwm1-pin {
1460                                 rockchip,pins =
1461                                         <0 RK_PB6 1 &pcfg_pull_none>;
1462                         };
1463
1464                         pwm1_pin_pull_down: pwm1-pin-pull-down {
1465                                 rockchip,pins =
1466                                         <0 RK_PB6 1 &pcfg_pull_down>;
1467                         };
1468                 };
1469
1470                 pwm2 {
1471                         pwm2_pin: pwm2-pin {
1472                                 rockchip,pins =
1473                                         <0 RK_PB7 1 &pcfg_pull_none>;
1474                         };
1475
1476                         pwm2_pin_pull_down: pwm2-pin-pull-down {
1477                                 rockchip,pins =
1478                                         <0 RK_PB7 1 &pcfg_pull_down>;
1479                         };
1480                 };
1481
1482                 pwm3 {
1483                         pwm3_pin: pwm3-pin {
1484                                 rockchip,pins =
1485                                         <0 RK_PC0 1 &pcfg_pull_none>;
1486                         };
1487
1488                         pwm3_pin_pull_down: pwm3-pin-pull-down {
1489                                 rockchip,pins =
1490                                         <0 RK_PC0 1 &pcfg_pull_down>;
1491                         };
1492                 };
1493
1494                 pwm4 {
1495                         pwm4_pin: pwm4-pin {
1496                                 rockchip,pins =
1497                                         <0 RK_PA1 2 &pcfg_pull_none>;
1498                         };
1499
1500                         pwm4_pin_pull_down: pwm4-pin-pull-down {
1501                                 rockchip,pins =
1502                                         <0 RK_PA1 2 &pcfg_pull_down>;
1503                         };
1504                 };
1505
1506                 pwm5 {
1507                         pwm5_pin: pwm5-pin {
1508                                 rockchip,pins =
1509                                         <0 RK_PC1 2 &pcfg_pull_none>;
1510                         };
1511
1512                         pwm5_pin_pull_down: pwm5-pin-pull-down {
1513                                 rockchip,pins =
1514                                         <0 RK_PC1 2 &pcfg_pull_down>;
1515                         };
1516                 };
1517
1518                 pwm6 {
1519                         pwm6_pin: pwm6-pin {
1520                                 rockchip,pins =
1521                                         <0 RK_PC2 2 &pcfg_pull_none>;
1522                         };
1523
1524                         pwm6_pin_pull_down: pwm6-pin-pull-down {
1525                                 rockchip,pins =
1526                                         <0 RK_PC2 2 &pcfg_pull_down>;
1527                         };
1528                 };
1529
1530                 pwm7 {
1531                         pwm7_pin: pwm7-pin {
1532                                 rockchip,pins =
1533                                         <2 RK_PB0 2 &pcfg_pull_none>;
1534                         };
1535
1536                         pwm7_pin_pull_down: pwm7-pin-pull-down {
1537                                 rockchip,pins =
1538                                         <2 RK_PB0 2 &pcfg_pull_down>;
1539                         };
1540                 };
1541
1542                 pwm8 {
1543                         pwm8_pin: pwm8-pin {
1544                                 rockchip,pins =
1545                                         <2 RK_PB2 2 &pcfg_pull_none>;
1546                         };
1547
1548                         pwm8_pin_pull_down: pwm8-pin-pull-down {
1549                                 rockchip,pins =
1550                                         <2 RK_PB2 2 &pcfg_pull_down>;
1551                         };
1552                 };
1553
1554                 pwm9 {
1555                         pwm9_pin: pwm9-pin {
1556                                 rockchip,pins =
1557                                         <2 RK_PB3 2 &pcfg_pull_none>;
1558                         };
1559
1560                         pwm9_pin_pull_down: pwm9-pin-pull-down {
1561                                 rockchip,pins =
1562                                         <2 RK_PB3 2 &pcfg_pull_down>;
1563                         };
1564                 };
1565
1566                 pwm10 {
1567                         pwm10_pin: pwm10-pin {
1568                                 rockchip,pins =
1569                                         <2 RK_PB4 2 &pcfg_pull_none>;
1570                         };
1571
1572                         pwm10_pin_pull_down: pwm10-pin-pull-down {
1573                                 rockchip,pins =
1574                                         <2 RK_PB4 2 &pcfg_pull_down>;
1575                         };
1576                 };
1577
1578                 pwm11 {
1579                         pwm11_pin: pwm11-pin {
1580                                 rockchip,pins =
1581                                         <2 RK_PC0 4 &pcfg_pull_none>;
1582                         };
1583
1584                         pwm11_pin_pull_down: pwm11-pin-pull-down {
1585                                 rockchip,pins =
1586                                         <2 RK_PC0 4 &pcfg_pull_down>;
1587                         };
1588                 };
1589
1590                 rtc {
1591                         rtc_32k: rtc-32k {
1592                                 rockchip,pins =
1593                                         <0 RK_PC3 1 &pcfg_pull_none>;
1594                         };
1595                 };
1596
1597                 sdmmc {
1598                         sdmmc_clk: sdmmc-clk {
1599                                 rockchip,pins =
1600                                         <4 RK_PD5 1 &pcfg_pull_none_4ma>;
1601                         };
1602
1603                         sdmmc_cmd: sdmmc-cmd {
1604                                 rockchip,pins =
1605                                         <4 RK_PD4 1 &pcfg_pull_up_4ma>;
1606                         };
1607
1608                         sdmmc_det: sdmmc-det {
1609                                 rockchip,pins =
1610                                         <0 RK_PA3 1 &pcfg_pull_up_4ma>;
1611                         };
1612
1613                         sdmmc_pwren: sdmmc-pwren {
1614                                 rockchip,pins =
1615                                         <4 RK_PD6 1 &pcfg_pull_none_4ma>;
1616                         };
1617
1618                         sdmmc_bus1: sdmmc-bus1 {
1619                                 rockchip,pins =
1620                                         <4 RK_PD0 1 &pcfg_pull_up_4ma>;
1621                         };
1622
1623                         sdmmc_bus4: sdmmc-bus4 {
1624                                 rockchip,pins =
1625                                         <4 RK_PD0 1 &pcfg_pull_up_4ma>,
1626                                         <4 RK_PD1 1 &pcfg_pull_up_4ma>,
1627                                         <4 RK_PD2 1 &pcfg_pull_up_4ma>,
1628                                         <4 RK_PD3 1 &pcfg_pull_up_4ma>;
1629                         };
1630                 };
1631
1632                 sdio {
1633                         sdio_clk: sdio-clk {
1634                                 rockchip,pins =
1635                                         <4 RK_PA5 1 &pcfg_pull_none_8ma>;
1636                         };
1637
1638                         sdio_cmd: sdio-cmd {
1639                                 rockchip,pins =
1640                                         <4 RK_PA4 1 &pcfg_pull_up_8ma>;
1641                         };
1642
1643                         sdio_pwren: sdio-pwren {
1644                                 rockchip,pins =
1645                                         <0 RK_PA2 1 &pcfg_pull_none_8ma>;
1646                         };
1647
1648                         sdio_wrpt: sdio-wrpt {
1649                                 rockchip,pins =
1650                                         <0 RK_PA1 1 &pcfg_pull_none_8ma>;
1651                         };
1652
1653                         sdio_intn: sdio-intn {
1654                                 rockchip,pins =
1655                                         <0 RK_PA0 1 &pcfg_pull_none_8ma>;
1656                         };
1657
1658                         sdio_bus1: sdio-bus1 {
1659                                 rockchip,pins =
1660                                         <4 RK_PA0 1 &pcfg_pull_up_8ma>;
1661                         };
1662
1663                         sdio_bus4: sdio-bus4 {
1664                                 rockchip,pins =
1665                                         <4 RK_PA0 1 &pcfg_pull_up_8ma>,
1666                                         <4 RK_PA1 1 &pcfg_pull_up_8ma>,
1667                                         <4 RK_PA2 1 &pcfg_pull_up_8ma>,
1668                                         <4 RK_PA3 1 &pcfg_pull_up_8ma>;
1669                         };
1670                 };
1671
1672                 spdif_in {
1673                         spdif_in: spdif-in {
1674                                 rockchip,pins =
1675                                         <0 RK_PC2 1 &pcfg_pull_none>;
1676                         };
1677                 };
1678
1679                 spdif_out {
1680                         spdif_out: spdif-out {
1681                                 rockchip,pins =
1682                                         <0 RK_PC1 1 &pcfg_pull_none>;
1683                         };
1684                 };
1685
1686                 spi0 {
1687                         spi0_clk: spi0-clk {
1688                                 rockchip,pins =
1689                                         <2 RK_PA2 2 &pcfg_pull_up_4ma>;
1690                         };
1691
1692                         spi0_csn0: spi0-csn0 {
1693                                 rockchip,pins =
1694                                         <2 RK_PA3 2 &pcfg_pull_up_4ma>;
1695                         };
1696
1697                         spi0_miso: spi0-miso {
1698                                 rockchip,pins =
1699                                         <2 RK_PA0 2 &pcfg_pull_up_4ma>;
1700                         };
1701
1702                         spi0_mosi: spi0-mosi {
1703                                 rockchip,pins =
1704                                         <2 RK_PA1 2 &pcfg_pull_up_4ma>;
1705                         };
1706                 };
1707
1708                 spi1 {
1709                         spi1_clk: spi1-clk {
1710                                 rockchip,pins =
1711                                         <3 RK_PB3 3 &pcfg_pull_up_4ma>;
1712                         };
1713
1714                         spi1_csn0: spi1-csn0 {
1715                                 rockchip,pins =
1716                                         <3 RK_PB5 3 &pcfg_pull_up_4ma>;
1717                         };
1718
1719                         spi1_miso: spi1-miso {
1720                                 rockchip,pins =
1721                                         <3 RK_PB2 3 &pcfg_pull_up_4ma>;
1722                         };
1723
1724                         spi1_mosi: spi1-mosi {
1725                                 rockchip,pins =
1726                                         <3 RK_PB4 3 &pcfg_pull_up_4ma>;
1727                         };
1728                 };
1729
1730                 spi1-m1 {
1731                         spi1m1_miso: spi1m1-miso {
1732                                 rockchip,pins =
1733                                         <2 RK_PA4 2 &pcfg_pull_up_4ma>;
1734                         };
1735
1736                         spi1m1_mosi: spi1m1-mosi {
1737                                 rockchip,pins =
1738                                         <2 RK_PA5 2 &pcfg_pull_up_4ma>;
1739                         };
1740
1741                         spi1m1_clk: spi1m1-clk {
1742                                 rockchip,pins =
1743                                         <2 RK_PA7 2 &pcfg_pull_up_4ma>;
1744                         };
1745
1746                         spi1m1_csn0: spi1m1-csn0 {
1747                                 rockchip,pins =
1748                                         <2 RK_PB1 2 &pcfg_pull_up_4ma>;
1749                         };
1750                 };
1751
1752                 spi2 {
1753                         spi2_clk: spi2-clk {
1754                                 rockchip,pins =
1755                                         <1 RK_PD0 3 &pcfg_pull_up_4ma>;
1756                         };
1757
1758                         spi2_csn0: spi2-csn0 {
1759                                 rockchip,pins =
1760                                         <1 RK_PD1 3 &pcfg_pull_up_4ma>;
1761                         };
1762
1763                         spi2_miso: spi2-miso {
1764                                 rockchip,pins =
1765                                         <1 RK_PC6 3 &pcfg_pull_up_4ma>;
1766                         };
1767
1768                         spi2_mosi: spi2-mosi {
1769                                 rockchip,pins =
1770                                         <1 RK_PC7 3 &pcfg_pull_up_4ma>;
1771                         };
1772                 };
1773
1774                 tsadc {
1775                         tsadc_otp_pin: tsadc-otp-pin {
1776                                 rockchip,pins =
1777                                         <0 RK_PB2 0 &pcfg_pull_none>;
1778                         };
1779
1780                         tsadc_otp_out: tsadc-otp-out {
1781                                 rockchip,pins =
1782                                         <0 RK_PB2 1 &pcfg_pull_none>;
1783                         };
1784                 };
1785
1786                 uart0 {
1787                         uart0_xfer: uart0-xfer {
1788                                 rockchip,pins =
1789                                         <2 RK_PA1 1 &pcfg_pull_up>,
1790                                         <2 RK_PA0 1 &pcfg_pull_up>;
1791                         };
1792
1793                         uart0_cts: uart0-cts {
1794                                 rockchip,pins =
1795                                         <2 RK_PA2 1 &pcfg_pull_none>;
1796                         };
1797
1798                         uart0_rts: uart0-rts {
1799                                 rockchip,pins =
1800                                         <2 RK_PA3 1 &pcfg_pull_none>;
1801                         };
1802
1803                         uart0_rts_pin: uart0-rts-pin {
1804                                 rockchip,pins =
1805                                         <2 RK_PA3 0 &pcfg_pull_none>;
1806                         };
1807                 };
1808
1809                 uart1 {
1810                         uart1_xfer: uart1-xfer {
1811                                 rockchip,pins =
1812                                         <1 RK_PD1 1 &pcfg_pull_up>,
1813                                         <1 RK_PD0 1 &pcfg_pull_up>;
1814                         };
1815
1816                         uart1_cts: uart1-cts {
1817                                 rockchip,pins =
1818                                         <1 RK_PC6 1 &pcfg_pull_none>;
1819                         };
1820
1821                         uart1_rts: uart1-rts {
1822                                 rockchip,pins =
1823                                         <1 RK_PC7 1 &pcfg_pull_none>;
1824                         };
1825                 };
1826
1827                 uart2-m0 {
1828                         uart2m0_xfer: uart2m0-xfer {
1829                                 rockchip,pins =
1830                                         <1 RK_PC7 2 &pcfg_pull_up>,
1831                                         <1 RK_PC6 2 &pcfg_pull_up>;
1832                         };
1833                 };
1834
1835                 uart2-m1 {
1836                         uart2m1_xfer: uart2m1-xfer {
1837                                 rockchip,pins =
1838                                         <4 RK_PD3 2 &pcfg_pull_up>,
1839                                         <4 RK_PD2 2 &pcfg_pull_up>;
1840                         };
1841                 };
1842
1843                 uart3 {
1844                         uart3_xfer: uart3-xfer {
1845                                 rockchip,pins =
1846                                         <3 RK_PB5 4 &pcfg_pull_up>,
1847                                         <3 RK_PB4 4 &pcfg_pull_up>;
1848                         };
1849                 };
1850
1851                 uart3-m1 {
1852                         uart3m1_xfer: uart3m1-xfer {
1853                                 rockchip,pins =
1854                                         <0 RK_PC2 3 &pcfg_pull_up>,
1855                                         <0 RK_PC1 3 &pcfg_pull_up>;
1856                         };
1857                 };
1858
1859                 uart4 {
1860                         uart4_xfer: uart4-xfer {
1861                                 rockchip,pins =
1862                                         <4 RK_PB1 1 &pcfg_pull_up>,
1863                                         <4 RK_PB0 1 &pcfg_pull_up>;
1864                         };
1865
1866                         uart4_cts: uart4-cts {
1867                                 rockchip,pins =
1868                                         <4 RK_PA6 1 &pcfg_pull_none>;
1869                         };
1870
1871                         uart4_rts: uart4-rts {
1872                                 rockchip,pins =
1873                                         <4 RK_PA7 1 &pcfg_pull_none>;
1874                         };
1875
1876                         uart4_rts_pin: uart4-rts-pin {
1877                                 rockchip,pins =
1878                                         <4 RK_PA7 0 &pcfg_pull_none>;
1879                         };
1880                 };
1881         };
1882 };