src/arm64/rockchip/rk3399.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/clock/rk3399-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/rk3399-power.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 / {
  15         compatible = "rockchip,rk3399";
  16
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 ethernet0 = &gmac;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 i2c6 = &i2c6;
  30                 i2c7 = &i2c7;
  31                 i2c8 = &i2c8;
  32                 serial0 = &uart0;
  33                 serial1 = &uart1;
  34                 serial2 = &uart2;
  35                 serial3 = &uart3;
  36                 serial4 = &uart4;
  37         };
  38
  39         cpus {
  40                 #address-cells = <2>;
  41                 #size-cells = <0>;
  42
  43                 cpu-map {
  44                         cluster0 {
  45                                 core0 {
  46                                         cpu = <&cpu_l0>;
  47                                 };
  48                                 core1 {
  49                                         cpu = <&cpu_l1>;
  50                                 };
  51                                 core2 {
  52                                         cpu = <&cpu_l2>;
  53                                 };
  54                                 core3 {
  55                                         cpu = <&cpu_l3>;
  56                                 };
  57                         };
  58
  59                         cluster1 {
  60                                 core0 {
  61                                         cpu = <&cpu_b0>;
  62                                 };
  63                                 core1 {
  64                                         cpu = <&cpu_b1>;
  65                                 };
  66                         };
  67                 };
  68
  69                 cpu_l0: cpu@0 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a53";
  72                         reg = <0x0 0x0>;
  73                         enable-method = "psci";
  74                         capacity-dmips-mhz = <485>;
  75                         clocks = <&cru ARMCLKL>;
  76                         #cooling-cells = <2>; /* min followed by max */
  77                         dynamic-power-coefficient = <100>;
  78                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  79                 };
  80
  81                 cpu_l1: cpu@1 {
  82                         device_type = "cpu";
  83                         compatible = "arm,cortex-a53";
  84                         reg = <0x0 0x1>;
  85                         enable-method = "psci";
  86                         capacity-dmips-mhz = <485>;
  87                         clocks = <&cru ARMCLKL>;
  88                         #cooling-cells = <2>; /* min followed by max */
  89                         dynamic-power-coefficient = <100>;
  90                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  91                 };
  92
  93                 cpu_l2: cpu@2 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a53";
  96                         reg = <0x0 0x2>;
  97                         enable-method = "psci";
  98                         capacity-dmips-mhz = <485>;
  99                         clocks = <&cru ARMCLKL>;
 100                         #cooling-cells = <2>; /* min followed by max */
 101                         dynamic-power-coefficient = <100>;
 102                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 103                 };
 104
 105                 cpu_l3: cpu@3 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a53";
 108                         reg = <0x0 0x3>;
 109                         enable-method = "psci";
 110                         capacity-dmips-mhz = <485>;
 111                         clocks = <&cru ARMCLKL>;
 112                         #cooling-cells = <2>; /* min followed by max */
 113                         dynamic-power-coefficient = <100>;
 114                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 115                 };
 116
 117                 cpu_b0: cpu@100 {
 118                         device_type = "cpu";
 119                         compatible = "arm,cortex-a72";
 120                         reg = <0x0 0x100>;
 121                         enable-method = "psci";
 122                         capacity-dmips-mhz = <1024>;
 123                         clocks = <&cru ARMCLKB>;
 124                         #cooling-cells = <2>; /* min followed by max */
 125                         dynamic-power-coefficient = <436>;
 126                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 127                 };
 128
 129                 cpu_b1: cpu@101 {
 130                         device_type = "cpu";
 131                         compatible = "arm,cortex-a72";
 132                         reg = <0x0 0x101>;
 133                         enable-method = "psci";
 134                         capacity-dmips-mhz = <1024>;
 135                         clocks = <&cru ARMCLKB>;
 136                         #cooling-cells = <2>; /* min followed by max */
 137                         dynamic-power-coefficient = <436>;
 138                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 139                 };
 140
 141                 idle-states {
 142                         entry-method = "psci";
 143
 144                         CPU_SLEEP: cpu-sleep {
 145                                 compatible = "arm,idle-state";
 146                                 local-timer-stop;
 147                                 arm,psci-suspend-param = <0x0010000>;
 148                                 entry-latency-us = <120>;
 149                                 exit-latency-us = <250>;
 150                                 min-residency-us = <900>;
 151                         };
 152
 153                         CLUSTER_SLEEP: cluster-sleep {
 154                                 compatible = "arm,idle-state";
 155                                 local-timer-stop;
 156                                 arm,psci-suspend-param = <0x1010000>;
 157                                 entry-latency-us = <400>;
 158                                 exit-latency-us = <500>;
 159                                 min-residency-us = <2000>;
 160                         };
 161                 };
 162         };
 163
 164         display-subsystem {
 165                 compatible = "rockchip,display-subsystem";
 166                 ports = <&vopl_out>, <&vopb_out>;
 167         };
 168
 169         pmu_a53 {
 170                 compatible = "arm,cortex-a53-pmu";
 171                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 172         };
 173
 174         pmu_a72 {
 175                 compatible = "arm,cortex-a72-pmu";
 176                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 177         };
 178
 179         psci {
 180                 compatible = "arm,psci-1.0";
 181                 method = "smc";
 182         };
 183
 184         timer {
 185                 compatible = "arm,armv8-timer";
 186                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 187                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 188                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 189                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 190                 arm,no-tick-in-suspend;
 191         };
 192
 193         xin24m: xin24m {
 194                 compatible = "fixed-clock";
 195                 clock-frequency = <24000000>;
 196                 clock-output-names = "xin24m";
 197                 #clock-cells = <0>;
 198         };
 199
 200         amba: bus {
 201                 compatible = "simple-bus";
 202                 #address-cells = <2>;
 203                 #size-cells = <2>;
 204                 ranges;
 205
 206                 dmac_bus: dma-controller@ff6d0000 {
 207                         compatible = "arm,pl330", "arm,primecell";
 208                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 209                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 210                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 211                         #dma-cells = <1>;
 212                         clocks = <&cru ACLK_DMAC0_PERILP>;
 213                         clock-names = "apb_pclk";
 214                 };
 215
 216                 dmac_peri: dma-controller@ff6e0000 {
 217                         compatible = "arm,pl330", "arm,primecell";
 218                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 219                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 220                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 221                         #dma-cells = <1>;
 222                         clocks = <&cru ACLK_DMAC1_PERILP>;
 223                         clock-names = "apb_pclk";
 224                 };
 225         };
 226
 227         pcie0: pcie@f8000000 {
 228                 compatible = "rockchip,rk3399-pcie";
 229                 reg = <0x0 0xf8000000 0x0 0x2000000>,
 230                       <0x0 0xfd000000 0x0 0x1000000>;
 231                 reg-names = "axi-base", "apb-base";
 232                 #address-cells = <3>;
 233                 #size-cells = <2>;
 234                 #interrupt-cells = <1>;
 235                 aspm-no-l0s;
 236                 bus-range = <0x0 0x1f>;
 237                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
 238                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
 239                 clock-names = "aclk", "aclk-perf",
 240                               "hclk", "pm";
 241                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
 242                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
 243                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
 244                 interrupt-names = "sys", "legacy", "client";
 245                 interrupt-map-mask = <0 0 0 7>;
 246                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
 247                                 <0 0 0 2 &pcie0_intc 1>,
 248                                 <0 0 0 3 &pcie0_intc 2>,
 249                                 <0 0 0 4 &pcie0_intc 3>;
 250                 linux,pci-domain = <0>;
 251                 max-link-speed = <1>;
 252                 msi-map = <0x0 &its 0x0 0x1000>;
 253                 phys = <&pcie_phy 0>, <&pcie_phy 1>,
 254                        <&pcie_phy 2>, <&pcie_phy 3>;
 255                 phy-names = "pcie-phy-0", "pcie-phy-1",
 256                             "pcie-phy-2", "pcie-phy-3";
 257                 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
 258                           0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
 259                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
 260                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
 261                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
 262                          <&cru SRST_A_PCIE>;
 263                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
 264                               "pm", "pclk", "aclk";
 265                 status = "disabled";
 266
 267                 pcie0_intc: interrupt-controller {
 268                         interrupt-controller;
 269                         #address-cells = <0>;
 270                         #interrupt-cells = <1>;
 271                 };
 272         };
 273
 274         gmac: ethernet@fe300000 {
 275                 compatible = "rockchip,rk3399-gmac";
 276                 reg = <0x0 0xfe300000 0x0 0x10000>;
 277                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 278                 interrupt-names = "macirq";
 279                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 280                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 281                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 282                          <&cru PCLK_GMAC>;
 283                 clock-names = "stmmaceth", "mac_clk_rx",
 284                               "mac_clk_tx", "clk_mac_ref",
 285                               "clk_mac_refout", "aclk_mac",
 286                               "pclk_mac";
 287                 power-domains = <&power RK3399_PD_GMAC>;
 288                 resets = <&cru SRST_A_GMAC>;
 289                 reset-names = "stmmaceth";
 290                 rockchip,grf = <&grf>;
 291                 snps,txpbl = <0x4>;
 292                 status = "disabled";
 293         };
 294
 295         sdio0: mmc@fe310000 {
 296                 compatible = "rockchip,rk3399-dw-mshc",
 297                              "rockchip,rk3288-dw-mshc";
 298                 reg = <0x0 0xfe310000 0x0 0x4000>;
 299                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 300                 max-frequency = <150000000>;
 301                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 302                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 303                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 304                 fifo-depth = <0x100>;
 305                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 306                 resets = <&cru SRST_SDIO0>;
 307                 reset-names = "reset";
 308                 status = "disabled";
 309         };
 310
 311         sdmmc: mmc@fe320000 {
 312                 compatible = "rockchip,rk3399-dw-mshc",
 313                              "rockchip,rk3288-dw-mshc";
 314                 reg = <0x0 0xfe320000 0x0 0x4000>;
 315                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 316                 max-frequency = <150000000>;
 317                 assigned-clocks = <&cru HCLK_SD>;
 318                 assigned-clock-rates = <200000000>;
 319                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 320                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 321                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 322                 fifo-depth = <0x100>;
 323                 power-domains = <&power RK3399_PD_SD>;
 324                 resets = <&cru SRST_SDMMC>;
 325                 reset-names = "reset";
 326                 status = "disabled";
 327         };
 328
 329         sdhci: sdhci@fe330000 {
 330                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 331                 reg = <0x0 0xfe330000 0x0 0x10000>;
 332                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 333                 arasan,soc-ctl-syscon = <&grf>;
 334                 assigned-clocks = <&cru SCLK_EMMC>;
 335                 assigned-clock-rates = <200000000>;
 336                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 337                 clock-names = "clk_xin", "clk_ahb";
 338                 clock-output-names = "emmc_cardclock";
 339                 #clock-cells = <0>;
 340                 phys = <&emmc_phy>;
 341                 phy-names = "phy_arasan";
 342                 power-domains = <&power RK3399_PD_EMMC>;
 343                 disable-cqe-dcmd;
 344                 status = "disabled";
 345         };
 346
 347         usb_host0_ehci: usb@fe380000 {
 348                 compatible = "generic-ehci";
 349                 reg = <0x0 0xfe380000 0x0 0x20000>;
 350                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 351                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 352                          <&u2phy0>;
 353                 phys = <&u2phy0_host>;
 354                 phy-names = "usb";
 355                 status = "disabled";
 356         };
 357
 358         usb_host0_ohci: usb@fe3a0000 {
 359                 compatible = "generic-ohci";
 360                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 361                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 362                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 363                          <&u2phy0>;
 364                 phys = <&u2phy0_host>;
 365                 phy-names = "usb";
 366                 status = "disabled";
 367         };
 368
 369         usb_host1_ehci: usb@fe3c0000 {
 370                 compatible = "generic-ehci";
 371                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 372                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 373                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 374                          <&u2phy1>;
 375                 phys = <&u2phy1_host>;
 376                 phy-names = "usb";
 377                 status = "disabled";
 378         };
 379
 380         usb_host1_ohci: usb@fe3e0000 {
 381                 compatible = "generic-ohci";
 382                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 383                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 384                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 385                          <&u2phy1>;
 386                 phys = <&u2phy1_host>;
 387                 phy-names = "usb";
 388                 status = "disabled";
 389         };
 390
 391         usbdrd3_0: usb@fe800000 {
 392                 compatible = "rockchip,rk3399-dwc3";
 393                 #address-cells = <2>;
 394                 #size-cells = <2>;
 395                 ranges;
 396                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 397                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 398                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 399                 clock-names = "ref_clk", "suspend_clk",
 400                               "bus_clk", "aclk_usb3_rksoc_axi_perf",
 401                               "aclk_usb3", "grf_clk";
 402                 resets = <&cru SRST_A_USB3_OTG0>;
 403                 reset-names = "usb3-otg";
 404                 status = "disabled";
 405
 406                 usbdrd_dwc3_0: usb@fe800000 {
 407                         compatible = "snps,dwc3";
 408                         reg = <0x0 0xfe800000 0x0 0x100000>;
 409                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 410                         clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
 411                                  <&cru SCLK_USB3OTG0_SUSPEND>;
 412                         clock-names = "ref", "bus_early", "suspend";
 413                         dr_mode = "otg";
 414                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
 415                         phy-names = "usb2-phy", "usb3-phy";
 416                         phy_type = "utmi_wide";
 417                         snps,dis_enblslpm_quirk;
 418                         snps,dis-u2-freeclk-exists-quirk;
 419                         snps,dis_u2_susphy_quirk;
 420                         snps,dis-del-phy-power-chg-quirk;
 421                         snps,dis-tx-ipgap-linecheck-quirk;
 422                         power-domains = <&power RK3399_PD_USB3>;
 423                         status = "disabled";
 424                 };
 425         };
 426
 427         usbdrd3_1: usb@fe900000 {
 428                 compatible = "rockchip,rk3399-dwc3";
 429                 #address-cells = <2>;
 430                 #size-cells = <2>;
 431                 ranges;
 432                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 433                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 434                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 435                 clock-names = "ref_clk", "suspend_clk",
 436                               "bus_clk", "aclk_usb3_rksoc_axi_perf",
 437                               "aclk_usb3", "grf_clk";
 438                 resets = <&cru SRST_A_USB3_OTG1>;
 439                 reset-names = "usb3-otg";
 440                 status = "disabled";
 441
 442                 usbdrd_dwc3_1: usb@fe900000 {
 443                         compatible = "snps,dwc3";
 444                         reg = <0x0 0xfe900000 0x0 0x100000>;
 445                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 446                         clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
 447                                  <&cru SCLK_USB3OTG1_SUSPEND>;
 448                         clock-names = "ref", "bus_early", "suspend";
 449                         dr_mode = "otg";
 450                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
 451                         phy-names = "usb2-phy", "usb3-phy";
 452                         phy_type = "utmi_wide";
 453                         snps,dis_enblslpm_quirk;
 454                         snps,dis-u2-freeclk-exists-quirk;
 455                         snps,dis_u2_susphy_quirk;
 456                         snps,dis-del-phy-power-chg-quirk;
 457                         snps,dis-tx-ipgap-linecheck-quirk;
 458                         power-domains = <&power RK3399_PD_USB3>;
 459                         status = "disabled";
 460                 };
 461         };
 462
 463         cdn_dp: dp@fec00000 {
 464                 compatible = "rockchip,rk3399-cdn-dp";
 465                 reg = <0x0 0xfec00000 0x0 0x100000>;
 466                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 467                 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
 468                 assigned-clock-rates = <100000000>, <200000000>;
 469                 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
 470                          <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
 471                 clock-names = "core-clk", "pclk", "spdif", "grf";
 472                 phys = <&tcphy0_dp>, <&tcphy1_dp>;
 473                 power-domains = <&power RK3399_PD_HDCP>;
 474                 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
 475                          <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
 476                 reset-names = "spdif", "dptx", "apb", "core";
 477                 rockchip,grf = <&grf>;
 478                 #sound-dai-cells = <1>;
 479                 status = "disabled";
 480
 481                 ports {
 482                         dp_in: port {
 483                                 #address-cells = <1>;
 484                                 #size-cells = <0>;
 485
 486                                 dp_in_vopb: endpoint@0 {
 487                                         reg = <0>;
 488                                         remote-endpoint = <&vopb_out_dp>;
 489                                 };
 490
 491                                 dp_in_vopl: endpoint@1 {
 492                                         reg = <1>;
 493                                         remote-endpoint = <&vopl_out_dp>;
 494                                 };
 495                         };
 496                 };
 497         };
 498
 499         gic: interrupt-controller@fee00000 {
 500                 compatible = "arm,gic-v3";
 501                 #interrupt-cells = <4>;
 502                 #address-cells = <2>;
 503                 #size-cells = <2>;
 504                 ranges;
 505                 interrupt-controller;
 506
 507                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 508                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 509                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 510                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 511                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 512                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 513                 its: interrupt-controller@fee20000 {
 514                         compatible = "arm,gic-v3-its";
 515                         msi-controller;
 516                         #msi-cells = <1>;
 517                         reg = <0x0 0xfee20000 0x0 0x20000>;
 518                 };
 519
 520                 ppi-partitions {
 521                         ppi_cluster0: interrupt-partition-0 {
 522                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 523                         };
 524
 525                         ppi_cluster1: interrupt-partition-1 {
 526                                 affinity = <&cpu_b0 &cpu_b1>;
 527                         };
 528                 };
 529         };
 530
 531         saradc: saradc@ff100000 {
 532                 compatible = "rockchip,rk3399-saradc";
 533                 reg = <0x0 0xff100000 0x0 0x100>;
 534                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 535                 #io-channel-cells = <1>;
 536                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 537                 clock-names = "saradc", "apb_pclk";
 538                 resets = <&cru SRST_P_SARADC>;
 539                 reset-names = "saradc-apb";
 540                 status = "disabled";
 541         };
 542
 543         i2c1: i2c@ff110000 {
 544                 compatible = "rockchip,rk3399-i2c";
 545                 reg = <0x0 0xff110000 0x0 0x1000>;
 546                 assigned-clocks = <&cru SCLK_I2C1>;
 547                 assigned-clock-rates = <200000000>;
 548                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 549                 clock-names = "i2c", "pclk";
 550                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 551                 pinctrl-names = "default";
 552                 pinctrl-0 = <&i2c1_xfer>;
 553                 #address-cells = <1>;
 554                 #size-cells = <0>;
 555                 status = "disabled";
 556         };
 557
 558         i2c2: i2c@ff120000 {
 559                 compatible = "rockchip,rk3399-i2c";
 560                 reg = <0x0 0xff120000 0x0 0x1000>;
 561                 assigned-clocks = <&cru SCLK_I2C2>;
 562                 assigned-clock-rates = <200000000>;
 563                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 564                 clock-names = "i2c", "pclk";
 565                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 566                 pinctrl-names = "default";
 567                 pinctrl-0 = <&i2c2_xfer>;
 568                 #address-cells = <1>;
 569                 #size-cells = <0>;
 570                 status = "disabled";
 571         };
 572
 573         i2c3: i2c@ff130000 {
 574                 compatible = "rockchip,rk3399-i2c";
 575                 reg = <0x0 0xff130000 0x0 0x1000>;
 576                 assigned-clocks = <&cru SCLK_I2C3>;
 577                 assigned-clock-rates = <200000000>;
 578                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 579                 clock-names = "i2c", "pclk";
 580                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 581                 pinctrl-names = "default";
 582                 pinctrl-0 = <&i2c3_xfer>;
 583                 #address-cells = <1>;
 584                 #size-cells = <0>;
 585                 status = "disabled";
 586         };
 587
 588         i2c5: i2c@ff140000 {
 589                 compatible = "rockchip,rk3399-i2c";
 590                 reg = <0x0 0xff140000 0x0 0x1000>;
 591                 assigned-clocks = <&cru SCLK_I2C5>;
 592                 assigned-clock-rates = <200000000>;
 593                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 594                 clock-names = "i2c", "pclk";
 595                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 596                 pinctrl-names = "default";
 597                 pinctrl-0 = <&i2c5_xfer>;
 598                 #address-cells = <1>;
 599                 #size-cells = <0>;
 600                 status = "disabled";
 601         };
 602
 603         i2c6: i2c@ff150000 {
 604                 compatible = "rockchip,rk3399-i2c";
 605                 reg = <0x0 0xff150000 0x0 0x1000>;
 606                 assigned-clocks = <&cru SCLK_I2C6>;
 607                 assigned-clock-rates = <200000000>;
 608                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 609                 clock-names = "i2c", "pclk";
 610                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 611                 pinctrl-names = "default";
 612                 pinctrl-0 = <&i2c6_xfer>;
 613                 #address-cells = <1>;
 614                 #size-cells = <0>;
 615                 status = "disabled";
 616         };
 617
 618         i2c7: i2c@ff160000 {
 619                 compatible = "rockchip,rk3399-i2c";
 620                 reg = <0x0 0xff160000 0x0 0x1000>;
 621                 assigned-clocks = <&cru SCLK_I2C7>;
 622                 assigned-clock-rates = <200000000>;
 623                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 624                 clock-names = "i2c", "pclk";
 625                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 626                 pinctrl-names = "default";
 627                 pinctrl-0 = <&i2c7_xfer>;
 628                 #address-cells = <1>;
 629                 #size-cells = <0>;
 630                 status = "disabled";
 631         };
 632
 633         uart0: serial@ff180000 {
 634                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 635                 reg = <0x0 0xff180000 0x0 0x100>;
 636                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 637                 clock-names = "baudclk", "apb_pclk";
 638                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 639                 reg-shift = <2>;
 640                 reg-io-width = <4>;
 641                 pinctrl-names = "default";
 642                 pinctrl-0 = <&uart0_xfer>;
 643                 status = "disabled";
 644         };
 645
 646         uart1: serial@ff190000 {
 647                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 648                 reg = <0x0 0xff190000 0x0 0x100>;
 649                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 650                 clock-names = "baudclk", "apb_pclk";
 651                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 652                 reg-shift = <2>;
 653                 reg-io-width = <4>;
 654                 pinctrl-names = "default";
 655                 pinctrl-0 = <&uart1_xfer>;
 656                 status = "disabled";
 657         };
 658
 659         uart2: serial@ff1a0000 {
 660                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 661                 reg = <0x0 0xff1a0000 0x0 0x100>;
 662                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 663                 clock-names = "baudclk", "apb_pclk";
 664                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 665                 reg-shift = <2>;
 666                 reg-io-width = <4>;
 667                 pinctrl-names = "default";
 668                 pinctrl-0 = <&uart2c_xfer>;
 669                 status = "disabled";
 670         };
 671
 672         uart3: serial@ff1b0000 {
 673                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 674                 reg = <0x0 0xff1b0000 0x0 0x100>;
 675                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 676                 clock-names = "baudclk", "apb_pclk";
 677                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 678                 reg-shift = <2>;
 679                 reg-io-width = <4>;
 680                 pinctrl-names = "default";
 681                 pinctrl-0 = <&uart3_xfer>;
 682                 status = "disabled";
 683         };
 684
 685         spi0: spi@ff1c0000 {
 686                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 687                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 688                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 689                 clock-names = "spiclk", "apb_pclk";
 690                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 691                 dmas = <&dmac_peri 10>, <&dmac_peri 11>;
 692                 dma-names = "tx", "rx";
 693                 pinctrl-names = "default";
 694                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 695                 #address-cells = <1>;
 696                 #size-cells = <0>;
 697                 status = "disabled";
 698         };
 699
 700         spi1: spi@ff1d0000 {
 701                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 702                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 703                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 704                 clock-names = "spiclk", "apb_pclk";
 705                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 706                 dmas = <&dmac_peri 12>, <&dmac_peri 13>;
 707                 dma-names = "tx", "rx";
 708                 pinctrl-names = "default";
 709                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 710                 #address-cells = <1>;
 711                 #size-cells = <0>;
 712                 status = "disabled";
 713         };
 714
 715         spi2: spi@ff1e0000 {
 716                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 717                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 718                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 719                 clock-names = "spiclk", "apb_pclk";
 720                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 721                 dmas = <&dmac_peri 14>, <&dmac_peri 15>;
 722                 dma-names = "tx", "rx";
 723                 pinctrl-names = "default";
 724                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 725                 #address-cells = <1>;
 726                 #size-cells = <0>;
 727                 status = "disabled";
 728         };
 729
 730         spi4: spi@ff1f0000 {
 731                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 732                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 733                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 734                 clock-names = "spiclk", "apb_pclk";
 735                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 736                 dmas = <&dmac_peri 18>, <&dmac_peri 19>;
 737                 dma-names = "tx", "rx";
 738                 pinctrl-names = "default";
 739                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 740                 #address-cells = <1>;
 741                 #size-cells = <0>;
 742                 status = "disabled";
 743         };
 744
 745         spi5: spi@ff200000 {
 746                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 747                 reg = <0x0 0xff200000 0x0 0x1000>;
 748                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 749                 clock-names = "spiclk", "apb_pclk";
 750                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 751                 dmas = <&dmac_bus 8>, <&dmac_bus 9>;
 752                 dma-names = "tx", "rx";
 753                 pinctrl-names = "default";
 754                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 755                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 756                 #address-cells = <1>;
 757                 #size-cells = <0>;
 758                 status = "disabled";
 759         };
 760
 761         thermal_zones: thermal-zones {
 762                 cpu_thermal: cpu {
 763                         polling-delay-passive = <100>;
 764                         polling-delay = <1000>;
 765
 766                         thermal-sensors = <&tsadc 0>;
 767
 768                         trips {
 769                                 cpu_alert0: cpu_alert0 {
 770                                         temperature = <70000>;
 771                                         hysteresis = <2000>;
 772                                         type = "passive";
 773                                 };
 774                                 cpu_alert1: cpu_alert1 {
 775                                         temperature = <75000>;
 776                                         hysteresis = <2000>;
 777                                         type = "passive";
 778                                 };
 779                                 cpu_crit: cpu_crit {
 780                                         temperature = <95000>;
 781                                         hysteresis = <2000>;
 782                                         type = "critical";
 783                                 };
 784                         };
 785
 786                         cooling-maps {
 787                                 map0 {
 788                                         trip = <&cpu_alert0>;
 789                                         cooling-device =
 790                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 791                                                 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 792                                 };
 793                                 map1 {
 794                                         trip = <&cpu_alert1>;
 795                                         cooling-device =
 796                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 797                                                 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 798                                                 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 799                                                 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 800                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 801                                                 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 802                                 };
 803                         };
 804                 };
 805
 806                 gpu_thermal: gpu {
 807                         polling-delay-passive = <100>;
 808                         polling-delay = <1000>;
 809
 810                         thermal-sensors = <&tsadc 1>;
 811
 812                         trips {
 813                                 gpu_alert0: gpu_alert0 {
 814                                         temperature = <75000>;
 815                                         hysteresis = <2000>;
 816                                         type = "passive";
 817                                 };
 818                                 gpu_crit: gpu_crit {
 819                                         temperature = <95000>;
 820                                         hysteresis = <2000>;
 821                                         type = "critical";
 822                                 };
 823                         };
 824
 825                         cooling-maps {
 826                                 map0 {
 827                                         trip = <&gpu_alert0>;
 828                                         cooling-device =
 829                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 830                                 };
 831                         };
 832                 };
 833         };
 834
 835         tsadc: tsadc@ff260000 {
 836                 compatible = "rockchip,rk3399-tsadc";
 837                 reg = <0x0 0xff260000 0x0 0x100>;
 838                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 839                 assigned-clocks = <&cru SCLK_TSADC>;
 840                 assigned-clock-rates = <750000>;
 841                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 842                 clock-names = "tsadc", "apb_pclk";
 843                 resets = <&cru SRST_TSADC>;
 844                 reset-names = "tsadc-apb";
 845                 rockchip,grf = <&grf>;
 846                 rockchip,hw-tshut-temp = <95000>;
 847                 pinctrl-names = "init", "default", "sleep";
 848                 pinctrl-0 = <&otp_gpio>;
 849                 pinctrl-1 = <&otp_out>;
 850                 pinctrl-2 = <&otp_gpio>;
 851                 #thermal-sensor-cells = <1>;
 852                 status = "disabled";
 853         };
 854
 855         qos_emmc: qos@ffa58000 {
 856                 compatible = "syscon";
 857                 reg = <0x0 0xffa58000 0x0 0x20>;
 858         };
 859
 860         qos_gmac: qos@ffa5c000 {
 861                 compatible = "syscon";
 862                 reg = <0x0 0xffa5c000 0x0 0x20>;
 863         };
 864
 865         qos_pcie: qos@ffa60080 {
 866                 compatible = "syscon";
 867                 reg = <0x0 0xffa60080 0x0 0x20>;
 868         };
 869
 870         qos_usb_host0: qos@ffa60100 {
 871                 compatible = "syscon";
 872                 reg = <0x0 0xffa60100 0x0 0x20>;
 873         };
 874
 875         qos_usb_host1: qos@ffa60180 {
 876                 compatible = "syscon";
 877                 reg = <0x0 0xffa60180 0x0 0x20>;
 878         };
 879
 880         qos_usb_otg0: qos@ffa70000 {
 881                 compatible = "syscon";
 882                 reg = <0x0 0xffa70000 0x0 0x20>;
 883         };
 884
 885         qos_usb_otg1: qos@ffa70080 {
 886                 compatible = "syscon";
 887                 reg = <0x0 0xffa70080 0x0 0x20>;
 888         };
 889
 890         qos_sd: qos@ffa74000 {
 891                 compatible = "syscon";
 892                 reg = <0x0 0xffa74000 0x0 0x20>;
 893         };
 894
 895         qos_sdioaudio: qos@ffa76000 {
 896                 compatible = "syscon";
 897                 reg = <0x0 0xffa76000 0x0 0x20>;
 898         };
 899
 900         qos_hdcp: qos@ffa90000 {
 901                 compatible = "syscon";
 902                 reg = <0x0 0xffa90000 0x0 0x20>;
 903         };
 904
 905         qos_iep: qos@ffa98000 {
 906                 compatible = "syscon";
 907                 reg = <0x0 0xffa98000 0x0 0x20>;
 908         };
 909
 910         qos_isp0_m0: qos@ffaa0000 {
 911                 compatible = "syscon";
 912                 reg = <0x0 0xffaa0000 0x0 0x20>;
 913         };
 914
 915         qos_isp0_m1: qos@ffaa0080 {
 916                 compatible = "syscon";
 917                 reg = <0x0 0xffaa0080 0x0 0x20>;
 918         };
 919
 920         qos_isp1_m0: qos@ffaa8000 {
 921                 compatible = "syscon";
 922                 reg = <0x0 0xffaa8000 0x0 0x20>;
 923         };
 924
 925         qos_isp1_m1: qos@ffaa8080 {
 926                 compatible = "syscon";
 927                 reg = <0x0 0xffaa8080 0x0 0x20>;
 928         };
 929
 930         qos_rga_r: qos@ffab0000 {
 931                 compatible = "syscon";
 932                 reg = <0x0 0xffab0000 0x0 0x20>;
 933         };
 934
 935         qos_rga_w: qos@ffab0080 {
 936                 compatible = "syscon";
 937                 reg = <0x0 0xffab0080 0x0 0x20>;
 938         };
 939
 940         qos_video_m0: qos@ffab8000 {
 941                 compatible = "syscon";
 942                 reg = <0x0 0xffab8000 0x0 0x20>;
 943         };
 944
 945         qos_video_m1_r: qos@ffac0000 {
 946                 compatible = "syscon";
 947                 reg = <0x0 0xffac0000 0x0 0x20>;
 948         };
 949
 950         qos_video_m1_w: qos@ffac0080 {
 951                 compatible = "syscon";
 952                 reg = <0x0 0xffac0080 0x0 0x20>;
 953         };
 954
 955         qos_vop_big_r: qos@ffac8000 {
 956                 compatible = "syscon";
 957                 reg = <0x0 0xffac8000 0x0 0x20>;
 958         };
 959
 960         qos_vop_big_w: qos@ffac8080 {
 961                 compatible = "syscon";
 962                 reg = <0x0 0xffac8080 0x0 0x20>;
 963         };
 964
 965         qos_vop_little: qos@ffad0000 {
 966                 compatible = "syscon";
 967                 reg = <0x0 0xffad0000 0x0 0x20>;
 968         };
 969
 970         qos_perihp: qos@ffad8080 {
 971                 compatible = "syscon";
 972                 reg = <0x0 0xffad8080 0x0 0x20>;
 973         };
 974
 975         qos_gpu: qos@ffae0000 {
 976                 compatible = "syscon";
 977                 reg = <0x0 0xffae0000 0x0 0x20>;
 978         };
 979
 980         pmu: power-management@ff310000 {
 981                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 982                 reg = <0x0 0xff310000 0x0 0x1000>;
 983
 984                 /*
 985                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 986                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 987                  * Some of the power domains are grouped together for every
 988                  * voltage domain.
 989                  * The detail contents as below.
 990                  */
 991                 power: power-controller {
 992                         compatible = "rockchip,rk3399-power-controller";
 993                         #power-domain-cells = <1>;
 994                         #address-cells = <1>;
 995                         #size-cells = <0>;
 996
 997                         /* These power domains are grouped by VD_CENTER */
 998                         pd_iep@RK3399_PD_IEP {
 999                                 reg = <RK3399_PD_IEP>;
1000                                 clocks = <&cru ACLK_IEP>,
1001                                          <&cru HCLK_IEP>;
1002                                 pm_qos = <&qos_iep>;
1003                         };
1004                         pd_rga@RK3399_PD_RGA {
1005                                 reg = <RK3399_PD_RGA>;
1006                                 clocks = <&cru ACLK_RGA>,
1007                                          <&cru HCLK_RGA>;
1008                                 pm_qos = <&qos_rga_r>,
1009                                          <&qos_rga_w>;
1010                         };
1011                         pd_vcodec@RK3399_PD_VCODEC {
1012                                 reg = <RK3399_PD_VCODEC>;
1013                                 clocks = <&cru ACLK_VCODEC>,
1014                                          <&cru HCLK_VCODEC>;
1015                                 pm_qos = <&qos_video_m0>;
1016                         };
1017                         pd_vdu@RK3399_PD_VDU {
1018                                 reg = <RK3399_PD_VDU>;
1019                                 clocks = <&cru ACLK_VDU>,
1020                                          <&cru HCLK_VDU>;
1021                                 pm_qos = <&qos_video_m1_r>,
1022                                          <&qos_video_m1_w>;
1023                         };
1024
1025                         /* These power domains are grouped by VD_GPU */
1026                         pd_gpu@RK3399_PD_GPU {
1027                                 reg = <RK3399_PD_GPU>;
1028                                 clocks = <&cru ACLK_GPU>;
1029                                 pm_qos = <&qos_gpu>;
1030                         };
1031
1032                         /* These power domains are grouped by VD_LOGIC */
1033                         pd_edp@RK3399_PD_EDP {
1034                                 reg = <RK3399_PD_EDP>;
1035                                 clocks = <&cru PCLK_EDP_CTRL>;
1036                         };
1037                         pd_emmc@RK3399_PD_EMMC {
1038                                 reg = <RK3399_PD_EMMC>;
1039                                 clocks = <&cru ACLK_EMMC>;
1040                                 pm_qos = <&qos_emmc>;
1041                         };
1042                         pd_gmac@RK3399_PD_GMAC {
1043                                 reg = <RK3399_PD_GMAC>;
1044                                 clocks = <&cru ACLK_GMAC>,
1045                                          <&cru PCLK_GMAC>;
1046                                 pm_qos = <&qos_gmac>;
1047                         };
1048                         pd_sd@RK3399_PD_SD {
1049                                 reg = <RK3399_PD_SD>;
1050                                 clocks = <&cru HCLK_SDMMC>,
1051                                          <&cru SCLK_SDMMC>;
1052                                 pm_qos = <&qos_sd>;
1053                         };
1054                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1055                                 reg = <RK3399_PD_SDIOAUDIO>;
1056                                 clocks = <&cru HCLK_SDIO>;
1057                                 pm_qos = <&qos_sdioaudio>;
1058                         };
1059                         pd_tcpc0@RK3399_PD_TCPD0 {
1060                                 reg = <RK3399_PD_TCPD0>;
1061                                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1062                                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1063                         };
1064                         pd_tcpc1@RK3399_PD_TCPD1 {
1065                                 reg = <RK3399_PD_TCPD1>;
1066                                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1067                                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1068                         };
1069                         pd_usb3@RK3399_PD_USB3 {
1070                                 reg = <RK3399_PD_USB3>;
1071                                 clocks = <&cru ACLK_USB3>;
1072                                 pm_qos = <&qos_usb_otg0>,
1073                                          <&qos_usb_otg1>;
1074                         };
1075                         pd_vio@RK3399_PD_VIO {
1076                                 reg = <RK3399_PD_VIO>;
1077                                 #address-cells = <1>;
1078                                 #size-cells = <0>;
1079
1080                                 pd_hdcp@RK3399_PD_HDCP {
1081                                         reg = <RK3399_PD_HDCP>;
1082                                         clocks = <&cru ACLK_HDCP>,
1083                                                  <&cru HCLK_HDCP>,
1084                                                  <&cru PCLK_HDCP>;
1085                                         pm_qos = <&qos_hdcp>;
1086                                 };
1087                                 pd_isp0@RK3399_PD_ISP0 {
1088                                         reg = <RK3399_PD_ISP0>;
1089                                         clocks = <&cru ACLK_ISP0>,
1090                                                  <&cru HCLK_ISP0>;
1091                                         pm_qos = <&qos_isp0_m0>,
1092                                                  <&qos_isp0_m1>;
1093                                 };
1094                                 pd_isp1@RK3399_PD_ISP1 {
1095                                         reg = <RK3399_PD_ISP1>;
1096                                         clocks = <&cru ACLK_ISP1>,
1097                                                  <&cru HCLK_ISP1>;
1098                                         pm_qos = <&qos_isp1_m0>,
1099                                                  <&qos_isp1_m1>;
1100                                 };
1101                                 pd_vo@RK3399_PD_VO {
1102                                         reg = <RK3399_PD_VO>;
1103                                         #address-cells = <1>;
1104                                         #size-cells = <0>;
1105
1106                                         pd_vopb@RK3399_PD_VOPB {
1107                                                 reg = <RK3399_PD_VOPB>;
1108                                                 clocks = <&cru ACLK_VOP0>,
1109                                                          <&cru HCLK_VOP0>;
1110                                                 pm_qos = <&qos_vop_big_r>,
1111                                                          <&qos_vop_big_w>;
1112                                         };
1113                                         pd_vopl@RK3399_PD_VOPL {
1114                                                 reg = <RK3399_PD_VOPL>;
1115                                                 clocks = <&cru ACLK_VOP1>,
1116                                                          <&cru HCLK_VOP1>;
1117                                                 pm_qos = <&qos_vop_little>;
1118                                         };
1119                                 };
1120                         };
1121                 };
1122         };
1123
1124         pmugrf: syscon@ff320000 {
1125                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1126                 reg = <0x0 0xff320000 0x0 0x1000>;
1127
1128                 pmu_io_domains: io-domains {
1129                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1130                         status = "disabled";
1131                 };
1132         };
1133
1134         spi3: spi@ff350000 {
1135                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1136                 reg = <0x0 0xff350000 0x0 0x1000>;
1137                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1138                 clock-names = "spiclk", "apb_pclk";
1139                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1140                 pinctrl-names = "default";
1141                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1142                 #address-cells = <1>;
1143                 #size-cells = <0>;
1144                 status = "disabled";
1145         };
1146
1147         uart4: serial@ff370000 {
1148                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1149                 reg = <0x0 0xff370000 0x0 0x100>;
1150                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1151                 clock-names = "baudclk", "apb_pclk";
1152                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1153                 reg-shift = <2>;
1154                 reg-io-width = <4>;
1155                 pinctrl-names = "default";
1156                 pinctrl-0 = <&uart4_xfer>;
1157                 status = "disabled";
1158         };
1159
1160         i2c0: i2c@ff3c0000 {
1161                 compatible = "rockchip,rk3399-i2c";
1162                 reg = <0x0 0xff3c0000 0x0 0x1000>;
1163                 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1164                 assigned-clock-rates = <200000000>;
1165                 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1166                 clock-names = "i2c", "pclk";
1167                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1168                 pinctrl-names = "default";
1169                 pinctrl-0 = <&i2c0_xfer>;
1170                 #address-cells = <1>;
1171                 #size-cells = <0>;
1172                 status = "disabled";
1173         };
1174
1175         i2c4: i2c@ff3d0000 {
1176                 compatible = "rockchip,rk3399-i2c";
1177                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1178                 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1179                 assigned-clock-rates = <200000000>;
1180                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1181                 clock-names = "i2c", "pclk";
1182                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1183                 pinctrl-names = "default";
1184                 pinctrl-0 = <&i2c4_xfer>;
1185                 #address-cells = <1>;
1186                 #size-cells = <0>;
1187                 status = "disabled";
1188         };
1189
1190         i2c8: i2c@ff3e0000 {
1191                 compatible = "rockchip,rk3399-i2c";
1192                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1193                 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1194                 assigned-clock-rates = <200000000>;
1195                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1196                 clock-names = "i2c", "pclk";
1197                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1198                 pinctrl-names = "default";
1199                 pinctrl-0 = <&i2c8_xfer>;
1200                 #address-cells = <1>;
1201                 #size-cells = <0>;
1202                 status = "disabled";
1203         };
1204
1205         pwm0: pwm@ff420000 {
1206                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1207                 reg = <0x0 0xff420000 0x0 0x10>;
1208                 #pwm-cells = <3>;
1209                 pinctrl-names = "default";
1210                 pinctrl-0 = <&pwm0_pin>;
1211                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1212                 clock-names = "pwm";
1213                 status = "disabled";
1214         };
1215
1216         pwm1: pwm@ff420010 {
1217                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1218                 reg = <0x0 0xff420010 0x0 0x10>;
1219                 #pwm-cells = <3>;
1220                 pinctrl-names = "default";
1221                 pinctrl-0 = <&pwm1_pin>;
1222                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1223                 clock-names = "pwm";
1224                 status = "disabled";
1225         };
1226
1227         pwm2: pwm@ff420020 {
1228                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1229                 reg = <0x0 0xff420020 0x0 0x10>;
1230                 #pwm-cells = <3>;
1231                 pinctrl-names = "default";
1232                 pinctrl-0 = <&pwm2_pin>;
1233                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1234                 clock-names = "pwm";
1235                 status = "disabled";
1236         };
1237
1238         pwm3: pwm@ff420030 {
1239                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1240                 reg = <0x0 0xff420030 0x0 0x10>;
1241                 #pwm-cells = <3>;
1242                 pinctrl-names = "default";
1243                 pinctrl-0 = <&pwm3a_pin>;
1244                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1245                 clock-names = "pwm";
1246                 status = "disabled";
1247         };
1248
1249         vpu: video-codec@ff650000 {
1250                 compatible = "rockchip,rk3399-vpu";
1251                 reg = <0x0 0xff650000 0x0 0x800>;
1252                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
1253                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1254                 interrupt-names = "vepu", "vdpu";
1255                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1256                 clock-names = "aclk", "hclk";
1257                 iommus = <&vpu_mmu>;
1258                 power-domains = <&power RK3399_PD_VCODEC>;
1259         };
1260
1261         vpu_mmu: iommu@ff650800 {
1262                 compatible = "rockchip,iommu";
1263                 reg = <0x0 0xff650800 0x0 0x40>;
1264                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1265                 interrupt-names = "vpu_mmu";
1266                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1267                 clock-names = "aclk", "iface";
1268                 #iommu-cells = <0>;
1269                 power-domains = <&power RK3399_PD_VCODEC>;
1270         };
1271
1272         vdec: video-codec@ff660000 {
1273                 compatible = "rockchip,rk3399-vdec";
1274                 reg = <0x0 0xff660000 0x0 0x400>;
1275                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1276                 interrupt-names = "vdpu";
1277                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1278                          <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1279                 clock-names = "axi", "ahb", "cabac", "core";
1280                 iommus = <&vdec_mmu>;
1281                 power-domains = <&power RK3399_PD_VDU>;
1282         };
1283
1284         vdec_mmu: iommu@ff660480 {
1285                 compatible = "rockchip,iommu";
1286                 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1287                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1288                 interrupt-names = "vdec_mmu";
1289                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1290                 clock-names = "aclk", "iface";
1291                 power-domains = <&power RK3399_PD_VDU>;
1292                 #iommu-cells = <0>;
1293         };
1294
1295         iep_mmu: iommu@ff670800 {
1296                 compatible = "rockchip,iommu";
1297                 reg = <0x0 0xff670800 0x0 0x40>;
1298                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1299                 interrupt-names = "iep_mmu";
1300                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1301                 clock-names = "aclk", "iface";
1302                 #iommu-cells = <0>;
1303                 status = "disabled";
1304         };
1305
1306         rga: rga@ff680000 {
1307                 compatible = "rockchip,rk3399-rga";
1308                 reg = <0x0 0xff680000 0x0 0x10000>;
1309                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1310                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1311                 clock-names = "aclk", "hclk", "sclk";
1312                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1313                 reset-names = "core", "axi", "ahb";
1314                 power-domains = <&power RK3399_PD_RGA>;
1315         };
1316
1317         efuse0: efuse@ff690000 {
1318                 compatible = "rockchip,rk3399-efuse";
1319                 reg = <0x0 0xff690000 0x0 0x80>;
1320                 #address-cells = <1>;
1321                 #size-cells = <1>;
1322                 clocks = <&cru PCLK_EFUSE1024NS>;
1323                 clock-names = "pclk_efuse";
1324
1325                 /* Data cells */
1326                 cpu_id: cpu-id@7 {
1327                         reg = <0x07 0x10>;
1328                 };
1329                 cpub_leakage: cpu-leakage@17 {
1330                         reg = <0x17 0x1>;
1331                 };
1332                 gpu_leakage: gpu-leakage@18 {
1333                         reg = <0x18 0x1>;
1334                 };
1335                 center_leakage: center-leakage@19 {
1336                         reg = <0x19 0x1>;
1337                 };
1338                 cpul_leakage: cpu-leakage@1a {
1339                         reg = <0x1a 0x1>;
1340                 };
1341                 logic_leakage: logic-leakage@1b {
1342                         reg = <0x1b 0x1>;
1343                 };
1344                 wafer_info: wafer-info@1c {
1345                         reg = <0x1c 0x1>;
1346                 };
1347         };
1348
1349         pmucru: pmu-clock-controller@ff750000 {
1350                 compatible = "rockchip,rk3399-pmucru";
1351                 reg = <0x0 0xff750000 0x0 0x1000>;
1352                 rockchip,grf = <&pmugrf>;
1353                 #clock-cells = <1>;
1354                 #reset-cells = <1>;
1355                 assigned-clocks = <&pmucru PLL_PPLL>;
1356                 assigned-clock-rates = <676000000>;
1357         };
1358
1359         cru: clock-controller@ff760000 {
1360                 compatible = "rockchip,rk3399-cru";
1361                 reg = <0x0 0xff760000 0x0 0x1000>;
1362                 rockchip,grf = <&grf>;
1363                 #clock-cells = <1>;
1364                 #reset-cells = <1>;
1365                 assigned-clocks =
1366                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1367                         <&cru PLL_NPLL>,
1368                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1369                         <&cru PCLK_PERIHP>,
1370                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1371                         <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1372                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1373                         <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1374                         <&cru ACLK_GIC_PRE>,
1375                         <&cru PCLK_DDR>;
1376                 assigned-clock-rates =
1377                          <594000000>,  <800000000>,
1378                         <1000000000>,
1379                          <150000000>,   <75000000>,
1380                           <37500000>,
1381                          <100000000>,  <100000000>,
1382                           <50000000>, <600000000>,
1383                          <100000000>,   <50000000>,
1384                          <400000000>, <400000000>,
1385                          <200000000>,
1386                          <200000000>;
1387         };
1388
1389         grf: syscon@ff770000 {
1390                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1391                 reg = <0x0 0xff770000 0x0 0x10000>;
1392                 #address-cells = <1>;
1393                 #size-cells = <1>;
1394
1395                 io_domains: io-domains {
1396                         compatible = "rockchip,rk3399-io-voltage-domain";
1397                         status = "disabled";
1398                 };
1399
1400                 u2phy0: usb2-phy@e450 {
1401                         compatible = "rockchip,rk3399-usb2phy";
1402                         reg = <0xe450 0x10>;
1403                         clocks = <&cru SCLK_USB2PHY0_REF>;
1404                         clock-names = "phyclk";
1405                         #clock-cells = <0>;
1406                         clock-output-names = "clk_usbphy0_480m";
1407                         status = "disabled";
1408
1409                         u2phy0_host: host-port {
1410                                 #phy-cells = <0>;
1411                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1412                                 interrupt-names = "linestate";
1413                                 status = "disabled";
1414                         };
1415
1416                         u2phy0_otg: otg-port {
1417                                 #phy-cells = <0>;
1418                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1419                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1420                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1421                                 interrupt-names = "otg-bvalid", "otg-id",
1422                                                   "linestate";
1423                                 status = "disabled";
1424                         };
1425                 };
1426
1427                 u2phy1: usb2-phy@e460 {
1428                         compatible = "rockchip,rk3399-usb2phy";
1429                         reg = <0xe460 0x10>;
1430                         clocks = <&cru SCLK_USB2PHY1_REF>;
1431                         clock-names = "phyclk";
1432                         #clock-cells = <0>;
1433                         clock-output-names = "clk_usbphy1_480m";
1434                         status = "disabled";
1435
1436                         u2phy1_host: host-port {
1437                                 #phy-cells = <0>;
1438                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1439                                 interrupt-names = "linestate";
1440                                 status = "disabled";
1441                         };
1442
1443                         u2phy1_otg: otg-port {
1444                                 #phy-cells = <0>;
1445                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1446                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1447                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1448                                 interrupt-names = "otg-bvalid", "otg-id",
1449                                                   "linestate";
1450                                 status = "disabled";
1451                         };
1452                 };
1453
1454                 emmc_phy: phy@f780 {
1455                         compatible = "rockchip,rk3399-emmc-phy";
1456                         reg = <0xf780 0x24>;
1457                         clocks = <&sdhci>;
1458                         clock-names = "emmcclk";
1459                         #phy-cells = <0>;
1460                         status = "disabled";
1461                 };
1462
1463                 pcie_phy: pcie-phy {
1464                         compatible = "rockchip,rk3399-pcie-phy";
1465                         clocks = <&cru SCLK_PCIEPHY_REF>;
1466                         clock-names = "refclk";
1467                         #phy-cells = <1>;
1468                         resets = <&cru SRST_PCIEPHY>;
1469                         drive-impedance-ohm = <50>;
1470                         reset-names = "phy";
1471                         status = "disabled";
1472                 };
1473         };
1474
1475         tcphy0: phy@ff7c0000 {
1476                 compatible = "rockchip,rk3399-typec-phy";
1477                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1478                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1479                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1480                 clock-names = "tcpdcore", "tcpdphy-ref";
1481                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1482                 assigned-clock-rates = <50000000>;
1483                 power-domains = <&power RK3399_PD_TCPD0>;
1484                 resets = <&cru SRST_UPHY0>,
1485                          <&cru SRST_UPHY0_PIPE_L00>,
1486                          <&cru SRST_P_UPHY0_TCPHY>;
1487                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1488                 rockchip,grf = <&grf>;
1489                 status = "disabled";
1490
1491                 tcphy0_dp: dp-port {
1492                         #phy-cells = <0>;
1493                 };
1494
1495                 tcphy0_usb3: usb3-port {
1496                         #phy-cells = <0>;
1497                 };
1498         };
1499
1500         tcphy1: phy@ff800000 {
1501                 compatible = "rockchip,rk3399-typec-phy";
1502                 reg = <0x0 0xff800000 0x0 0x40000>;
1503                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1504                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1505                 clock-names = "tcpdcore", "tcpdphy-ref";
1506                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1507                 assigned-clock-rates = <50000000>;
1508                 power-domains = <&power RK3399_PD_TCPD1>;
1509                 resets = <&cru SRST_UPHY1>,
1510                          <&cru SRST_UPHY1_PIPE_L00>,
1511                          <&cru SRST_P_UPHY1_TCPHY>;
1512                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1513                 rockchip,grf = <&grf>;
1514                 status = "disabled";
1515
1516                 tcphy1_dp: dp-port {
1517                         #phy-cells = <0>;
1518                 };
1519
1520                 tcphy1_usb3: usb3-port {
1521                         #phy-cells = <0>;
1522                 };
1523         };
1524
1525         watchdog@ff848000 {
1526                 compatible = "snps,dw-wdt";
1527                 reg = <0x0 0xff848000 0x0 0x100>;
1528                 clocks = <&cru PCLK_WDT>;
1529                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1530         };
1531
1532         rktimer: rktimer@ff850000 {
1533                 compatible = "rockchip,rk3399-timer";
1534                 reg = <0x0 0xff850000 0x0 0x1000>;
1535                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1536                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1537                 clock-names = "pclk", "timer";
1538         };
1539
1540         spdif: spdif@ff870000 {
1541                 compatible = "rockchip,rk3399-spdif";
1542                 reg = <0x0 0xff870000 0x0 0x1000>;
1543                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1544                 dmas = <&dmac_bus 7>;
1545                 dma-names = "tx";
1546                 clock-names = "mclk", "hclk";
1547                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1548                 pinctrl-names = "default";
1549                 pinctrl-0 = <&spdif_bus>;
1550                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1551                 #sound-dai-cells = <0>;
1552                 status = "disabled";
1553         };
1554
1555         i2s0: i2s@ff880000 {
1556                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1557                 reg = <0x0 0xff880000 0x0 0x1000>;
1558                 rockchip,grf = <&grf>;
1559                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1560                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1561                 dma-names = "tx", "rx";
1562                 clock-names = "i2s_clk", "i2s_hclk";
1563                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1564                 pinctrl-names = "default";
1565                 pinctrl-0 = <&i2s0_8ch_bus>;
1566                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1567                 #sound-dai-cells = <0>;
1568                 status = "disabled";
1569         };
1570
1571         i2s1: i2s@ff890000 {
1572                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1573                 reg = <0x0 0xff890000 0x0 0x1000>;
1574                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1575                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1576                 dma-names = "tx", "rx";
1577                 clock-names = "i2s_clk", "i2s_hclk";
1578                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1579                 pinctrl-names = "default";
1580                 pinctrl-0 = <&i2s1_2ch_bus>;
1581                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1582                 #sound-dai-cells = <0>;
1583                 status = "disabled";
1584         };
1585
1586         i2s2: i2s@ff8a0000 {
1587                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1588                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1589                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1590                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1591                 dma-names = "tx", "rx";
1592                 clock-names = "i2s_clk", "i2s_hclk";
1593                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1594                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1595                 #sound-dai-cells = <0>;
1596                 status = "disabled";
1597         };
1598
1599         vopl: vop@ff8f0000 {
1600                 compatible = "rockchip,rk3399-vop-lit";
1601                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1602                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1603                 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1604                 assigned-clock-rates = <400000000>, <100000000>;
1605                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1606                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1607                 iommus = <&vopl_mmu>;
1608                 power-domains = <&power RK3399_PD_VOPL>;
1609                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1610                 reset-names = "axi", "ahb", "dclk";
1611                 status = "disabled";
1612
1613                 vopl_out: port {
1614                         #address-cells = <1>;
1615                         #size-cells = <0>;
1616
1617                         vopl_out_mipi: endpoint@0 {
1618                                 reg = <0>;
1619                                 remote-endpoint = <&mipi_in_vopl>;
1620                         };
1621
1622                         vopl_out_edp: endpoint@1 {
1623                                 reg = <1>;
1624                                 remote-endpoint = <&edp_in_vopl>;
1625                         };
1626
1627                         vopl_out_hdmi: endpoint@2 {
1628                                 reg = <2>;
1629                                 remote-endpoint = <&hdmi_in_vopl>;
1630                         };
1631
1632                         vopl_out_mipi1: endpoint@3 {
1633                                 reg = <3>;
1634                                 remote-endpoint = <&mipi1_in_vopl>;
1635                         };
1636
1637                         vopl_out_dp: endpoint@4 {
1638                                 reg = <4>;
1639                                 remote-endpoint = <&dp_in_vopl>;
1640                         };
1641                 };
1642         };
1643
1644         vopl_mmu: iommu@ff8f3f00 {
1645                 compatible = "rockchip,iommu";
1646                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1647                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1648                 interrupt-names = "vopl_mmu";
1649                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1650                 clock-names = "aclk", "iface";
1651                 power-domains = <&power RK3399_PD_VOPL>;
1652                 #iommu-cells = <0>;
1653                 status = "disabled";
1654         };
1655
1656         vopb: vop@ff900000 {
1657                 compatible = "rockchip,rk3399-vop-big";
1658                 reg = <0x0 0xff900000 0x0 0x3efc>;
1659                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1660                 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1661                 assigned-clock-rates = <400000000>, <100000000>;
1662                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1663                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1664                 iommus = <&vopb_mmu>;
1665                 power-domains = <&power RK3399_PD_VOPB>;
1666                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1667                 reset-names = "axi", "ahb", "dclk";
1668                 status = "disabled";
1669
1670                 vopb_out: port {
1671                         #address-cells = <1>;
1672                         #size-cells = <0>;
1673
1674                         vopb_out_edp: endpoint@0 {
1675                                 reg = <0>;
1676                                 remote-endpoint = <&edp_in_vopb>;
1677                         };
1678
1679                         vopb_out_mipi: endpoint@1 {
1680                                 reg = <1>;
1681                                 remote-endpoint = <&mipi_in_vopb>;
1682                         };
1683
1684                         vopb_out_hdmi: endpoint@2 {
1685                                 reg = <2>;
1686                                 remote-endpoint = <&hdmi_in_vopb>;
1687                         };
1688
1689                         vopb_out_mipi1: endpoint@3 {
1690                                 reg = <3>;
1691                                 remote-endpoint = <&mipi1_in_vopb>;
1692                         };
1693
1694                         vopb_out_dp: endpoint@4 {
1695                                 reg = <4>;
1696                                 remote-endpoint = <&dp_in_vopb>;
1697                         };
1698                 };
1699         };
1700
1701         vopb_mmu: iommu@ff903f00 {
1702                 compatible = "rockchip,iommu";
1703                 reg = <0x0 0xff903f00 0x0 0x100>;
1704                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1705                 interrupt-names = "vopb_mmu";
1706                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1707                 clock-names = "aclk", "iface";
1708                 power-domains = <&power RK3399_PD_VOPB>;
1709                 #iommu-cells = <0>;
1710                 status = "disabled";
1711         };
1712
1713         isp0_mmu: iommu@ff914000 {
1714                 compatible = "rockchip,iommu";
1715                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1716                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1717                 interrupt-names = "isp0_mmu";
1718                 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
1719                 clock-names = "aclk", "iface";
1720                 #iommu-cells = <0>;
1721                 power-domains = <&power RK3399_PD_ISP0>;
1722                 rockchip,disable-mmu-reset;
1723         };
1724
1725         isp1_mmu: iommu@ff924000 {
1726                 compatible = "rockchip,iommu";
1727                 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1728                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1729                 interrupt-names = "isp1_mmu";
1730                 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
1731                 clock-names = "aclk", "iface";
1732                 #iommu-cells = <0>;
1733                 power-domains = <&power RK3399_PD_ISP1>;
1734                 rockchip,disable-mmu-reset;
1735         };
1736
1737         hdmi_sound: hdmi-sound {
1738                 compatible = "simple-audio-card";
1739                 simple-audio-card,format = "i2s";
1740                 simple-audio-card,mclk-fs = <256>;
1741                 simple-audio-card,name = "hdmi-sound";
1742                 status = "disabled";
1743
1744                 simple-audio-card,cpu {
1745                         sound-dai = <&i2s2>;
1746                 };
1747                 simple-audio-card,codec {
1748                         sound-dai = <&hdmi>;
1749                 };
1750         };
1751
1752         hdmi: hdmi@ff940000 {
1753                 compatible = "rockchip,rk3399-dw-hdmi";
1754                 reg = <0x0 0xff940000 0x0 0x20000>;
1755                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1756                 clocks = <&cru PCLK_HDMI_CTRL>,
1757                          <&cru SCLK_HDMI_SFR>,
1758                          <&cru PLL_VPLL>,
1759                          <&cru PCLK_VIO_GRF>,
1760                          <&cru SCLK_HDMI_CEC>;
1761                 clock-names = "iahb", "isfr", "vpll", "grf", "cec";
1762                 power-domains = <&power RK3399_PD_HDCP>;
1763                 reg-io-width = <4>;
1764                 rockchip,grf = <&grf>;
1765                 #sound-dai-cells = <0>;
1766                 status = "disabled";
1767
1768                 ports {
1769                         hdmi_in: port {
1770                                 #address-cells = <1>;
1771                                 #size-cells = <0>;
1772
1773                                 hdmi_in_vopb: endpoint@0 {
1774                                         reg = <0>;
1775                                         remote-endpoint = <&vopb_out_hdmi>;
1776                                 };
1777                                 hdmi_in_vopl: endpoint@1 {
1778                                         reg = <1>;
1779                                         remote-endpoint = <&vopl_out_hdmi>;
1780                                 };
1781                         };
1782                 };
1783         };
1784
1785         mipi_dsi: mipi@ff960000 {
1786                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1787                 reg = <0x0 0xff960000 0x0 0x8000>;
1788                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1789                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1790                          <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1791                 clock-names = "ref", "pclk", "phy_cfg", "grf";
1792                 power-domains = <&power RK3399_PD_VIO>;
1793                 resets = <&cru SRST_P_MIPI_DSI0>;
1794                 reset-names = "apb";
1795                 rockchip,grf = <&grf>;
1796                 #address-cells = <1>;
1797                 #size-cells = <0>;
1798                 status = "disabled";
1799
1800                 ports {
1801                         #address-cells = <1>;
1802                         #size-cells = <0>;
1803
1804                         mipi_in: port@0 {
1805                                 reg = <0>;
1806                                 #address-cells = <1>;
1807                                 #size-cells = <0>;
1808
1809                                 mipi_in_vopb: endpoint@0 {
1810                                         reg = <0>;
1811                                         remote-endpoint = <&vopb_out_mipi>;
1812                                 };
1813                                 mipi_in_vopl: endpoint@1 {
1814                                         reg = <1>;
1815                                         remote-endpoint = <&vopl_out_mipi>;
1816                                 };
1817                         };
1818                 };
1819         };
1820
1821         mipi_dsi1: mipi@ff968000 {
1822                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1823                 reg = <0x0 0xff968000 0x0 0x8000>;
1824                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1825                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1826                          <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1827                 clock-names = "ref", "pclk", "phy_cfg", "grf";
1828                 power-domains = <&power RK3399_PD_VIO>;
1829                 resets = <&cru SRST_P_MIPI_DSI1>;
1830                 reset-names = "apb";
1831                 rockchip,grf = <&grf>;
1832                 #address-cells = <1>;
1833                 #size-cells = <0>;
1834                 status = "disabled";
1835
1836                 ports {
1837                         #address-cells = <1>;
1838                         #size-cells = <0>;
1839
1840                         mipi1_in: port@0 {
1841                                 reg = <0>;
1842                                 #address-cells = <1>;
1843                                 #size-cells = <0>;
1844
1845                                 mipi1_in_vopb: endpoint@0 {
1846                                         reg = <0>;
1847                                         remote-endpoint = <&vopb_out_mipi1>;
1848                                 };
1849
1850                                 mipi1_in_vopl: endpoint@1 {
1851                                         reg = <1>;
1852                                         remote-endpoint = <&vopl_out_mipi1>;
1853                                 };
1854                         };
1855                 };
1856         };
1857
1858         edp: edp@ff970000 {
1859                 compatible = "rockchip,rk3399-edp";
1860                 reg = <0x0 0xff970000 0x0 0x8000>;
1861                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1862                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
1863                 clock-names = "dp", "pclk", "grf";
1864                 pinctrl-names = "default";
1865                 pinctrl-0 = <&edp_hpd>;
1866                 power-domains = <&power RK3399_PD_EDP>;
1867                 resets = <&cru SRST_P_EDP_CTRL>;
1868                 reset-names = "dp";
1869                 rockchip,grf = <&grf>;
1870                 status = "disabled";
1871
1872                 ports {
1873                         #address-cells = <1>;
1874                         #size-cells = <0>;
1875                         edp_in: port@0 {
1876                                 reg = <0>;
1877                                 #address-cells = <1>;
1878                                 #size-cells = <0>;
1879
1880                                 edp_in_vopb: endpoint@0 {
1881                                         reg = <0>;
1882                                         remote-endpoint = <&vopb_out_edp>;
1883                                 };
1884
1885                                 edp_in_vopl: endpoint@1 {
1886                                         reg = <1>;
1887                                         remote-endpoint = <&vopl_out_edp>;
1888                                 };
1889                         };
1890                 };
1891         };
1892
1893         gpu: gpu@ff9a0000 {
1894                 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1895                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1896                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1897                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
1898                              <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
1899                 interrupt-names = "job", "mmu", "gpu";
1900                 clocks = <&cru ACLK_GPU>;
1901                 #cooling-cells = <2>;
1902                 power-domains = <&power RK3399_PD_GPU>;
1903                 status = "disabled";
1904         };
1905
1906         pinctrl: pinctrl {
1907                 compatible = "rockchip,rk3399-pinctrl";
1908                 rockchip,grf = <&grf>;
1909                 rockchip,pmu = <&pmugrf>;
1910                 #address-cells = <2>;
1911                 #size-cells = <2>;
1912                 ranges;
1913
1914                 gpio0: gpio0@ff720000 {
1915                         compatible = "rockchip,gpio-bank";
1916                         reg = <0x0 0xff720000 0x0 0x100>;
1917                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1918                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1919
1920                         gpio-controller;
1921                         #gpio-cells = <0x2>;
1922
1923                         interrupt-controller;
1924                         #interrupt-cells = <0x2>;
1925                 };
1926
1927                 gpio1: gpio1@ff730000 {
1928                         compatible = "rockchip,gpio-bank";
1929                         reg = <0x0 0xff730000 0x0 0x100>;
1930                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1931                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1932
1933                         gpio-controller;
1934                         #gpio-cells = <0x2>;
1935
1936                         interrupt-controller;
1937                         #interrupt-cells = <0x2>;
1938                 };
1939
1940                 gpio2: gpio2@ff780000 {
1941                         compatible = "rockchip,gpio-bank";
1942                         reg = <0x0 0xff780000 0x0 0x100>;
1943                         clocks = <&cru PCLK_GPIO2>;
1944                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1945
1946                         gpio-controller;
1947                         #gpio-cells = <0x2>;
1948
1949                         interrupt-controller;
1950                         #interrupt-cells = <0x2>;
1951                 };
1952
1953                 gpio3: gpio3@ff788000 {
1954                         compatible = "rockchip,gpio-bank";
1955                         reg = <0x0 0xff788000 0x0 0x100>;
1956                         clocks = <&cru PCLK_GPIO3>;
1957                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1958
1959                         gpio-controller;
1960                         #gpio-cells = <0x2>;
1961
1962                         interrupt-controller;
1963                         #interrupt-cells = <0x2>;
1964                 };
1965
1966                 gpio4: gpio4@ff790000 {
1967                         compatible = "rockchip,gpio-bank";
1968                         reg = <0x0 0xff790000 0x0 0x100>;
1969                         clocks = <&cru PCLK_GPIO4>;
1970                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1971
1972                         gpio-controller;
1973                         #gpio-cells = <0x2>;
1974
1975                         interrupt-controller;
1976                         #interrupt-cells = <0x2>;
1977                 };
1978
1979                 pcfg_pull_up: pcfg-pull-up {
1980                         bias-pull-up;
1981                 };
1982
1983                 pcfg_pull_down: pcfg-pull-down {
1984                         bias-pull-down;
1985                 };
1986
1987                 pcfg_pull_none: pcfg-pull-none {
1988                         bias-disable;
1989                 };
1990
1991                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1992                         bias-disable;
1993                         drive-strength = <12>;
1994                 };
1995
1996                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1997                         bias-disable;
1998                         drive-strength = <13>;
1999                 };
2000
2001                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2002                         bias-disable;
2003                         drive-strength = <18>;
2004                 };
2005
2006                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2007                         bias-disable;
2008                         drive-strength = <20>;
2009                 };
2010
2011                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2012                         bias-pull-up;
2013                         drive-strength = <2>;
2014                 };
2015
2016                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2017                         bias-pull-up;
2018                         drive-strength = <8>;
2019                 };
2020
2021                 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
2022                         bias-pull-up;
2023                         drive-strength = <18>;
2024                 };
2025
2026                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2027                         bias-pull-up;
2028                         drive-strength = <20>;
2029                 };
2030
2031                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2032                         bias-pull-down;
2033                         drive-strength = <4>;
2034                 };
2035
2036                 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
2037                         bias-pull-down;
2038                         drive-strength = <8>;
2039                 };
2040
2041                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2042                         bias-pull-down;
2043                         drive-strength = <12>;
2044                 };
2045
2046                 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
2047                         bias-pull-down;
2048                         drive-strength = <18>;
2049                 };
2050
2051                 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
2052                         bias-pull-down;
2053                         drive-strength = <20>;
2054                 };
2055
2056                 pcfg_output_high: pcfg-output-high {
2057                         output-high;
2058                 };
2059
2060                 pcfg_output_low: pcfg-output-low {
2061                         output-low;
2062                 };
2063
2064                 clock {
2065                         clk_32k: clk-32k {
2066                                 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
2067                         };
2068                 };
2069
2070                 edp {
2071                         edp_hpd: edp-hpd {
2072                                 rockchip,pins =
2073                                         <4 RK_PC7 2 &pcfg_pull_none>;
2074                         };
2075                 };
2076
2077                 gmac {
2078                         rgmii_pins: rgmii-pins {
2079                                 rockchip,pins =
2080                                         /* mac_txclk */
2081                                         <3 RK_PC1 1 &pcfg_pull_none_13ma>,
2082                                         /* mac_rxclk */
2083                                         <3 RK_PB6 1 &pcfg_pull_none>,
2084                                         /* mac_mdio */
2085                                         <3 RK_PB5 1 &pcfg_pull_none>,
2086                                         /* mac_txen */
2087                                         <3 RK_PB4 1 &pcfg_pull_none_13ma>,
2088                                         /* mac_clk */
2089                                         <3 RK_PB3 1 &pcfg_pull_none>,
2090                                         /* mac_rxdv */
2091                                         <3 RK_PB1 1 &pcfg_pull_none>,
2092                                         /* mac_mdc */
2093                                         <3 RK_PB0 1 &pcfg_pull_none>,
2094                                         /* mac_rxd1 */
2095                                         <3 RK_PA7 1 &pcfg_pull_none>,
2096                                         /* mac_rxd0 */
2097                                         <3 RK_PA6 1 &pcfg_pull_none>,
2098                                         /* mac_txd1 */
2099                                         <3 RK_PA5 1 &pcfg_pull_none_13ma>,
2100                                         /* mac_txd0 */
2101                                         <3 RK_PA4 1 &pcfg_pull_none_13ma>,
2102                                         /* mac_rxd3 */
2103                                         <3 RK_PA3 1 &pcfg_pull_none>,
2104                                         /* mac_rxd2 */
2105                                         <3 RK_PA2 1 &pcfg_pull_none>,
2106                                         /* mac_txd3 */
2107                                         <3 RK_PA1 1 &pcfg_pull_none_13ma>,
2108                                         /* mac_txd2 */
2109                                         <3 RK_PA0 1 &pcfg_pull_none_13ma>;
2110                         };
2111
2112                         rmii_pins: rmii-pins {
2113                                 rockchip,pins =
2114                                         /* mac_mdio */
2115                                         <3 RK_PB5 1 &pcfg_pull_none>,
2116                                         /* mac_txen */
2117                                         <3 RK_PB4 1 &pcfg_pull_none_13ma>,
2118                                         /* mac_clk */
2119                                         <3 RK_PB3 1 &pcfg_pull_none>,
2120                                         /* mac_rxer */
2121                                         <3 RK_PB2 1 &pcfg_pull_none>,
2122                                         /* mac_rxdv */
2123                                         <3 RK_PB1 1 &pcfg_pull_none>,
2124                                         /* mac_mdc */
2125                                         <3 RK_PB0 1 &pcfg_pull_none>,
2126                                         /* mac_rxd1 */
2127                                         <3 RK_PA7 1 &pcfg_pull_none>,
2128                                         /* mac_rxd0 */
2129                                         <3 RK_PA6 1 &pcfg_pull_none>,
2130                                         /* mac_txd1 */
2131                                         <3 RK_PA5 1 &pcfg_pull_none_13ma>,
2132                                         /* mac_txd0 */
2133                                         <3 RK_PA4 1 &pcfg_pull_none_13ma>;
2134                         };
2135                 };
2136
2137                 i2c0 {
2138                         i2c0_xfer: i2c0-xfer {
2139                                 rockchip,pins =
2140                                         <1 RK_PB7 2 &pcfg_pull_none>,
2141                                         <1 RK_PC0 2 &pcfg_pull_none>;
2142                         };
2143                 };
2144
2145                 i2c1 {
2146                         i2c1_xfer: i2c1-xfer {
2147                                 rockchip,pins =
2148                                         <4 RK_PA2 1 &pcfg_pull_none>,
2149                                         <4 RK_PA1 1 &pcfg_pull_none>;
2150                         };
2151                 };
2152
2153                 i2c2 {
2154                         i2c2_xfer: i2c2-xfer {
2155                                 rockchip,pins =
2156                                         <2 RK_PA1 2 &pcfg_pull_none_12ma>,
2157                                         <2 RK_PA0 2 &pcfg_pull_none_12ma>;
2158                         };
2159                 };
2160
2161                 i2c3 {
2162                         i2c3_xfer: i2c3-xfer {
2163                                 rockchip,pins =
2164                                         <4 RK_PC1 1 &pcfg_pull_none>,
2165                                         <4 RK_PC0 1 &pcfg_pull_none>;
2166                         };
2167                 };
2168
2169                 i2c4 {
2170                         i2c4_xfer: i2c4-xfer {
2171                                 rockchip,pins =
2172                                         <1 RK_PB4 1 &pcfg_pull_none>,
2173                                         <1 RK_PB3 1 &pcfg_pull_none>;
2174                         };
2175                 };
2176
2177                 i2c5 {
2178                         i2c5_xfer: i2c5-xfer {
2179                                 rockchip,pins =
2180                                         <3 RK_PB3 2 &pcfg_pull_none>,
2181                                         <3 RK_PB2 2 &pcfg_pull_none>;
2182                         };
2183                 };
2184
2185                 i2c6 {
2186                         i2c6_xfer: i2c6-xfer {
2187                                 rockchip,pins =
2188                                         <2 RK_PB2 2 &pcfg_pull_none>,
2189                                         <2 RK_PB1 2 &pcfg_pull_none>;
2190                         };
2191                 };
2192
2193                 i2c7 {
2194                         i2c7_xfer: i2c7-xfer {
2195                                 rockchip,pins =
2196                                         <2 RK_PB0 2 &pcfg_pull_none>,
2197                                         <2 RK_PA7 2 &pcfg_pull_none>;
2198                         };
2199                 };
2200
2201                 i2c8 {
2202                         i2c8_xfer: i2c8-xfer {
2203                                 rockchip,pins =
2204                                         <1 RK_PC5 1 &pcfg_pull_none>,
2205                                         <1 RK_PC4 1 &pcfg_pull_none>;
2206                         };
2207                 };
2208
2209                 i2s0 {
2210                         i2s0_2ch_bus: i2s0-2ch-bus {
2211                                 rockchip,pins =
2212                                         <3 RK_PD0 1 &pcfg_pull_none>,
2213                                         <3 RK_PD1 1 &pcfg_pull_none>,
2214                                         <3 RK_PD2 1 &pcfg_pull_none>,
2215                                         <3 RK_PD3 1 &pcfg_pull_none>,
2216                                         <3 RK_PD7 1 &pcfg_pull_none>,
2217                                         <4 RK_PA0 1 &pcfg_pull_none>;
2218                         };
2219
2220                         i2s0_8ch_bus: i2s0-8ch-bus {
2221                                 rockchip,pins =
2222                                         <3 RK_PD0 1 &pcfg_pull_none>,
2223                                         <3 RK_PD1 1 &pcfg_pull_none>,
2224                                         <3 RK_PD2 1 &pcfg_pull_none>,
2225                                         <3 RK_PD3 1 &pcfg_pull_none>,
2226                                         <3 RK_PD4 1 &pcfg_pull_none>,
2227                                         <3 RK_PD5 1 &pcfg_pull_none>,
2228                                         <3 RK_PD6 1 &pcfg_pull_none>,
2229                                         <3 RK_PD7 1 &pcfg_pull_none>,
2230                                         <4 RK_PA0 1 &pcfg_pull_none>;
2231                         };
2232                 };
2233
2234                 i2s1 {
2235                         i2s1_2ch_bus: i2s1-2ch-bus {
2236                                 rockchip,pins =
2237                                         <4 RK_PA3 1 &pcfg_pull_none>,
2238                                         <4 RK_PA4 1 &pcfg_pull_none>,
2239                                         <4 RK_PA5 1 &pcfg_pull_none>,
2240                                         <4 RK_PA6 1 &pcfg_pull_none>,
2241                                         <4 RK_PA7 1 &pcfg_pull_none>;
2242                         };
2243                 };
2244
2245                 sdio0 {
2246                         sdio0_bus1: sdio0-bus1 {
2247                                 rockchip,pins =
2248                                         <2 RK_PC4 1 &pcfg_pull_up>;
2249                         };
2250
2251                         sdio0_bus4: sdio0-bus4 {
2252                                 rockchip,pins =
2253                                         <2 RK_PC4 1 &pcfg_pull_up>,
2254                                         <2 RK_PC5 1 &pcfg_pull_up>,
2255                                         <2 RK_PC6 1 &pcfg_pull_up>,
2256                                         <2 RK_PC7 1 &pcfg_pull_up>;
2257                         };
2258
2259                         sdio0_cmd: sdio0-cmd {
2260                                 rockchip,pins =
2261                                         <2 RK_PD0 1 &pcfg_pull_up>;
2262                         };
2263
2264                         sdio0_clk: sdio0-clk {
2265                                 rockchip,pins =
2266                                         <2 RK_PD1 1 &pcfg_pull_none>;
2267                         };
2268
2269                         sdio0_cd: sdio0-cd {
2270                                 rockchip,pins =
2271                                         <2 RK_PD2 1 &pcfg_pull_up>;
2272                         };
2273
2274                         sdio0_pwr: sdio0-pwr {
2275                                 rockchip,pins =
2276                                         <2 RK_PD3 1 &pcfg_pull_up>;
2277                         };
2278
2279                         sdio0_bkpwr: sdio0-bkpwr {
2280                                 rockchip,pins =
2281                                         <2 RK_PD4 1 &pcfg_pull_up>;
2282                         };
2283
2284                         sdio0_wp: sdio0-wp {
2285                                 rockchip,pins =
2286                                         <0 RK_PA3 1 &pcfg_pull_up>;
2287                         };
2288
2289                         sdio0_int: sdio0-int {
2290                                 rockchip,pins =
2291                                         <0 RK_PA4 1 &pcfg_pull_up>;
2292                         };
2293                 };
2294
2295                 sdmmc {
2296                         sdmmc_bus1: sdmmc-bus1 {
2297                                 rockchip,pins =
2298                                         <4 RK_PB0 1 &pcfg_pull_up>;
2299                         };
2300
2301                         sdmmc_bus4: sdmmc-bus4 {
2302                                 rockchip,pins =
2303                                         <4 RK_PB0 1 &pcfg_pull_up>,
2304                                         <4 RK_PB1 1 &pcfg_pull_up>,
2305                                         <4 RK_PB2 1 &pcfg_pull_up>,
2306                                         <4 RK_PB3 1 &pcfg_pull_up>;
2307                         };
2308
2309                         sdmmc_clk: sdmmc-clk {
2310                                 rockchip,pins =
2311                                         <4 RK_PB4 1 &pcfg_pull_none>;
2312                         };
2313
2314                         sdmmc_cmd: sdmmc-cmd {
2315                                 rockchip,pins =
2316                                         <4 RK_PB5 1 &pcfg_pull_up>;
2317                         };
2318
2319                         sdmmc_cd: sdmmc-cd {
2320                                 rockchip,pins =
2321                                         <0 RK_PA7 1 &pcfg_pull_up>;
2322                         };
2323
2324                         sdmmc_wp: sdmmc-wp {
2325                                 rockchip,pins =
2326                                         <0 RK_PB0 1 &pcfg_pull_up>;
2327                         };
2328                 };
2329
2330                 sleep {
2331                         ap_pwroff: ap-pwroff {
2332                                 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>;
2333                         };
2334
2335                         ddrio_pwroff: ddrio-pwroff {
2336                                 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
2337                         };
2338                 };
2339
2340                 spdif {
2341                         spdif_bus: spdif-bus {
2342                                 rockchip,pins =
2343                                         <4 RK_PC5 1 &pcfg_pull_none>;
2344                         };
2345
2346                         spdif_bus_1: spdif-bus-1 {
2347                                 rockchip,pins =
2348                                         <3 RK_PC0 3 &pcfg_pull_none>;
2349                         };
2350                 };
2351
2352                 spi0 {
2353                         spi0_clk: spi0-clk {
2354                                 rockchip,pins =
2355                                         <3 RK_PA6 2 &pcfg_pull_up>;
2356                         };
2357                         spi0_cs0: spi0-cs0 {
2358                                 rockchip,pins =
2359                                         <3 RK_PA7 2 &pcfg_pull_up>;
2360                         };
2361                         spi0_cs1: spi0-cs1 {
2362                                 rockchip,pins =
2363                                         <3 RK_PB0 2 &pcfg_pull_up>;
2364                         };
2365                         spi0_tx: spi0-tx {
2366                                 rockchip,pins =
2367                                         <3 RK_PA5 2 &pcfg_pull_up>;
2368                         };
2369                         spi0_rx: spi0-rx {
2370                                 rockchip,pins =
2371                                         <3 RK_PA4 2 &pcfg_pull_up>;
2372                         };
2373                 };
2374
2375                 spi1 {
2376                         spi1_clk: spi1-clk {
2377                                 rockchip,pins =
2378                                         <1 RK_PB1 2 &pcfg_pull_up>;
2379                         };
2380                         spi1_cs0: spi1-cs0 {
2381                                 rockchip,pins =
2382                                         <1 RK_PB2 2 &pcfg_pull_up>;
2383                         };
2384                         spi1_rx: spi1-rx {
2385                                 rockchip,pins =
2386                                         <1 RK_PA7 2 &pcfg_pull_up>;
2387                         };
2388                         spi1_tx: spi1-tx {
2389                                 rockchip,pins =
2390                                         <1 RK_PB0 2 &pcfg_pull_up>;
2391                         };
2392                 };
2393
2394                 spi2 {
2395                         spi2_clk: spi2-clk {
2396                                 rockchip,pins =
2397                                         <2 RK_PB3 1 &pcfg_pull_up>;
2398                         };
2399                         spi2_cs0: spi2-cs0 {
2400                                 rockchip,pins =
2401                                         <2 RK_PB4 1 &pcfg_pull_up>;
2402                         };
2403                         spi2_rx: spi2-rx {
2404                                 rockchip,pins =
2405                                         <2 RK_PB1 1 &pcfg_pull_up>;
2406                         };
2407                         spi2_tx: spi2-tx {
2408                                 rockchip,pins =
2409                                         <2 RK_PB2 1 &pcfg_pull_up>;
2410                         };
2411                 };
2412
2413                 spi3 {
2414                         spi3_clk: spi3-clk {
2415                                 rockchip,pins =
2416                                         <1 RK_PC1 1 &pcfg_pull_up>;
2417                         };
2418                         spi3_cs0: spi3-cs0 {
2419                                 rockchip,pins =
2420                                         <1 RK_PC2 1 &pcfg_pull_up>;
2421                         };
2422                         spi3_rx: spi3-rx {
2423                                 rockchip,pins =
2424                                         <1 RK_PB7 1 &pcfg_pull_up>;
2425                         };
2426                         spi3_tx: spi3-tx {
2427                                 rockchip,pins =
2428                                         <1 RK_PC0 1 &pcfg_pull_up>;
2429                         };
2430                 };
2431
2432                 spi4 {
2433                         spi4_clk: spi4-clk {
2434                                 rockchip,pins =
2435                                         <3 RK_PA2 2 &pcfg_pull_up>;
2436                         };
2437                         spi4_cs0: spi4-cs0 {
2438                                 rockchip,pins =
2439                                         <3 RK_PA3 2 &pcfg_pull_up>;
2440                         };
2441                         spi4_rx: spi4-rx {
2442                                 rockchip,pins =
2443                                         <3 RK_PA0 2 &pcfg_pull_up>;
2444                         };
2445                         spi4_tx: spi4-tx {
2446                                 rockchip,pins =
2447                                         <3 RK_PA1 2 &pcfg_pull_up>;
2448                         };
2449                 };
2450
2451                 spi5 {
2452                         spi5_clk: spi5-clk {
2453                                 rockchip,pins =
2454                                         <2 RK_PC6 2 &pcfg_pull_up>;
2455                         };
2456                         spi5_cs0: spi5-cs0 {
2457                                 rockchip,pins =
2458                                         <2 RK_PC7 2 &pcfg_pull_up>;
2459                         };
2460                         spi5_rx: spi5-rx {
2461                                 rockchip,pins =
2462                                         <2 RK_PC4 2 &pcfg_pull_up>;
2463                         };
2464                         spi5_tx: spi5-tx {
2465                                 rockchip,pins =
2466                                         <2 RK_PC5 2 &pcfg_pull_up>;
2467                         };
2468                 };
2469
2470                 testclk {
2471                         test_clkout0: test-clkout0 {
2472                                 rockchip,pins =
2473                                         <0 RK_PA0 1 &pcfg_pull_none>;
2474                         };
2475
2476                         test_clkout1: test-clkout1 {
2477                                 rockchip,pins =
2478                                         <2 RK_PD1 2 &pcfg_pull_none>;
2479                         };
2480
2481                         test_clkout2: test-clkout2 {
2482                                 rockchip,pins =
2483                                         <0 RK_PB0 3 &pcfg_pull_none>;
2484                         };
2485                 };
2486
2487                 tsadc {
2488                         otp_gpio: otp-gpio {
2489                                 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
2490                         };
2491
2492                         otp_out: otp-out {
2493                                 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
2494                         };
2495                 };
2496
2497                 uart0 {
2498                         uart0_xfer: uart0-xfer {
2499                                 rockchip,pins =
2500                                         <2 RK_PC0 1 &pcfg_pull_up>,
2501                                         <2 RK_PC1 1 &pcfg_pull_none>;
2502                         };
2503
2504                         uart0_cts: uart0-cts {
2505                                 rockchip,pins =
2506                                         <2 RK_PC2 1 &pcfg_pull_none>;
2507                         };
2508
2509                         uart0_rts: uart0-rts {
2510                                 rockchip,pins =
2511                                         <2 RK_PC3 1 &pcfg_pull_none>;
2512                         };
2513                 };
2514
2515                 uart1 {
2516                         uart1_xfer: uart1-xfer {
2517                                 rockchip,pins =
2518                                         <3 RK_PB4 2 &pcfg_pull_up>,
2519                                         <3 RK_PB5 2 &pcfg_pull_none>;
2520                         };
2521                 };
2522
2523                 uart2a {
2524                         uart2a_xfer: uart2a-xfer {
2525                                 rockchip,pins =
2526                                         <4 RK_PB0 2 &pcfg_pull_up>,
2527                                         <4 RK_PB1 2 &pcfg_pull_none>;
2528                         };
2529                 };
2530
2531                 uart2b {
2532                         uart2b_xfer: uart2b-xfer {
2533                                 rockchip,pins =
2534                                         <4 RK_PC0 2 &pcfg_pull_up>,
2535                                         <4 RK_PC1 2 &pcfg_pull_none>;
2536                         };
2537                 };
2538
2539                 uart2c {
2540                         uart2c_xfer: uart2c-xfer {
2541                                 rockchip,pins =
2542                                         <4 RK_PC3 1 &pcfg_pull_up>,
2543                                         <4 RK_PC4 1 &pcfg_pull_none>;
2544                         };
2545                 };
2546
2547                 uart3 {
2548                         uart3_xfer: uart3-xfer {
2549                                 rockchip,pins =
2550                                         <3 RK_PB6 2 &pcfg_pull_up>,
2551                                         <3 RK_PB7 2 &pcfg_pull_none>;
2552                         };
2553
2554                         uart3_cts: uart3-cts {
2555                                 rockchip,pins =
2556                                         <3 RK_PC0 2 &pcfg_pull_none>;
2557                         };
2558
2559                         uart3_rts: uart3-rts {
2560                                 rockchip,pins =
2561                                         <3 RK_PC1 2 &pcfg_pull_none>;
2562                         };
2563                 };
2564
2565                 uart4 {
2566                         uart4_xfer: uart4-xfer {
2567                                 rockchip,pins =
2568                                         <1 RK_PA7 1 &pcfg_pull_up>,
2569                                         <1 RK_PB0 1 &pcfg_pull_none>;
2570                         };
2571                 };
2572
2573                 uarthdcp {
2574                         uarthdcp_xfer: uarthdcp-xfer {
2575                                 rockchip,pins =
2576                                         <4 RK_PC5 2 &pcfg_pull_up>,
2577                                         <4 RK_PC6 2 &pcfg_pull_none>;
2578                         };
2579                 };
2580
2581                 pwm0 {
2582                         pwm0_pin: pwm0-pin {
2583                                 rockchip,pins =
2584                                         <4 RK_PC2 1 &pcfg_pull_none>;
2585                         };
2586
2587                         pwm0_pin_pull_down: pwm0-pin-pull-down {
2588                                 rockchip,pins =
2589                                         <4 RK_PC2 1 &pcfg_pull_down>;
2590                         };
2591
2592                         vop0_pwm_pin: vop0-pwm-pin {
2593                                 rockchip,pins =
2594                                         <4 RK_PC2 2 &pcfg_pull_none>;
2595                         };
2596
2597                         vop1_pwm_pin: vop1-pwm-pin {
2598                                 rockchip,pins =
2599                                         <4 RK_PC2 3 &pcfg_pull_none>;
2600                         };
2601                 };
2602
2603                 pwm1 {
2604                         pwm1_pin: pwm1-pin {
2605                                 rockchip,pins =
2606                                         <4 RK_PC6 1 &pcfg_pull_none>;
2607                         };
2608
2609                         pwm1_pin_pull_down: pwm1-pin-pull-down {
2610                                 rockchip,pins =
2611                                         <4 RK_PC6 1 &pcfg_pull_down>;
2612                         };
2613                 };
2614
2615                 pwm2 {
2616                         pwm2_pin: pwm2-pin {
2617                                 rockchip,pins =
2618                                         <1 RK_PC3 1 &pcfg_pull_none>;
2619                         };
2620
2621                         pwm2_pin_pull_down: pwm2-pin-pull-down {
2622                                 rockchip,pins =
2623                                         <1 RK_PC3 1 &pcfg_pull_down>;
2624                         };
2625                 };
2626
2627                 pwm3a {
2628                         pwm3a_pin: pwm3a-pin {
2629                                 rockchip,pins =
2630                                         <0 RK_PA6 1 &pcfg_pull_none>;
2631                         };
2632                 };
2633
2634                 pwm3b {
2635                         pwm3b_pin: pwm3b-pin {
2636                                 rockchip,pins =
2637                                         <1 RK_PB6 1 &pcfg_pull_none>;
2638                         };
2639                 };
2640
2641                 hdmi {
2642                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2643                                 rockchip,pins =
2644                                         <4 RK_PC1 3 &pcfg_pull_none>,
2645                                         <4 RK_PC0 3 &pcfg_pull_none>;
2646                         };
2647
2648                         hdmi_cec: hdmi-cec {
2649                                 rockchip,pins =
2650                                         <4 RK_PC7 1 &pcfg_pull_none>;
2651                         };
2652                 };
2653
2654                 pcie {
2655                         pcie_clkreqn_cpm: pci-clkreqn-cpm {
2656                                 rockchip,pins =
2657                                         <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2658                         };
2659
2660                         pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2661                                 rockchip,pins =
2662                                         <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
2663                         };
2664                 };
2665
2666         };
2667 };