src/arm64/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 i2c0 = &i2c0;
  60                 i2c1 = &i2c1;
  61                 i2c2 = &i2c2;
  62                 i2c3 = &i2c3;
  63                 i2c4 = &i2c4;
  64                 i2c5 = &i2c5;
  65                 i2c6 = &i2c6;
  66                 i2c7 = &i2c7;
  67                 i2c8 = &i2c8;
  68                 serial0 = &uart0;
  69                 serial1 = &uart1;
  70                 serial2 = &uart2;
  71                 serial3 = &uart3;
  72                 serial4 = &uart4;
  73         };
  74
  75         cpus {
  76                 #address-cells = <2>;
  77                 #size-cells = <0>;
  78
  79                 cpu-map {
  80                         cluster0 {
  81                                 core0 {
  82                                         cpu = <&cpu_l0>;
  83                                 };
  84                                 core1 {
  85                                         cpu = <&cpu_l1>;
  86                                 };
  87                                 core2 {
  88                                         cpu = <&cpu_l2>;
  89                                 };
  90                                 core3 {
  91                                         cpu = <&cpu_l3>;
  92                                 };
  93                         };
  94
  95                         cluster1 {
  96                                 core0 {
  97                                         cpu = <&cpu_b0>;
  98                                 };
  99                                 core1 {
 100                                         cpu = <&cpu_b1>;
 101                                 };
 102                         };
 103                 };
 104
 105                 cpu_l0: cpu@0 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a53", "arm,armv8";
 108                         reg = <0x0 0x0>;
 109                         enable-method = "psci";
 110                         #cooling-cells = <2>; /* min followed by max */
 111                         clocks = <&cru ARMCLKL>;
 112                 };
 113
 114                 cpu_l1: cpu@1 {
 115                         device_type = "cpu";
 116                         compatible = "arm,cortex-a53", "arm,armv8";
 117                         reg = <0x0 0x1>;
 118                         enable-method = "psci";
 119                         clocks = <&cru ARMCLKL>;
 120                 };
 121
 122                 cpu_l2: cpu@2 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a53", "arm,armv8";
 125                         reg = <0x0 0x2>;
 126                         enable-method = "psci";
 127                         clocks = <&cru ARMCLKL>;
 128                 };
 129
 130                 cpu_l3: cpu@3 {
 131                         device_type = "cpu";
 132                         compatible = "arm,cortex-a53", "arm,armv8";
 133                         reg = <0x0 0x3>;
 134                         enable-method = "psci";
 135                         clocks = <&cru ARMCLKL>;
 136                 };
 137
 138                 cpu_b0: cpu@100 {
 139                         device_type = "cpu";
 140                         compatible = "arm,cortex-a72", "arm,armv8";
 141                         reg = <0x0 0x100>;
 142                         enable-method = "psci";
 143                         #cooling-cells = <2>; /* min followed by max */
 144                         clocks = <&cru ARMCLKB>;
 145                 };
 146
 147                 cpu_b1: cpu@101 {
 148                         device_type = "cpu";
 149                         compatible = "arm,cortex-a72", "arm,armv8";
 150                         reg = <0x0 0x101>;
 151                         enable-method = "psci";
 152                         clocks = <&cru ARMCLKB>;
 153                 };
 154         };
 155
 156         pmu_a53 {
 157                 compatible = "arm,cortex-a53-pmu";
 158                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 159         };
 160
 161         pmu_a72 {
 162                 compatible = "arm,cortex-a72-pmu";
 163                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 164         };
 165
 166         psci {
 167                 compatible = "arm,psci-1.0";
 168                 method = "smc";
 169         };
 170
 171         timer {
 172                 compatible = "arm,armv8-timer";
 173                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 174                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 175                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 176                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 177                 arm,no-tick-in-suspend;
 178         };
 179
 180         xin24m: xin24m {
 181                 compatible = "fixed-clock";
 182                 clock-frequency = <24000000>;
 183                 clock-output-names = "xin24m";
 184                 #clock-cells = <0>;
 185         };
 186
 187         amba {
 188                 compatible = "simple-bus";
 189                 #address-cells = <2>;
 190                 #size-cells = <2>;
 191                 ranges;
 192
 193                 dmac_bus: dma-controller@ff6d0000 {
 194                         compatible = "arm,pl330", "arm,primecell";
 195                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 196                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 197                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 198                         #dma-cells = <1>;
 199                         clocks = <&cru ACLK_DMAC0_PERILP>;
 200                         clock-names = "apb_pclk";
 201                 };
 202
 203                 dmac_peri: dma-controller@ff6e0000 {
 204                         compatible = "arm,pl330", "arm,primecell";
 205                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 206                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 207                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 208                         #dma-cells = <1>;
 209                         clocks = <&cru ACLK_DMAC1_PERILP>;
 210                         clock-names = "apb_pclk";
 211                 };
 212         };
 213
 214         pcie0: pcie@f8000000 {
 215                 compatible = "rockchip,rk3399-pcie";
 216                 reg = <0x0 0xf8000000 0x0 0x2000000>,
 217                       <0x0 0xfd000000 0x0 0x1000000>;
 218                 reg-names = "axi-base", "apb-base";
 219                 #address-cells = <3>;
 220                 #size-cells = <2>;
 221                 #interrupt-cells = <1>;
 222                 aspm-no-l0s;
 223                 bus-range = <0x0 0x1>;
 224                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
 225                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
 226                 clock-names = "aclk", "aclk-perf",
 227                               "hclk", "pm";
 228                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
 229                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
 230                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
 231                 interrupt-names = "sys", "legacy", "client";
 232                 interrupt-map-mask = <0 0 0 7>;
 233                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
 234                                 <0 0 0 2 &pcie0_intc 1>,
 235                                 <0 0 0 3 &pcie0_intc 2>,
 236                                 <0 0 0 4 &pcie0_intc 3>;
 237                 linux,pci-domain = <0>;
 238                 max-link-speed = <1>;
 239                 msi-map = <0x0 &its 0x0 0x1000>;
 240                 phys = <&pcie_phy>;
 241                 phy-names = "pcie-phy";
 242                 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
 243                           0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
 244                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
 245                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
 246                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
 247                          <&cru SRST_A_PCIE>;
 248                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
 249                               "pm", "pclk", "aclk";
 250                 status = "disabled";
 251
 252                 pcie0_intc: interrupt-controller {
 253                         interrupt-controller;
 254                         #address-cells = <0>;
 255                         #interrupt-cells = <1>;
 256                 };
 257         };
 258
 259         gmac: ethernet@fe300000 {
 260                 compatible = "rockchip,rk3399-gmac";
 261                 reg = <0x0 0xfe300000 0x0 0x10000>;
 262                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 263                 interrupt-names = "macirq";
 264                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 265                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 266                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 267                          <&cru PCLK_GMAC>;
 268                 clock-names = "stmmaceth", "mac_clk_rx",
 269                               "mac_clk_tx", "clk_mac_ref",
 270                               "clk_mac_refout", "aclk_mac",
 271                               "pclk_mac";
 272                 power-domains = <&power RK3399_PD_GMAC>;
 273                 resets = <&cru SRST_A_GMAC>;
 274                 reset-names = "stmmaceth";
 275                 rockchip,grf = <&grf>;
 276                 status = "disabled";
 277         };
 278
 279         sdio0: dwmmc@fe310000 {
 280                 compatible = "rockchip,rk3399-dw-mshc",
 281                              "rockchip,rk3288-dw-mshc";
 282                 reg = <0x0 0xfe310000 0x0 0x4000>;
 283                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 284                 max-frequency = <150000000>;
 285                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 286                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 287                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 288                 fifo-depth = <0x100>;
 289                 resets = <&cru SRST_SDIO0>;
 290                 reset-names = "reset";
 291                 status = "disabled";
 292         };
 293
 294         sdmmc: dwmmc@fe320000 {
 295                 compatible = "rockchip,rk3399-dw-mshc",
 296                              "rockchip,rk3288-dw-mshc";
 297                 reg = <0x0 0xfe320000 0x0 0x4000>;
 298                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 299                 max-frequency = <150000000>;
 300                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 301                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 302                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 303                 fifo-depth = <0x100>;
 304                 power-domains = <&power RK3399_PD_SD>;
 305                 resets = <&cru SRST_SDMMC>;
 306                 reset-names = "reset";
 307                 status = "disabled";
 308         };
 309
 310         sdhci: sdhci@fe330000 {
 311                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 312                 reg = <0x0 0xfe330000 0x0 0x10000>;
 313                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 314                 arasan,soc-ctl-syscon = <&grf>;
 315                 assigned-clocks = <&cru SCLK_EMMC>;
 316                 assigned-clock-rates = <200000000>;
 317                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 318                 clock-names = "clk_xin", "clk_ahb";
 319                 clock-output-names = "emmc_cardclock";
 320                 #clock-cells = <0>;
 321                 phys = <&emmc_phy>;
 322                 phy-names = "phy_arasan";
 323                 power-domains = <&power RK3399_PD_EMMC>;
 324                 status = "disabled";
 325         };
 326
 327         usb_host0_ehci: usb@fe380000 {
 328                 compatible = "generic-ehci";
 329                 reg = <0x0 0xfe380000 0x0 0x20000>;
 330                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 331                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 332                          <&u2phy0>;
 333                 clock-names = "usbhost", "arbiter",
 334                               "utmi";
 335                 phys = <&u2phy0_host>;
 336                 phy-names = "usb";
 337                 status = "disabled";
 338         };
 339
 340         usb_host0_ohci: usb@fe3a0000 {
 341                 compatible = "generic-ohci";
 342                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 343                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 344                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 345                          <&u2phy0>;
 346                 clock-names = "usbhost", "arbiter",
 347                               "utmi";
 348                 phys = <&u2phy0_host>;
 349                 phy-names = "usb";
 350                 status = "disabled";
 351         };
 352
 353         usb_host1_ehci: usb@fe3c0000 {
 354                 compatible = "generic-ehci";
 355                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 356                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 357                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 358                          <&u2phy1>;
 359                 clock-names = "usbhost", "arbiter",
 360                               "utmi";
 361                 phys = <&u2phy1_host>;
 362                 phy-names = "usb";
 363                 status = "disabled";
 364         };
 365
 366         usb_host1_ohci: usb@fe3e0000 {
 367                 compatible = "generic-ohci";
 368                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 369                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 370                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 371                          <&u2phy1>;
 372                 clock-names = "usbhost", "arbiter",
 373                               "utmi";
 374                 phys = <&u2phy1_host>;
 375                 phy-names = "usb";
 376                 status = "disabled";
 377         };
 378
 379         usbdrd3_0: usb@fe800000 {
 380                 compatible = "rockchip,rk3399-dwc3";
 381                 #address-cells = <2>;
 382                 #size-cells = <2>;
 383                 ranges;
 384                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 385                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
 386                 clock-names = "ref_clk", "suspend_clk",
 387                               "bus_clk", "grf_clk";
 388                 status = "disabled";
 389
 390                 usbdrd_dwc3_0: dwc3 {
 391                         compatible = "snps,dwc3";
 392                         reg = <0x0 0xfe800000 0x0 0x100000>;
 393                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 394                         dr_mode = "otg";
 395                         phys = <&u2phy0_otg>;
 396                         phy-names = "usb2-phy";
 397                         phy_type = "utmi_wide";
 398                         snps,dis_enblslpm_quirk;
 399                         snps,dis-u2-freeclk-exists-quirk;
 400                         snps,dis_u2_susphy_quirk;
 401                         snps,dis-del-phy-power-chg-quirk;
 402                         status = "disabled";
 403                 };
 404         };
 405
 406         usbdrd3_1: usb@fe900000 {
 407                 compatible = "rockchip,rk3399-dwc3";
 408                 #address-cells = <2>;
 409                 #size-cells = <2>;
 410                 ranges;
 411                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 412                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
 413                 clock-names = "ref_clk", "suspend_clk",
 414                               "bus_clk", "grf_clk";
 415                 status = "disabled";
 416
 417                 usbdrd_dwc3_1: dwc3 {
 418                         compatible = "snps,dwc3";
 419                         reg = <0x0 0xfe900000 0x0 0x100000>;
 420                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 421                         dr_mode = "otg";
 422                         phys = <&u2phy1_otg>;
 423                         phy-names = "usb2-phy";
 424                         phy_type = "utmi_wide";
 425                         snps,dis_enblslpm_quirk;
 426                         snps,dis-u2-freeclk-exists-quirk;
 427                         snps,dis_u2_susphy_quirk;
 428                         snps,dis-del-phy-power-chg-quirk;
 429                         status = "disabled";
 430                 };
 431         };
 432
 433         gic: interrupt-controller@fee00000 {
 434                 compatible = "arm,gic-v3";
 435                 #interrupt-cells = <4>;
 436                 #address-cells = <2>;
 437                 #size-cells = <2>;
 438                 ranges;
 439                 interrupt-controller;
 440
 441                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 442                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 443                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 444                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 445                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 446                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 447                 its: interrupt-controller@fee20000 {
 448                         compatible = "arm,gic-v3-its";
 449                         msi-controller;
 450                         reg = <0x0 0xfee20000 0x0 0x20000>;
 451                 };
 452
 453                 ppi-partitions {
 454                         ppi_cluster0: interrupt-partition-0 {
 455                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 456                         };
 457
 458                         ppi_cluster1: interrupt-partition-1 {
 459                                 affinity = <&cpu_b0 &cpu_b1>;
 460                         };
 461                 };
 462         };
 463
 464         saradc: saradc@ff100000 {
 465                 compatible = "rockchip,rk3399-saradc";
 466                 reg = <0x0 0xff100000 0x0 0x100>;
 467                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 468                 #io-channel-cells = <1>;
 469                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 470                 clock-names = "saradc", "apb_pclk";
 471                 resets = <&cru SRST_P_SARADC>;
 472                 reset-names = "saradc-apb";
 473                 status = "disabled";
 474         };
 475
 476         i2c1: i2c@ff110000 {
 477                 compatible = "rockchip,rk3399-i2c";
 478                 reg = <0x0 0xff110000 0x0 0x1000>;
 479                 assigned-clocks = <&cru SCLK_I2C1>;
 480                 assigned-clock-rates = <200000000>;
 481                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 482                 clock-names = "i2c", "pclk";
 483                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 484                 pinctrl-names = "default";
 485                 pinctrl-0 = <&i2c1_xfer>;
 486                 #address-cells = <1>;
 487                 #size-cells = <0>;
 488                 status = "disabled";
 489         };
 490
 491         i2c2: i2c@ff120000 {
 492                 compatible = "rockchip,rk3399-i2c";
 493                 reg = <0x0 0xff120000 0x0 0x1000>;
 494                 assigned-clocks = <&cru SCLK_I2C2>;
 495                 assigned-clock-rates = <200000000>;
 496                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 497                 clock-names = "i2c", "pclk";
 498                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 499                 pinctrl-names = "default";
 500                 pinctrl-0 = <&i2c2_xfer>;
 501                 #address-cells = <1>;
 502                 #size-cells = <0>;
 503                 status = "disabled";
 504         };
 505
 506         i2c3: i2c@ff130000 {
 507                 compatible = "rockchip,rk3399-i2c";
 508                 reg = <0x0 0xff130000 0x0 0x1000>;
 509                 assigned-clocks = <&cru SCLK_I2C3>;
 510                 assigned-clock-rates = <200000000>;
 511                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 512                 clock-names = "i2c", "pclk";
 513                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 514                 pinctrl-names = "default";
 515                 pinctrl-0 = <&i2c3_xfer>;
 516                 #address-cells = <1>;
 517                 #size-cells = <0>;
 518                 status = "disabled";
 519         };
 520
 521         i2c5: i2c@ff140000 {
 522                 compatible = "rockchip,rk3399-i2c";
 523                 reg = <0x0 0xff140000 0x0 0x1000>;
 524                 assigned-clocks = <&cru SCLK_I2C5>;
 525                 assigned-clock-rates = <200000000>;
 526                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 527                 clock-names = "i2c", "pclk";
 528                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 529                 pinctrl-names = "default";
 530                 pinctrl-0 = <&i2c5_xfer>;
 531                 #address-cells = <1>;
 532                 #size-cells = <0>;
 533                 status = "disabled";
 534         };
 535
 536         i2c6: i2c@ff150000 {
 537                 compatible = "rockchip,rk3399-i2c";
 538                 reg = <0x0 0xff150000 0x0 0x1000>;
 539                 assigned-clocks = <&cru SCLK_I2C6>;
 540                 assigned-clock-rates = <200000000>;
 541                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 542                 clock-names = "i2c", "pclk";
 543                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 544                 pinctrl-names = "default";
 545                 pinctrl-0 = <&i2c6_xfer>;
 546                 #address-cells = <1>;
 547                 #size-cells = <0>;
 548                 status = "disabled";
 549         };
 550
 551         i2c7: i2c@ff160000 {
 552                 compatible = "rockchip,rk3399-i2c";
 553                 reg = <0x0 0xff160000 0x0 0x1000>;
 554                 assigned-clocks = <&cru SCLK_I2C7>;
 555                 assigned-clock-rates = <200000000>;
 556                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 557                 clock-names = "i2c", "pclk";
 558                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 559                 pinctrl-names = "default";
 560                 pinctrl-0 = <&i2c7_xfer>;
 561                 #address-cells = <1>;
 562                 #size-cells = <0>;
 563                 status = "disabled";
 564         };
 565
 566         uart0: serial@ff180000 {
 567                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 568                 reg = <0x0 0xff180000 0x0 0x100>;
 569                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 570                 clock-names = "baudclk", "apb_pclk";
 571                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 572                 reg-shift = <2>;
 573                 reg-io-width = <4>;
 574                 pinctrl-names = "default";
 575                 pinctrl-0 = <&uart0_xfer>;
 576                 status = "disabled";
 577         };
 578
 579         uart1: serial@ff190000 {
 580                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 581                 reg = <0x0 0xff190000 0x0 0x100>;
 582                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 583                 clock-names = "baudclk", "apb_pclk";
 584                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 585                 reg-shift = <2>;
 586                 reg-io-width = <4>;
 587                 pinctrl-names = "default";
 588                 pinctrl-0 = <&uart1_xfer>;
 589                 status = "disabled";
 590         };
 591
 592         uart2: serial@ff1a0000 {
 593                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 594                 reg = <0x0 0xff1a0000 0x0 0x100>;
 595                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 596                 clock-names = "baudclk", "apb_pclk";
 597                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 598                 reg-shift = <2>;
 599                 reg-io-width = <4>;
 600                 pinctrl-names = "default";
 601                 pinctrl-0 = <&uart2c_xfer>;
 602                 status = "disabled";
 603         };
 604
 605         uart3: serial@ff1b0000 {
 606                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 607                 reg = <0x0 0xff1b0000 0x0 0x100>;
 608                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 609                 clock-names = "baudclk", "apb_pclk";
 610                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 611                 reg-shift = <2>;
 612                 reg-io-width = <4>;
 613                 pinctrl-names = "default";
 614                 pinctrl-0 = <&uart3_xfer>;
 615                 status = "disabled";
 616         };
 617
 618         spi0: spi@ff1c0000 {
 619                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 620                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 621                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 622                 clock-names = "spiclk", "apb_pclk";
 623                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 624                 pinctrl-names = "default";
 625                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 626                 #address-cells = <1>;
 627                 #size-cells = <0>;
 628                 status = "disabled";
 629         };
 630
 631         spi1: spi@ff1d0000 {
 632                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 633                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 634                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 635                 clock-names = "spiclk", "apb_pclk";
 636                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 637                 pinctrl-names = "default";
 638                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 639                 #address-cells = <1>;
 640                 #size-cells = <0>;
 641                 status = "disabled";
 642         };
 643
 644         spi2: spi@ff1e0000 {
 645                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 646                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 647                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 648                 clock-names = "spiclk", "apb_pclk";
 649                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 650                 pinctrl-names = "default";
 651                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 652                 #address-cells = <1>;
 653                 #size-cells = <0>;
 654                 status = "disabled";
 655         };
 656
 657         spi4: spi@ff1f0000 {
 658                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 659                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 660                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 661                 clock-names = "spiclk", "apb_pclk";
 662                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 663                 pinctrl-names = "default";
 664                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 665                 #address-cells = <1>;
 666                 #size-cells = <0>;
 667                 status = "disabled";
 668         };
 669
 670         spi5: spi@ff200000 {
 671                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 672                 reg = <0x0 0xff200000 0x0 0x1000>;
 673                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 674                 clock-names = "spiclk", "apb_pclk";
 675                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 676                 pinctrl-names = "default";
 677                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 678                 #address-cells = <1>;
 679                 #size-cells = <0>;
 680                 status = "disabled";
 681         };
 682
 683         thermal_zones: thermal-zones {
 684                 cpu_thermal: cpu {
 685                         polling-delay-passive = <100>;
 686                         polling-delay = <1000>;
 687
 688                         thermal-sensors = <&tsadc 0>;
 689
 690                         trips {
 691                                 cpu_alert0: cpu_alert0 {
 692                                         temperature = <70000>;
 693                                         hysteresis = <2000>;
 694                                         type = "passive";
 695                                 };
 696                                 cpu_alert1: cpu_alert1 {
 697                                         temperature = <75000>;
 698                                         hysteresis = <2000>;
 699                                         type = "passive";
 700                                 };
 701                                 cpu_crit: cpu_crit {
 702                                         temperature = <95000>;
 703                                         hysteresis = <2000>;
 704                                         type = "critical";
 705                                 };
 706                         };
 707
 708                         cooling-maps {
 709                                 map0 {
 710                                         trip = <&cpu_alert0>;
 711                                         cooling-device =
 712                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 713                                 };
 714                                 map1 {
 715                                         trip = <&cpu_alert1>;
 716                                         cooling-device =
 717                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 718                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 719                                 };
 720                         };
 721                 };
 722
 723                 gpu_thermal: gpu {
 724                         polling-delay-passive = <100>;
 725                         polling-delay = <1000>;
 726
 727                         thermal-sensors = <&tsadc 1>;
 728
 729                         trips {
 730                                 gpu_alert0: gpu_alert0 {
 731                                         temperature = <75000>;
 732                                         hysteresis = <2000>;
 733                                         type = "passive";
 734                                 };
 735                                 gpu_crit: gpu_crit {
 736                                         temperature = <95000>;
 737                                         hysteresis = <2000>;
 738                                         type = "critical";
 739                                 };
 740                         };
 741
 742                         cooling-maps {
 743                                 map0 {
 744                                         trip = <&gpu_alert0>;
 745                                         cooling-device =
 746                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 747                                 };
 748                         };
 749                 };
 750         };
 751
 752         tsadc: tsadc@ff260000 {
 753                 compatible = "rockchip,rk3399-tsadc";
 754                 reg = <0x0 0xff260000 0x0 0x100>;
 755                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 756                 assigned-clocks = <&cru SCLK_TSADC>;
 757                 assigned-clock-rates = <750000>;
 758                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 759                 clock-names = "tsadc", "apb_pclk";
 760                 resets = <&cru SRST_TSADC>;
 761                 reset-names = "tsadc-apb";
 762                 rockchip,grf = <&grf>;
 763                 rockchip,hw-tshut-temp = <95000>;
 764                 pinctrl-names = "init", "default", "sleep";
 765                 pinctrl-0 = <&otp_gpio>;
 766                 pinctrl-1 = <&otp_out>;
 767                 pinctrl-2 = <&otp_gpio>;
 768                 #thermal-sensor-cells = <1>;
 769                 status = "disabled";
 770         };
 771
 772         qos_sd: qos@ffa74000 {
 773                 compatible = "syscon";
 774                 reg = <0x0 0xffa74000 0x0 0x20>;
 775         };
 776
 777         qos_emmc: qos@ffa58000 {
 778                 compatible = "syscon";
 779                 reg = <0x0 0xffa58000 0x0 0x20>;
 780         };
 781
 782         qos_gmac: qos@ffa5c000 {
 783                 compatible = "syscon";
 784                 reg = <0x0 0xffa5c000 0x0 0x20>;
 785         };
 786
 787         qos_hdcp: qos@ffa90000 {
 788                 compatible = "syscon";
 789                 reg = <0x0 0xffa90000 0x0 0x20>;
 790         };
 791
 792         qos_iep: qos@ffa98000 {
 793                 compatible = "syscon";
 794                 reg = <0x0 0xffa98000 0x0 0x20>;
 795         };
 796
 797         qos_isp0_m0: qos@ffaa0000 {
 798                 compatible = "syscon";
 799                 reg = <0x0 0xffaa0000 0x0 0x20>;
 800         };
 801
 802         qos_isp0_m1: qos@ffaa0080 {
 803                 compatible = "syscon";
 804                 reg = <0x0 0xffaa0080 0x0 0x20>;
 805         };
 806
 807         qos_isp1_m0: qos@ffaa8000 {
 808                 compatible = "syscon";
 809                 reg = <0x0 0xffaa8000 0x0 0x20>;
 810         };
 811
 812         qos_isp1_m1: qos@ffaa8080 {
 813                 compatible = "syscon";
 814                 reg = <0x0 0xffaa8080 0x0 0x20>;
 815         };
 816
 817         qos_rga_r: qos@ffab0000 {
 818                 compatible = "syscon";
 819                 reg = <0x0 0xffab0000 0x0 0x20>;
 820         };
 821
 822         qos_rga_w: qos@ffab0080 {
 823                 compatible = "syscon";
 824                 reg = <0x0 0xffab0080 0x0 0x20>;
 825         };
 826
 827         qos_video_m0: qos@ffab8000 {
 828                 compatible = "syscon";
 829                 reg = <0x0 0xffab8000 0x0 0x20>;
 830         };
 831
 832         qos_video_m1_r: qos@ffac0000 {
 833                 compatible = "syscon";
 834                 reg = <0x0 0xffac0000 0x0 0x20>;
 835         };
 836
 837         qos_video_m1_w: qos@ffac0080 {
 838                 compatible = "syscon";
 839                 reg = <0x0 0xffac0080 0x0 0x20>;
 840         };
 841
 842         qos_vop_big_r: qos@ffac8000 {
 843                 compatible = "syscon";
 844                 reg = <0x0 0xffac8000 0x0 0x20>;
 845         };
 846
 847         qos_vop_big_w: qos@ffac8080 {
 848                 compatible = "syscon";
 849                 reg = <0x0 0xffac8080 0x0 0x20>;
 850         };
 851
 852         qos_vop_little: qos@ffad0000 {
 853                 compatible = "syscon";
 854                 reg = <0x0 0xffad0000 0x0 0x20>;
 855         };
 856
 857         qos_gpu: qos@ffae0000 {
 858                 compatible = "syscon";
 859                 reg = <0x0 0xffae0000 0x0 0x20>;
 860         };
 861
 862         pmu: power-management@ff310000 {
 863                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 864                 reg = <0x0 0xff310000 0x0 0x1000>;
 865
 866                 /*
 867                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 868                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 869                  * Some of the power domains are grouped together for every
 870                  * voltage domain.
 871                  * The detail contents as below.
 872                  */
 873                 power: power-controller {
 874                         compatible = "rockchip,rk3399-power-controller";
 875                         #power-domain-cells = <1>;
 876                         #address-cells = <1>;
 877                         #size-cells = <0>;
 878
 879                         /* These power domains are grouped by VD_CENTER */
 880                         pd_iep@RK3399_PD_IEP {
 881                                 reg = <RK3399_PD_IEP>;
 882                                 clocks = <&cru ACLK_IEP>,
 883                                          <&cru HCLK_IEP>;
 884                                 pm_qos = <&qos_iep>;
 885                         };
 886                         pd_rga@RK3399_PD_RGA {
 887                                 reg = <RK3399_PD_RGA>;
 888                                 clocks = <&cru ACLK_RGA>,
 889                                          <&cru HCLK_RGA>;
 890                                 pm_qos = <&qos_rga_r>,
 891                                          <&qos_rga_w>;
 892                         };
 893                         pd_vcodec@RK3399_PD_VCODEC {
 894                                 reg = <RK3399_PD_VCODEC>;
 895                                 clocks = <&cru ACLK_VCODEC>,
 896                                          <&cru HCLK_VCODEC>;
 897                                 pm_qos = <&qos_video_m0>;
 898                         };
 899                         pd_vdu@RK3399_PD_VDU {
 900                                 reg = <RK3399_PD_VDU>;
 901                                 clocks = <&cru ACLK_VDU>,
 902                                          <&cru HCLK_VDU>;
 903                                 pm_qos = <&qos_video_m1_r>,
 904                                          <&qos_video_m1_w>;
 905                         };
 906
 907                         /* These power domains are grouped by VD_GPU */
 908                         pd_gpu@RK3399_PD_GPU {
 909                                 reg = <RK3399_PD_GPU>;
 910                                 clocks = <&cru ACLK_GPU>;
 911                                 pm_qos = <&qos_gpu>;
 912                         };
 913
 914                         /* These power domains are grouped by VD_LOGIC */
 915                         pd_emmc@RK3399_PD_EMMC {
 916                                 reg = <RK3399_PD_EMMC>;
 917                                 clocks = <&cru ACLK_EMMC>;
 918                                 pm_qos = <&qos_emmc>;
 919                         };
 920                         pd_gmac@RK3399_PD_GMAC {
 921                                 reg = <RK3399_PD_GMAC>;
 922                                 clocks = <&cru ACLK_GMAC>,
 923                                          <&cru PCLK_GMAC>;
 924                                 pm_qos = <&qos_gmac>;
 925                         };
 926                         pd_sd@RK3399_PD_SD {
 927                                 reg = <RK3399_PD_SD>;
 928                                 clocks = <&cru HCLK_SDMMC>,
 929                                          <&cru SCLK_SDMMC>;
 930                                 pm_qos = <&qos_sd>;
 931                         };
 932                         pd_vio@RK3399_PD_VIO {
 933                                 reg = <RK3399_PD_VIO>;
 934                                 #address-cells = <1>;
 935                                 #size-cells = <0>;
 936
 937                                 pd_hdcp@RK3399_PD_HDCP {
 938                                         reg = <RK3399_PD_HDCP>;
 939                                         clocks = <&cru ACLK_HDCP>,
 940                                                  <&cru HCLK_HDCP>,
 941                                                  <&cru PCLK_HDCP>;
 942                                         pm_qos = <&qos_hdcp>;
 943                                 };
 944                                 pd_isp0@RK3399_PD_ISP0 {
 945                                         reg = <RK3399_PD_ISP0>;
 946                                         clocks = <&cru ACLK_ISP0>,
 947                                                  <&cru HCLK_ISP0>;
 948                                         pm_qos = <&qos_isp0_m0>,
 949                                                  <&qos_isp0_m1>;
 950                                 };
 951                                 pd_isp1@RK3399_PD_ISP1 {
 952                                         reg = <RK3399_PD_ISP1>;
 953                                         clocks = <&cru ACLK_ISP1>,
 954                                                  <&cru HCLK_ISP1>;
 955                                         pm_qos = <&qos_isp1_m0>,
 956                                                  <&qos_isp1_m1>;
 957                                 };
 958                                 pd_tcpc0@RK3399_PD_TCPC0 {
 959                                         reg = <RK3399_PD_TCPD0>;
 960                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
 961                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
 962                                 };
 963                                 pd_tcpc1@RK3399_PD_TCPC1 {
 964                                         reg = <RK3399_PD_TCPD1>;
 965                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
 966                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
 967                                 };
 968                                 pd_vo@RK3399_PD_VO {
 969                                         reg = <RK3399_PD_VO>;
 970                                         #address-cells = <1>;
 971                                         #size-cells = <0>;
 972
 973                                         pd_vopb@RK3399_PD_VOPB {
 974                                                 reg = <RK3399_PD_VOPB>;
 975                                                 clocks = <&cru ACLK_VOP0>,
 976                                                          <&cru HCLK_VOP0>;
 977                                                 pm_qos = <&qos_vop_big_r>,
 978                                                          <&qos_vop_big_w>;
 979                                         };
 980                                         pd_vopl@RK3399_PD_VOPL {
 981                                                 reg = <RK3399_PD_VOPL>;
 982                                                 clocks = <&cru ACLK_VOP1>,
 983                                                          <&cru HCLK_VOP1>;
 984                                                 pm_qos = <&qos_vop_little>;
 985                                         };
 986                                 };
 987                         };
 988                 };
 989         };
 990
 991         pmugrf: syscon@ff320000 {
 992                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 993                 reg = <0x0 0xff320000 0x0 0x1000>;
 994                 #address-cells = <1>;
 995                 #size-cells = <1>;
 996
 997                 pmu_io_domains: io-domains {
 998                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
 999                         status = "disabled";
1000                 };
1001         };
1002
1003         spi3: spi@ff350000 {
1004                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1005                 reg = <0x0 0xff350000 0x0 0x1000>;
1006                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1007                 clock-names = "spiclk", "apb_pclk";
1008                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1009                 pinctrl-names = "default";
1010                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1011                 #address-cells = <1>;
1012                 #size-cells = <0>;
1013                 status = "disabled";
1014         };
1015
1016         uart4: serial@ff370000 {
1017                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1018                 reg = <0x0 0xff370000 0x0 0x100>;
1019                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1020                 clock-names = "baudclk", "apb_pclk";
1021                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1022                 reg-shift = <2>;
1023                 reg-io-width = <4>;
1024                 pinctrl-names = "default";
1025                 pinctrl-0 = <&uart4_xfer>;
1026                 status = "disabled";
1027         };
1028
1029         i2c0: i2c@ff3c0000 {
1030                 compatible = "rockchip,rk3399-i2c";
1031                 reg = <0x0 0xff3c0000 0x0 0x1000>;
1032                 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1033                 assigned-clock-rates = <200000000>;
1034                 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1035                 clock-names = "i2c", "pclk";
1036                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1037                 pinctrl-names = "default";
1038                 pinctrl-0 = <&i2c0_xfer>;
1039                 #address-cells = <1>;
1040                 #size-cells = <0>;
1041                 status = "disabled";
1042         };
1043
1044         i2c4: i2c@ff3d0000 {
1045                 compatible = "rockchip,rk3399-i2c";
1046                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1047                 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1048                 assigned-clock-rates = <200000000>;
1049                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1050                 clock-names = "i2c", "pclk";
1051                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1052                 pinctrl-names = "default";
1053                 pinctrl-0 = <&i2c4_xfer>;
1054                 #address-cells = <1>;
1055                 #size-cells = <0>;
1056                 status = "disabled";
1057         };
1058
1059         i2c8: i2c@ff3e0000 {
1060                 compatible = "rockchip,rk3399-i2c";
1061                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1062                 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1063                 assigned-clock-rates = <200000000>;
1064                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1065                 clock-names = "i2c", "pclk";
1066                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1067                 pinctrl-names = "default";
1068                 pinctrl-0 = <&i2c8_xfer>;
1069                 #address-cells = <1>;
1070                 #size-cells = <0>;
1071                 status = "disabled";
1072         };
1073
1074         pwm0: pwm@ff420000 {
1075                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1076                 reg = <0x0 0xff420000 0x0 0x10>;
1077                 #pwm-cells = <3>;
1078                 pinctrl-names = "default";
1079                 pinctrl-0 = <&pwm0_pin>;
1080                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1081                 clock-names = "pwm";
1082                 status = "disabled";
1083         };
1084
1085         pwm1: pwm@ff420010 {
1086                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1087                 reg = <0x0 0xff420010 0x0 0x10>;
1088                 #pwm-cells = <3>;
1089                 pinctrl-names = "default";
1090                 pinctrl-0 = <&pwm1_pin>;
1091                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1092                 clock-names = "pwm";
1093                 status = "disabled";
1094         };
1095
1096         pwm2: pwm@ff420020 {
1097                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1098                 reg = <0x0 0xff420020 0x0 0x10>;
1099                 #pwm-cells = <3>;
1100                 pinctrl-names = "default";
1101                 pinctrl-0 = <&pwm2_pin>;
1102                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1103                 clock-names = "pwm";
1104                 status = "disabled";
1105         };
1106
1107         pwm3: pwm@ff420030 {
1108                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1109                 reg = <0x0 0xff420030 0x0 0x10>;
1110                 #pwm-cells = <3>;
1111                 pinctrl-names = "default";
1112                 pinctrl-0 = <&pwm3a_pin>;
1113                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1114                 clock-names = "pwm";
1115                 status = "disabled";
1116         };
1117
1118         efuse0: efuse@ff690000 {
1119                 compatible = "rockchip,rk3399-efuse";
1120                 reg = <0x0 0xff690000 0x0 0x80>;
1121                 #address-cells = <1>;
1122                 #size-cells = <1>;
1123                 clocks = <&cru PCLK_EFUSE1024NS>;
1124                 clock-names = "pclk_efuse";
1125
1126                 /* Data cells */
1127                 cpu_id: cpu-id@7 {
1128                         reg = <0x07 0x10>;
1129                 };
1130                 cpub_leakage: cpu-leakage@17 {
1131                         reg = <0x17 0x1>;
1132                 };
1133                 gpu_leakage: gpu-leakage@18 {
1134                         reg = <0x18 0x1>;
1135                 };
1136                 center_leakage: center-leakage@19 {
1137                         reg = <0x19 0x1>;
1138                 };
1139                 cpul_leakage: cpu-leakage@1a {
1140                         reg = <0x1a 0x1>;
1141                 };
1142                 logic_leakage: logic-leakage@1b {
1143                         reg = <0x1b 0x1>;
1144                 };
1145                 wafer_info: wafer-info@1c {
1146                         reg = <0x1c 0x1>;
1147                 };
1148         };
1149
1150         pmucru: pmu-clock-controller@ff750000 {
1151                 compatible = "rockchip,rk3399-pmucru";
1152                 reg = <0x0 0xff750000 0x0 0x1000>;
1153                 rockchip,grf = <&pmugrf>;
1154                 #clock-cells = <1>;
1155                 #reset-cells = <1>;
1156                 assigned-clocks = <&pmucru PLL_PPLL>;
1157                 assigned-clock-rates = <676000000>;
1158         };
1159
1160         cru: clock-controller@ff760000 {
1161                 compatible = "rockchip,rk3399-cru";
1162                 reg = <0x0 0xff760000 0x0 0x1000>;
1163                 rockchip,grf = <&grf>;
1164                 #clock-cells = <1>;
1165                 #reset-cells = <1>;
1166                 assigned-clocks =
1167                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1168                         <&cru PLL_NPLL>,
1169                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1170                         <&cru PCLK_PERIHP>,
1171                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1172                         <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1173                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1174                 assigned-clock-rates =
1175                          <594000000>,  <800000000>,
1176                         <1000000000>,
1177                          <150000000>,   <75000000>,
1178                           <37500000>,
1179                          <100000000>,  <100000000>,
1180                           <50000000>, <600000000>,
1181                          <100000000>,   <50000000>;
1182         };
1183
1184         grf: syscon@ff770000 {
1185                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1186                 reg = <0x0 0xff770000 0x0 0x10000>;
1187                 #address-cells = <1>;
1188                 #size-cells = <1>;
1189
1190                 io_domains: io-domains {
1191                         compatible = "rockchip,rk3399-io-voltage-domain";
1192                         status = "disabled";
1193                 };
1194
1195                 u2phy0: usb2-phy@e450 {
1196                         compatible = "rockchip,rk3399-usb2phy";
1197                         reg = <0xe450 0x10>;
1198                         clocks = <&cru SCLK_USB2PHY0_REF>;
1199                         clock-names = "phyclk";
1200                         #clock-cells = <0>;
1201                         clock-output-names = "clk_usbphy0_480m";
1202                         status = "disabled";
1203
1204                         u2phy0_host: host-port {
1205                                 #phy-cells = <0>;
1206                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1207                                 interrupt-names = "linestate";
1208                                 status = "disabled";
1209                         };
1210
1211                         u2phy0_otg: otg-port {
1212                                 #phy-cells = <0>;
1213                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1214                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1215                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1216                                 interrupt-names = "otg-bvalid", "otg-id",
1217                                                   "linestate";
1218                                 status = "disabled";
1219                         };
1220                 };
1221
1222                 u2phy1: usb2-phy@e460 {
1223                         compatible = "rockchip,rk3399-usb2phy";
1224                         reg = <0xe460 0x10>;
1225                         clocks = <&cru SCLK_USB2PHY1_REF>;
1226                         clock-names = "phyclk";
1227                         #clock-cells = <0>;
1228                         clock-output-names = "clk_usbphy1_480m";
1229                         status = "disabled";
1230
1231                         u2phy1_host: host-port {
1232                                 #phy-cells = <0>;
1233                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1234                                 interrupt-names = "linestate";
1235                                 status = "disabled";
1236                         };
1237
1238                         u2phy1_otg: otg-port {
1239                                 #phy-cells = <0>;
1240                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1241                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1242                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1243                                 interrupt-names = "otg-bvalid", "otg-id",
1244                                                   "linestate";
1245                                 status = "disabled";
1246                         };
1247                 };
1248
1249                 emmc_phy: phy@f780 {
1250                         compatible = "rockchip,rk3399-emmc-phy";
1251                         reg = <0xf780 0x24>;
1252                         clocks = <&sdhci>;
1253                         clock-names = "emmcclk";
1254                         #phy-cells = <0>;
1255                         status = "disabled";
1256                 };
1257
1258                 pcie_phy: pcie-phy {
1259                         compatible = "rockchip,rk3399-pcie-phy";
1260                         clocks = <&cru SCLK_PCIEPHY_REF>;
1261                         clock-names = "refclk";
1262                         #phy-cells = <0>;
1263                         resets = <&cru SRST_PCIEPHY>;
1264                         reset-names = "phy";
1265                         status = "disabled";
1266                 };
1267         };
1268
1269         tcphy0: phy@ff7c0000 {
1270                 compatible = "rockchip,rk3399-typec-phy";
1271                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1272                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1273                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1274                 clock-names = "tcpdcore", "tcpdphy-ref";
1275                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1276                 assigned-clock-rates = <50000000>;
1277                 power-domains = <&power RK3399_PD_TCPD0>;
1278                 resets = <&cru SRST_UPHY0>,
1279                          <&cru SRST_UPHY0_PIPE_L00>,
1280                          <&cru SRST_P_UPHY0_TCPHY>;
1281                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1282                 rockchip,grf = <&grf>;
1283                 rockchip,typec-conn-dir = <0xe580 0 16>;
1284                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1285                 rockchip,external-psm = <0xe588 14 30>;
1286                 rockchip,pipe-status = <0xe5c0 0 0>;
1287                 status = "disabled";
1288
1289                 tcphy0_dp: dp-port {
1290                         #phy-cells = <0>;
1291                 };
1292
1293                 tcphy0_usb3: usb3-port {
1294                         #phy-cells = <0>;
1295                 };
1296         };
1297
1298         tcphy1: phy@ff800000 {
1299                 compatible = "rockchip,rk3399-typec-phy";
1300                 reg = <0x0 0xff800000 0x0 0x40000>;
1301                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1302                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1303                 clock-names = "tcpdcore", "tcpdphy-ref";
1304                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1305                 assigned-clock-rates = <50000000>;
1306                 power-domains = <&power RK3399_PD_TCPD1>;
1307                 resets = <&cru SRST_UPHY1>,
1308                          <&cru SRST_UPHY1_PIPE_L00>,
1309                          <&cru SRST_P_UPHY1_TCPHY>;
1310                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1311                 rockchip,grf = <&grf>;
1312                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1313                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1314                 rockchip,external-psm = <0xe594 14 30>;
1315                 rockchip,pipe-status = <0xe5c0 16 16>;
1316                 status = "disabled";
1317
1318                 tcphy1_dp: dp-port {
1319                         #phy-cells = <0>;
1320                 };
1321
1322                 tcphy1_usb3: usb3-port {
1323                         #phy-cells = <0>;
1324                 };
1325         };
1326
1327         watchdog@ff848000 {
1328                 compatible = "snps,dw-wdt";
1329                 reg = <0x0 0xff848000 0x0 0x100>;
1330                 clocks = <&cru PCLK_WDT>;
1331                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1332         };
1333
1334         rktimer: rktimer@ff850000 {
1335                 compatible = "rockchip,rk3399-timer";
1336                 reg = <0x0 0xff850000 0x0 0x1000>;
1337                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1338                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1339                 clock-names = "pclk", "timer";
1340         };
1341
1342         spdif: spdif@ff870000 {
1343                 compatible = "rockchip,rk3399-spdif";
1344                 reg = <0x0 0xff870000 0x0 0x1000>;
1345                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1346                 dmas = <&dmac_bus 7>;
1347                 dma-names = "tx";
1348                 clock-names = "mclk", "hclk";
1349                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1350                 pinctrl-names = "default";
1351                 pinctrl-0 = <&spdif_bus>;
1352                 status = "disabled";
1353         };
1354
1355         i2s0: i2s@ff880000 {
1356                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1357                 reg = <0x0 0xff880000 0x0 0x1000>;
1358                 rockchip,grf = <&grf>;
1359                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1360                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1361                 dma-names = "tx", "rx";
1362                 clock-names = "i2s_clk", "i2s_hclk";
1363                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1364                 pinctrl-names = "default";
1365                 pinctrl-0 = <&i2s0_8ch_bus>;
1366                 status = "disabled";
1367         };
1368
1369         i2s1: i2s@ff890000 {
1370                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1371                 reg = <0x0 0xff890000 0x0 0x1000>;
1372                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1373                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1374                 dma-names = "tx", "rx";
1375                 clock-names = "i2s_clk", "i2s_hclk";
1376                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1377                 pinctrl-names = "default";
1378                 pinctrl-0 = <&i2s1_2ch_bus>;
1379                 status = "disabled";
1380         };
1381
1382         i2s2: i2s@ff8a0000 {
1383                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1384                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1385                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1386                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1387                 dma-names = "tx", "rx";
1388                 clock-names = "i2s_clk", "i2s_hclk";
1389                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1390                 status = "disabled";
1391         };
1392
1393         pinctrl: pinctrl {
1394                 compatible = "rockchip,rk3399-pinctrl";
1395                 rockchip,grf = <&grf>;
1396                 rockchip,pmu = <&pmugrf>;
1397                 #address-cells = <2>;
1398                 #size-cells = <2>;
1399                 ranges;
1400
1401                 gpio0: gpio0@ff720000 {
1402                         compatible = "rockchip,gpio-bank";
1403                         reg = <0x0 0xff720000 0x0 0x100>;
1404                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1405                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1406
1407                         gpio-controller;
1408                         #gpio-cells = <0x2>;
1409
1410                         interrupt-controller;
1411                         #interrupt-cells = <0x2>;
1412                 };
1413
1414                 gpio1: gpio1@ff730000 {
1415                         compatible = "rockchip,gpio-bank";
1416                         reg = <0x0 0xff730000 0x0 0x100>;
1417                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1418                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1419
1420                         gpio-controller;
1421                         #gpio-cells = <0x2>;
1422
1423                         interrupt-controller;
1424                         #interrupt-cells = <0x2>;
1425                 };
1426
1427                 gpio2: gpio2@ff780000 {
1428                         compatible = "rockchip,gpio-bank";
1429                         reg = <0x0 0xff780000 0x0 0x100>;
1430                         clocks = <&cru PCLK_GPIO2>;
1431                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1432
1433                         gpio-controller;
1434                         #gpio-cells = <0x2>;
1435
1436                         interrupt-controller;
1437                         #interrupt-cells = <0x2>;
1438                 };
1439
1440                 gpio3: gpio3@ff788000 {
1441                         compatible = "rockchip,gpio-bank";
1442                         reg = <0x0 0xff788000 0x0 0x100>;
1443                         clocks = <&cru PCLK_GPIO3>;
1444                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1445
1446                         gpio-controller;
1447                         #gpio-cells = <0x2>;
1448
1449                         interrupt-controller;
1450                         #interrupt-cells = <0x2>;
1451                 };
1452
1453                 gpio4: gpio4@ff790000 {
1454                         compatible = "rockchip,gpio-bank";
1455                         reg = <0x0 0xff790000 0x0 0x100>;
1456                         clocks = <&cru PCLK_GPIO4>;
1457                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1458
1459                         gpio-controller;
1460                         #gpio-cells = <0x2>;
1461
1462                         interrupt-controller;
1463                         #interrupt-cells = <0x2>;
1464                 };
1465
1466                 pcfg_pull_up: pcfg-pull-up {
1467                         bias-pull-up;
1468                 };
1469
1470                 pcfg_pull_down: pcfg-pull-down {
1471                         bias-pull-down;
1472                 };
1473
1474                 pcfg_pull_none: pcfg-pull-none {
1475                         bias-disable;
1476                 };
1477
1478                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1479                         bias-disable;
1480                         drive-strength = <12>;
1481                 };
1482
1483                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1484                         bias-pull-up;
1485                         drive-strength = <8>;
1486                 };
1487
1488                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1489                         bias-pull-down;
1490                         drive-strength = <4>;
1491                 };
1492
1493                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1494                         bias-pull-up;
1495                         drive-strength = <2>;
1496                 };
1497
1498                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1499                         bias-pull-down;
1500                         drive-strength = <12>;
1501                 };
1502
1503                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1504                         bias-disable;
1505                         drive-strength = <13>;
1506                 };
1507
1508                 clock {
1509                         clk_32k: clk-32k {
1510                                 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
1511                         };
1512                 };
1513
1514                 edp {
1515                         edp_hpd: edp-hpd {
1516                                 rockchip,pins =
1517                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
1518                         };
1519                 };
1520
1521                 gmac {
1522                         rgmii_pins: rgmii-pins {
1523                                 rockchip,pins =
1524                                         /* mac_txclk */
1525                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1526                                         /* mac_rxclk */
1527                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1528                                         /* mac_mdio */
1529                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1530                                         /* mac_txen */
1531                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1532                                         /* mac_clk */
1533                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1534                                         /* mac_rxdv */
1535                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1536                                         /* mac_mdc */
1537                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1538                                         /* mac_rxd1 */
1539                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1540                                         /* mac_rxd0 */
1541                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1542                                         /* mac_txd1 */
1543                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1544                                         /* mac_txd0 */
1545                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1546                                         /* mac_rxd3 */
1547                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1548                                         /* mac_rxd2 */
1549                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1550                                         /* mac_txd3 */
1551                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1552                                         /* mac_txd2 */
1553                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1554                         };
1555
1556                         rmii_pins: rmii-pins {
1557                                 rockchip,pins =
1558                                         /* mac_mdio */
1559                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1560                                         /* mac_txen */
1561                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1562                                         /* mac_clk */
1563                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1564                                         /* mac_rxer */
1565                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1566                                         /* mac_rxdv */
1567                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1568                                         /* mac_mdc */
1569                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1570                                         /* mac_rxd1 */
1571                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1572                                         /* mac_rxd0 */
1573                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1574                                         /* mac_txd1 */
1575                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1576                                         /* mac_txd0 */
1577                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1578                         };
1579                 };
1580
1581                 i2c0 {
1582                         i2c0_xfer: i2c0-xfer {
1583                                 rockchip,pins =
1584                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1585                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1586                         };
1587                 };
1588
1589                 i2c1 {
1590                         i2c1_xfer: i2c1-xfer {
1591                                 rockchip,pins =
1592                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1593                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1594                         };
1595                 };
1596
1597                 i2c2 {
1598                         i2c2_xfer: i2c2-xfer {
1599                                 rockchip,pins =
1600                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1601                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1602                         };
1603                 };
1604
1605                 i2c3 {
1606                         i2c3_xfer: i2c3-xfer {
1607                                 rockchip,pins =
1608                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1609                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1610                         };
1611                 };
1612
1613                 i2c4 {
1614                         i2c4_xfer: i2c4-xfer {
1615                                 rockchip,pins =
1616                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1617                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1618                         };
1619                 };
1620
1621                 i2c5 {
1622                         i2c5_xfer: i2c5-xfer {
1623                                 rockchip,pins =
1624                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1625                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1626                         };
1627                 };
1628
1629                 i2c6 {
1630                         i2c6_xfer: i2c6-xfer {
1631                                 rockchip,pins =
1632                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1633                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1634                         };
1635                 };
1636
1637                 i2c7 {
1638                         i2c7_xfer: i2c7-xfer {
1639                                 rockchip,pins =
1640                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1641                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1642                         };
1643                 };
1644
1645                 i2c8 {
1646                         i2c8_xfer: i2c8-xfer {
1647                                 rockchip,pins =
1648                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1649                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1650                         };
1651                 };
1652
1653                 i2s0 {
1654                         i2s0_8ch_bus: i2s0-8ch-bus {
1655                                 rockchip,pins =
1656                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1657                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1658                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1659                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1660                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1661                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1662                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1663                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1664                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1665                         };
1666                 };
1667
1668                 i2s1 {
1669                         i2s1_2ch_bus: i2s1-2ch-bus {
1670                                 rockchip,pins =
1671                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1672                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1673                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1674                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1675                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1676                         };
1677                 };
1678
1679                 sleep {
1680                         ap_pwroff: ap-pwroff {
1681                                 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
1682                         };
1683
1684                         ddrio_pwroff: ddrio-pwroff {
1685                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1686                         };
1687                 };
1688
1689                 spdif {
1690                         spdif_bus: spdif-bus {
1691                                 rockchip,pins =
1692                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1693                         };
1694                 };
1695
1696                 spi0 {
1697                         spi0_clk: spi0-clk {
1698                                 rockchip,pins =
1699                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1700                         };
1701                         spi0_cs0: spi0-cs0 {
1702                                 rockchip,pins =
1703                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1704                         };
1705                         spi0_cs1: spi0-cs1 {
1706                                 rockchip,pins =
1707                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1708                         };
1709                         spi0_tx: spi0-tx {
1710                                 rockchip,pins =
1711                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1712                         };
1713                         spi0_rx: spi0-rx {
1714                                 rockchip,pins =
1715                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1716                         };
1717                 };
1718
1719                 spi1 {
1720                         spi1_clk: spi1-clk {
1721                                 rockchip,pins =
1722                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1723                         };
1724                         spi1_cs0: spi1-cs0 {
1725                                 rockchip,pins =
1726                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1727                         };
1728                         spi1_rx: spi1-rx {
1729                                 rockchip,pins =
1730                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1731                         };
1732                         spi1_tx: spi1-tx {
1733                                 rockchip,pins =
1734                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1735                         };
1736                 };
1737
1738                 spi2 {
1739                         spi2_clk: spi2-clk {
1740                                 rockchip,pins =
1741                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1742                         };
1743                         spi2_cs0: spi2-cs0 {
1744                                 rockchip,pins =
1745                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1746                         };
1747                         spi2_rx: spi2-rx {
1748                                 rockchip,pins =
1749                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1750                         };
1751                         spi2_tx: spi2-tx {
1752                                 rockchip,pins =
1753                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1754                         };
1755                 };
1756
1757                 spi3 {
1758                         spi3_clk: spi3-clk {
1759                                 rockchip,pins =
1760                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1761                         };
1762                         spi3_cs0: spi3-cs0 {
1763                                 rockchip,pins =
1764                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1765                         };
1766                         spi3_rx: spi3-rx {
1767                                 rockchip,pins =
1768                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1769                         };
1770                         spi3_tx: spi3-tx {
1771                                 rockchip,pins =
1772                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1773                         };
1774                 };
1775
1776                 spi4 {
1777                         spi4_clk: spi4-clk {
1778                                 rockchip,pins =
1779                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1780                         };
1781                         spi4_cs0: spi4-cs0 {
1782                                 rockchip,pins =
1783                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1784                         };
1785                         spi4_rx: spi4-rx {
1786                                 rockchip,pins =
1787                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1788                         };
1789                         spi4_tx: spi4-tx {
1790                                 rockchip,pins =
1791                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1792                         };
1793                 };
1794
1795                 spi5 {
1796                         spi5_clk: spi5-clk {
1797                                 rockchip,pins =
1798                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1799                         };
1800                         spi5_cs0: spi5-cs0 {
1801                                 rockchip,pins =
1802                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1803                         };
1804                         spi5_rx: spi5-rx {
1805                                 rockchip,pins =
1806                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1807                         };
1808                         spi5_tx: spi5-tx {
1809                                 rockchip,pins =
1810                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1811                         };
1812                 };
1813
1814                 tsadc {
1815                         otp_gpio: otp-gpio {
1816                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1817                         };
1818
1819                         otp_out: otp-out {
1820                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1821                         };
1822                 };
1823
1824                 uart0 {
1825                         uart0_xfer: uart0-xfer {
1826                                 rockchip,pins =
1827                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1828                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1829                         };
1830
1831                         uart0_cts: uart0-cts {
1832                                 rockchip,pins =
1833                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1834                         };
1835
1836                         uart0_rts: uart0-rts {
1837                                 rockchip,pins =
1838                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1839                         };
1840                 };
1841
1842                 uart1 {
1843                         uart1_xfer: uart1-xfer {
1844                                 rockchip,pins =
1845                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1846                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1847                         };
1848                 };
1849
1850                 uart2a {
1851                         uart2a_xfer: uart2a-xfer {
1852                                 rockchip,pins =
1853                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1854                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1855                         };
1856                 };
1857
1858                 uart2b {
1859                         uart2b_xfer: uart2b-xfer {
1860                                 rockchip,pins =
1861                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1862                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1863                         };
1864                 };
1865
1866                 uart2c {
1867                         uart2c_xfer: uart2c-xfer {
1868                                 rockchip,pins =
1869                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1870                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1871                         };
1872                 };
1873
1874                 uart3 {
1875                         uart3_xfer: uart3-xfer {
1876                                 rockchip,pins =
1877                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1878                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1879                         };
1880
1881                         uart3_cts: uart3-cts {
1882                                 rockchip,pins =
1883                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1884                         };
1885
1886                         uart3_rts: uart3-rts {
1887                                 rockchip,pins =
1888                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1889                         };
1890                 };
1891
1892                 uart4 {
1893                         uart4_xfer: uart4-xfer {
1894                                 rockchip,pins =
1895                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1896                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1897                         };
1898                 };
1899
1900                 uarthdcp {
1901                         uarthdcp_xfer: uarthdcp-xfer {
1902                                 rockchip,pins =
1903                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1904                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1905                         };
1906                 };
1907
1908                 pwm0 {
1909                         pwm0_pin: pwm0-pin {
1910                                 rockchip,pins =
1911                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1912                         };
1913
1914                         vop0_pwm_pin: vop0-pwm-pin {
1915                                 rockchip,pins =
1916                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1917                         };
1918                 };
1919
1920                 pwm1 {
1921                         pwm1_pin: pwm1-pin {
1922                                 rockchip,pins =
1923                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1924                         };
1925
1926                         vop1_pwm_pin: vop1-pwm-pin {
1927                                 rockchip,pins =
1928                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1929                         };
1930                 };
1931
1932                 pwm2 {
1933                         pwm2_pin: pwm2-pin {
1934                                 rockchip,pins =
1935                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1936                         };
1937                 };
1938
1939                 pwm3a {
1940                         pwm3a_pin: pwm3a-pin {
1941                                 rockchip,pins =
1942                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1943                         };
1944                 };
1945
1946                 pwm3b {
1947                         pwm3b_pin: pwm3b-pin {
1948                                 rockchip,pins =
1949                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1950                         };
1951                 };
1952
1953                 pcie {
1954                         pcie_clkreqn: pci-clkreqn {
1955                                 rockchip,pins =
1956                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
1957                         };
1958
1959                         pcie_clkreqnb: pci-clkreqnb {
1960                                 rockchip,pins =
1961                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
1962                         };
1963                 };
1964
1965         };
1966 };