src/arm64/ti/k3-am62-mcu.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for AM625 SoC Family MCU Domain peripherals
   4  *
   5  * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 &cbass_mcu {
   9         mcu_pmx0: pinctrl@4084000 {
  10                 compatible = "pinctrl-single";
  11                 reg = <0x00 0x04084000 0x00 0x88>;
  12                 #pinctrl-cells = <1>;
  13                 pinctrl-single,register-width = <32>;
  14                 pinctrl-single,function-mask = <0xffffffff>;
  15         };
  16
  17         /*
  18          * The MCU domain timer interrupts are routed only to the ESM module,
  19          * and not currently available for Linux. The MCU domain timers are
  20          * of limited use without interrupts, and likely reserved by the ESM.
  21          */
  22         mcu_timer0: timer@4800000 {
  23                 compatible = "ti,am654-timer";
  24                 reg = <0x00 0x4800000 0x00 0x400>;
  25                 clocks = <&k3_clks 35 2>;
  26                 clock-names = "fck";
  27                 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
  28                 ti,timer-pwm;
  29                 status = "reserved";
  30         };
  31
  32         mcu_timer1: timer@4810000 {
  33                 compatible = "ti,am654-timer";
  34                 reg = <0x00 0x4810000 0x00 0x400>;
  35                 clocks = <&k3_clks 48 2>;
  36                 clock-names = "fck";
  37                 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
  38                 ti,timer-pwm;
  39                 status = "reserved";
  40         };
  41
  42         mcu_timer2: timer@4820000 {
  43                 compatible = "ti,am654-timer";
  44                 reg = <0x00 0x4820000 0x00 0x400>;
  45                 clocks = <&k3_clks 49 2>;
  46                 clock-names = "fck";
  47                 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
  48                 ti,timer-pwm;
  49                 status = "reserved";
  50         };
  51
  52         mcu_timer3: timer@4830000 {
  53                 compatible = "ti,am654-timer";
  54                 reg = <0x00 0x4830000 0x00 0x400>;
  55                 clocks = <&k3_clks 50 2>;
  56                 clock-names = "fck";
  57                 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
  58                 ti,timer-pwm;
  59                 status = "reserved";
  60         };
  61
  62         mcu_uart0: serial@4a00000 {
  63                 compatible = "ti,am64-uart", "ti,am654-uart";
  64                 reg = <0x00 0x04a00000 0x00 0x100>;
  65                 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
  66                 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
  67                 clocks = <&k3_clks 149 0>;
  68                 clock-names = "fclk";
  69                 status = "disabled";
  70         };
  71
  72         mcu_i2c0: i2c@4900000 {
  73                 compatible = "ti,am64-i2c", "ti,omap4-i2c";
  74                 reg = <0x00 0x04900000 0x00 0x100>;
  75                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
  76                 #address-cells = <1>;
  77                 #size-cells = <0>;
  78                 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
  79                 clocks = <&k3_clks 106 2>;
  80                 clock-names = "fck";
  81                 status = "disabled";
  82         };
  83
  84         mcu_spi0: spi@4b00000 {
  85                 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
  86                 reg = <0x00 0x04b00000 0x00 0x400>;
  87                 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
  88                 #address-cells = <1>;
  89                 #size-cells = <0>;
  90                 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
  91                 clocks = <&k3_clks 147 0>;
  92                 status = "disabled";
  93         };
  94
  95         mcu_spi1: spi@4b10000 {
  96                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
  97                 reg = <0x00 0x04b10000 0x00 0x400>;
  98                 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
  99                 #address-cells = <1>;
 100                 #size-cells = <0>;
 101                 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
 102                 clocks = <&k3_clks 148 0>;
 103                 status = "disabled";
 104         };
 105
 106         mcu_gpio_intr: interrupt-controller@4210000 {
 107                 compatible = "ti,sci-intr";
 108                 reg = <0x00 0x04210000 0x00 0x200>;
 109                 ti,intr-trigger-type = <1>;
 110                 interrupt-controller;
 111                 interrupt-parent = <&gic500>;
 112                 #interrupt-cells = <1>;
 113                 ti,sci = <&dmsc>;
 114                 ti,sci-dev-id = <5>;
 115                 ti,interrupt-ranges = <0 104 4>;
 116         };
 117
 118         mcu_gpio0: gpio@4201000 {
 119                 compatible = "ti,am64-gpio", "ti,keystone-gpio";
 120                 reg = <0x00 0x4201000 0x00 0x100>;
 121                 gpio-controller;
 122                 #gpio-cells = <2>;
 123                 interrupt-parent = <&mcu_gpio_intr>;
 124                 interrupts = <30>, <31>;
 125                 interrupt-controller;
 126                 #interrupt-cells = <2>;
 127                 ti,ngpio = <24>;
 128                 ti,davinci-gpio-unbanked = <0>;
 129                 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
 130                 clocks = <&k3_clks 79 0>;
 131                 clock-names = "gpio";
 132         };
 133 };