1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/mux/ti-serdes.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include "k3-am642.dtsi"
15 compatible = "ti,am642-sk", "ti,am642";
16 model = "Texas Instruments AM642 SK";
19 stdout-path = "serial2:115200n8";
20 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
24 device_type = "memory";
26 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
35 secure_ddr: optee@9e800000 {
36 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
41 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
42 compatible = "shared-dma-pool";
43 reg = <0x00 0xa0000000 0x00 0x100000>;
47 main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
48 compatible = "shared-dma-pool";
49 reg = <0x00 0xa0100000 0x00 0xf00000>;
53 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
54 compatible = "shared-dma-pool";
55 reg = <0x00 0xa1000000 0x00 0x100000>;
59 main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
60 compatible = "shared-dma-pool";
61 reg = <0x00 0xa1100000 0x00 0xf00000>;
65 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
66 compatible = "shared-dma-pool";
67 reg = <0x00 0xa2000000 0x00 0x100000>;
71 main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
72 compatible = "shared-dma-pool";
73 reg = <0x00 0xa2100000 0x00 0xf00000>;
77 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
78 compatible = "shared-dma-pool";
79 reg = <0x00 0xa3000000 0x00 0x100000>;
83 main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
84 compatible = "shared-dma-pool";
85 reg = <0x00 0xa3100000 0x00 0xf00000>;
89 rtos_ipc_memory_region: ipc-memories@a5000000 {
90 reg = <0x00 0xa5000000 0x00 0x00800000>;
96 vusb_main: fixed-regulator-vusb-main5v0 {
97 /* USB MAIN INPUT 5V DC */
98 compatible = "regulator-fixed";
99 regulator-name = "vusb_main5v0";
100 regulator-min-microvolt = <5000000>;
101 regulator-max-microvolt = <5000000>;
106 vcc_3v3_sys: fixedregulator-vcc-3v3-sys {
107 /* output of LP8733xx */
108 compatible = "regulator-fixed";
109 regulator-name = "vcc_3v3_sys";
110 regulator-min-microvolt = <3300000>;
111 regulator-max-microvolt = <3300000>;
112 vin-supply = <&vusb_main>;
117 vdd_mmc1: fixed-regulator-sd {
119 compatible = "regulator-fixed";
120 regulator-name = "vdd_mmc1";
121 regulator-min-microvolt = <3300000>;
122 regulator-max-microvolt = <3300000>;
125 vin-supply = <&vcc_3v3_sys>;
126 gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
131 main_mmc1_pins_default: main-mmc1-pins-default {
132 pinctrl-single,pins = <
133 AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */
134 AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
135 AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */
136 AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */
137 AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */
138 AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */
139 AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */
140 AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */
144 main_usb0_pins_default: main-usb0-pins-default {
145 pinctrl-single,pins = <
146 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
150 main_i2c1_pins_default: main-i2c1-pins-default {
151 pinctrl-single,pins = <
152 AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
153 AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
157 mdio1_pins_default: mdio1-pins-default {
158 pinctrl-single,pins = <
159 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
160 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
164 rgmii1_pins_default: rgmii1-pins-default {
165 pinctrl-single,pins = <
166 AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
167 AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
168 AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
169 AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
170 AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
171 AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
172 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
173 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
174 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
175 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
176 AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
177 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
181 rgmii2_pins_default: rgmii2-pins-default {
182 pinctrl-single,pins = <
183 AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
184 AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
185 AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
186 AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
187 AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
188 AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
189 AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
190 AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
191 AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
192 AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
193 AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
194 AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
198 ospi0_pins_default: ospi0-pins-default {
199 pinctrl-single,pins = <
200 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
201 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
202 AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
203 AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
204 AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
205 AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
206 AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
207 AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
208 AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
209 AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
210 AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
214 main_ecap0_pins_default: main-ecap0-pins-default {
215 pinctrl-single,pins = <
216 AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
230 /* main_uart1 is reserved for firmware usage */
263 pinctrl-names = "default";
264 pinctrl-0 = <&main_i2c1_pins_default>;
265 clock-frequency = <400000>;
268 compatible = "nxp,pca9538";
272 gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
273 "PRU_DETECT", "MMC1_SD_EN",
274 "VPP_LDO_EN", "RPI_PS_3V3_En",
275 "RPI_PS_5V0_En", "RPI_HAT_DETECT";
291 /* mcu_gpio0 is reserved for mcu firmware usage */
298 vmmc-supply = <&vdd_mmc1>;
299 pinctrl-names = "default";
301 pinctrl-0 = <&main_mmc1_pins_default>;
302 ti,driver-strength-ohm = <50>;
307 idle-states = <AM64_SERDES0_LANE0_USB>;
311 serdes0_usb_link: phy@0 {
313 cdns,num-lanes = <1>;
315 cdns,phy-type = <PHY_TYPE_USB3>;
316 resets = <&serdes_wiz0 1>;
326 maximum-speed = "super-speed";
327 pinctrl-names = "default";
328 pinctrl-0 = <&main_usb0_pins_default>;
329 phys = <&serdes0_usb_link>;
330 phy-names = "cdns3,usb3-phy";
334 pinctrl-names = "default";
335 pinctrl-0 = <&mdio1_pins_default
337 &rgmii2_pins_default>;
341 phy-mode = "rgmii-rxid";
342 phy-handle = <&cpsw3g_phy0>;
346 phy-mode = "rgmii-rxid";
347 phy-handle = <&cpsw3g_phy1>;
351 cpsw3g_phy0: ethernet-phy@0 {
353 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
354 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
357 cpsw3g_phy1: ethernet-phy@1 {
359 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
360 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
369 pinctrl-names = "default";
370 pinctrl-0 = <&ospi0_pins_default>;
373 compatible = "jedec,spi-nor";
375 spi-tx-bus-width = <8>;
376 spi-rx-bus-width = <8>;
377 spi-max-frequency = <25000000>;
378 cdns,tshsl-ns = <60>;
379 cdns,tsd2d-ns = <60>;
380 cdns,tchsh-ns = <60>;
381 cdns,tslch-ns = <60>;
382 cdns,read-delay = <4>;
383 #address-cells = <1>;
389 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
390 ti,mbox-rx = <0 0 2>;
391 ti,mbox-tx = <1 0 2>;
394 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
395 ti,mbox-rx = <2 0 2>;
396 ti,mbox-tx = <3 0 2>;
405 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
406 ti,mbox-rx = <0 0 2>;
407 ti,mbox-tx = <1 0 2>;
410 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
411 ti,mbox-rx = <2 0 2>;
412 ti,mbox-tx = <3 0 2>;
421 mbox_m4_0: mbox-m4-0 {
422 ti,mbox-rx = <0 0 2>;
423 ti,mbox-tx = <1 0 2>;
432 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
433 memory-region = <&main_r5fss0_core0_dma_memory_region>,
434 <&main_r5fss0_core0_memory_region>;
438 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
439 memory-region = <&main_r5fss0_core1_dma_memory_region>,
440 <&main_r5fss0_core1_memory_region>;
444 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
445 memory-region = <&main_r5fss1_core0_dma_memory_region>,
446 <&main_r5fss1_core0_memory_region>;
450 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
451 memory-region = <&main_r5fss1_core1_dma_memory_region>,
452 <&main_r5fss1_core1_memory_region>;
464 /* PWM is available on Pin 1 of header J3 */
465 pinctrl-names = "default";
466 pinctrl-0 = <&main_ecap0_pins_default>;
495 * EPWM4_A, EPWM4_B is available on Pin 32 and 33 on J4 (RPi hat)
496 * But RPi Hat will be used for other use cases, so marking epwm4 as disabled.
503 * EPWM5_A, EPWM5_B is available on Pin 29 and 31 on J4 (RPi hat)
504 * But RPi Hat will be used for other use cases, so marking epwm5 as disabled.