src/arm64/ti/k3-am65-main.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for AM6 SoC Family Main Domain peripherals
   4  *
   5  * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7 #include <dt-bindings/phy/phy-am654-serdes.h>
   8
   9 &cbass_main {
  10         msmc_ram: sram@70000000 {
  11                 compatible = "mmio-sram";
  12                 reg = <0x0 0x70000000 0x0 0x200000>;
  13                 #address-cells = <1>;
  14                 #size-cells = <1>;
  15                 ranges = <0x0 0x0 0x70000000 0x200000>;
  16
  17                 atf-sram@0 {
  18                         reg = <0x0 0x20000>;
  19                 };
  20
  21                 sysfw-sram@f0000 {
  22                         reg = <0xf0000 0x10000>;
  23                 };
  24
  25                 l3cache-sram@100000 {
  26                         reg = <0x100000 0x100000>;
  27                 };
  28         };
  29
  30         gic500: interrupt-controller@1800000 {
  31                 compatible = "arm,gic-v3";
  32                 #address-cells = <2>;
  33                 #size-cells = <2>;
  34                 ranges;
  35                 #interrupt-cells = <3>;
  36                 interrupt-controller;
  37                 reg = <0x00 0x01800000 0x00 0x10000>,   /* GICD */
  38                       <0x00 0x01880000 0x00 0x90000>;   /* GICR */
  39                 /*
  40                  * vcpumntirq:
  41                  * virtual CPU interface maintenance interrupt
  42                  */
  43                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  44
  45                 gic_its: gic-its@1820000 {
  46                         compatible = "arm,gic-v3-its";
  47                         reg = <0x00 0x01820000 0x00 0x10000>;
  48                         socionext,synquacer-pre-its = <0x1000000 0x400000>;
  49                         msi-controller;
  50                         #msi-cells = <1>;
  51                 };
  52         };
  53
  54         serdes0: serdes@900000 {
  55                 compatible = "ti,phy-am654-serdes";
  56                 reg = <0x0 0x900000 0x0 0x2000>;
  57                 reg-names = "serdes";
  58                 #phy-cells = <2>;
  59                 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
  60                 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
  61                 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
  62                 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
  63                 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
  64                 ti,serdes-clk = <&serdes0_clk>;
  65                 #clock-cells = <1>;
  66                 mux-controls = <&serdes_mux 0>;
  67         };
  68
  69         serdes1: serdes@910000 {
  70                 compatible = "ti,phy-am654-serdes";
  71                 reg = <0x0 0x910000 0x0 0x2000>;
  72                 reg-names = "serdes";
  73                 #phy-cells = <2>;
  74                 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
  75                 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
  76                 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
  77                 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
  78                 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
  79                 ti,serdes-clk = <&serdes1_clk>;
  80                 #clock-cells = <1>;
  81                 mux-controls = <&serdes_mux 1>;
  82         };
  83
  84         main_uart0: serial@2800000 {
  85                 compatible = "ti,am654-uart";
  86                 reg = <0x00 0x02800000 0x00 0x100>;
  87                 reg-shift = <2>;
  88                 reg-io-width = <4>;
  89                 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
  90                 clock-frequency = <48000000>;
  91                 current-speed = <115200>;
  92                 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
  93         };
  94
  95         main_uart1: serial@2810000 {
  96                 compatible = "ti,am654-uart";
  97                 reg = <0x00 0x02810000 0x00 0x100>;
  98                 reg-shift = <2>;
  99                 reg-io-width = <4>;
 100                 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 101                 clock-frequency = <48000000>;
 102                 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
 103         };
 104
 105         main_uart2: serial@2820000 {
 106                 compatible = "ti,am654-uart";
 107                 reg = <0x00 0x02820000 0x00 0x100>;
 108                 reg-shift = <2>;
 109                 reg-io-width = <4>;
 110                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
 111                 clock-frequency = <48000000>;
 112                 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
 113         };
 114
 115         main_pmx0: pinmux@11c000 {
 116                 compatible = "pinctrl-single";
 117                 reg = <0x0 0x11c000 0x0 0x2e4>;
 118                 #pinctrl-cells = <1>;
 119                 pinctrl-single,register-width = <32>;
 120                 pinctrl-single,function-mask = <0xffffffff>;
 121         };
 122
 123         main_pmx1: pinmux@11c2e8 {
 124                 compatible = "pinctrl-single";
 125                 reg = <0x0 0x11c2e8 0x0 0x24>;
 126                 #pinctrl-cells = <1>;
 127                 pinctrl-single,register-width = <32>;
 128                 pinctrl-single,function-mask = <0xffffffff>;
 129         };
 130
 131         main_i2c0: i2c@2000000 {
 132                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
 133                 reg = <0x0 0x2000000 0x0 0x100>;
 134                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 135                 #address-cells = <1>;
 136                 #size-cells = <0>;
 137                 clock-names = "fck";
 138                 clocks = <&k3_clks 110 1>;
 139                 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
 140         };
 141
 142         main_i2c1: i2c@2010000 {
 143                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
 144                 reg = <0x0 0x2010000 0x0 0x100>;
 145                 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 146                 #address-cells = <1>;
 147                 #size-cells = <0>;
 148                 clock-names = "fck";
 149                 clocks = <&k3_clks 111 1>;
 150                 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
 151         };
 152
 153         main_i2c2: i2c@2020000 {
 154                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
 155                 reg = <0x0 0x2020000 0x0 0x100>;
 156                 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
 157                 #address-cells = <1>;
 158                 #size-cells = <0>;
 159                 clock-names = "fck";
 160                 clocks = <&k3_clks 112 1>;
 161                 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
 162         };
 163
 164         main_i2c3: i2c@2030000 {
 165                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
 166                 reg = <0x0 0x2030000 0x0 0x100>;
 167                 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 168                 #address-cells = <1>;
 169                 #size-cells = <0>;
 170                 clock-names = "fck";
 171                 clocks = <&k3_clks 113 1>;
 172                 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
 173         };
 174
 175         ecap0: pwm@3100000 {
 176                 compatible = "ti,am654-ecap", "ti,am3352-ecap";
 177                 #pwm-cells = <3>;
 178                 reg = <0x0 0x03100000 0x0 0x60>;
 179                 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
 180                 clocks = <&k3_clks 39 0>;
 181                 clock-names = "fck";
 182         };
 183
 184         main_spi0: spi@2100000 {
 185                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 186                 reg = <0x0 0x2100000 0x0 0x400>;
 187                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 188                 clocks = <&k3_clks 137 1>;
 189                 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
 190                 #address-cells = <1>;
 191                 #size-cells = <0>;
 192                 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
 193                 dma-names = "tx0", "rx0";
 194         };
 195
 196         main_spi1: spi@2110000 {
 197                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 198                 reg = <0x0 0x2110000 0x0 0x400>;
 199                 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
 200                 clocks = <&k3_clks 138 1>;
 201                 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
 202                 #address-cells = <1>;
 203                 #size-cells = <0>;
 204                 assigned-clocks = <&k3_clks 137 1>;
 205                 assigned-clock-rates = <48000000>;
 206         };
 207
 208         main_spi2: spi@2120000 {
 209                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 210                 reg = <0x0 0x2120000 0x0 0x400>;
 211                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 212                 clocks = <&k3_clks 139 1>;
 213                 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
 214                 #address-cells = <1>;
 215                 #size-cells = <0>;
 216         };
 217
 218         main_spi3: spi@2130000 {
 219                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 220                 reg = <0x0 0x2130000 0x0 0x400>;
 221                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 222                 clocks = <&k3_clks 140 1>;
 223                 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
 224                 #address-cells = <1>;
 225                 #size-cells = <0>;
 226         };
 227
 228         main_spi4: spi@2140000 {
 229                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 230                 reg = <0x0 0x2140000 0x0 0x400>;
 231                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 232                 clocks = <&k3_clks 141 1>;
 233                 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
 234                 #address-cells = <1>;
 235                 #size-cells = <0>;
 236         };
 237
 238         sdhci0: sdhci@4f80000 {
 239                 compatible = "ti,am654-sdhci-5.1";
 240                 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
 241                 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
 242                 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
 243                 clock-names = "clk_ahb", "clk_xin";
 244                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 245                 mmc-ddr-1_8v;
 246                 mmc-hs200-1_8v;
 247                 ti,otap-del-sel = <0x2>;
 248                 ti,trm-icp = <0x8>;
 249                 dma-coherent;
 250         };
 251
 252         scm_conf: scm_conf@100000 {
 253                 compatible = "syscon", "simple-mfd";
 254                 reg = <0 0x00100000 0 0x1c000>;
 255                 #address-cells = <1>;
 256                 #size-cells = <1>;
 257                 ranges = <0x0 0x0 0x00100000 0x1c000>;
 258
 259                 pcie0_mode: pcie-mode@4060 {
 260                         compatible = "syscon";
 261                         reg = <0x00004060 0x4>;
 262                 };
 263
 264                 pcie1_mode: pcie-mode@4070 {
 265                         compatible = "syscon";
 266                         reg = <0x00004070 0x4>;
 267                 };
 268
 269                 pcie_devid: pcie-devid@210 {
 270                         compatible = "syscon";
 271                         reg = <0x00000210 0x4>;
 272                 };
 273
 274                 serdes0_clk: serdes_clk@4080 {
 275                         compatible = "syscon";
 276                         reg = <0x00004080 0x4>;
 277                 };
 278
 279                 serdes1_clk: serdes_clk@4090 {
 280                         compatible = "syscon";
 281                         reg = <0x00004090 0x4>;
 282                 };
 283
 284                 serdes_mux: mux-controller {
 285                         compatible = "mmio-mux";
 286                         #mux-control-cells = <1>;
 287                         mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
 288                                         <0x4090 0x3>; /* SERDES1 lane select */
 289                 };
 290
 291                 dss_oldi_io_ctrl: dss_oldi_io_ctrl@41E0 {
 292                         compatible = "syscon";
 293                         reg = <0x0000041E0 0x14>;
 294                 };
 295
 296                 ehrpwm_tbclk: syscon@4140 {
 297                         compatible = "ti,am654-ehrpwm-tbclk", "syscon";
 298                         reg = <0x4140 0x18>;
 299                         #clock-cells = <1>;
 300                 };
 301         };
 302
 303         dwc3_0: dwc3@4000000 {
 304                 compatible = "ti,am654-dwc3";
 305                 reg = <0x0 0x4000000 0x0 0x4000>;
 306                 #address-cells = <1>;
 307                 #size-cells = <1>;
 308                 ranges = <0x0 0x0 0x4000000 0x20000>;
 309                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 310                 dma-coherent;
 311                 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
 312                 clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
 313                 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
 314                 assigned-clock-parents = <&k3_clks 151 4>,      /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
 315                                          <&k3_clks 151 9>;      /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
 316
 317                 usb0: usb@10000 {
 318                         compatible = "snps,dwc3";
 319                         reg = <0x10000 0x10000>;
 320                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 321                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 322                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 323                         interrupt-names = "peripheral",
 324                                           "host",
 325                                           "otg";
 326                         maximum-speed = "high-speed";
 327                         dr_mode = "otg";
 328                         phys = <&usb0_phy>;
 329                         phy-names = "usb2-phy";
 330                         snps,dis_u3_susphy_quirk;
 331                 };
 332         };
 333
 334         usb0_phy: phy@4100000 {
 335                 compatible = "ti,am654-usb2", "ti,omap-usb2";
 336                 reg = <0x0 0x4100000 0x0 0x54>;
 337                 syscon-phy-power = <&scm_conf 0x4000>;
 338                 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
 339                 clock-names = "wkupclk", "refclk";
 340                 #phy-cells = <0>;
 341         };
 342
 343         dwc3_1: dwc3@4020000 {
 344                 compatible = "ti,am654-dwc3";
 345                 reg = <0x0 0x4020000 0x0 0x4000>;
 346                 #address-cells = <1>;
 347                 #size-cells = <1>;
 348                 ranges = <0x0 0x0 0x4020000 0x20000>;
 349                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 350                 dma-coherent;
 351                 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
 352                 clocks = <&k3_clks 152 2>;
 353                 assigned-clocks = <&k3_clks 152 2>;
 354                 assigned-clock-parents = <&k3_clks 152 4>;      /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
 355
 356                 usb1: usb@10000 {
 357                         compatible = "snps,dwc3";
 358                         reg = <0x10000 0x10000>;
 359                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 360                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 361                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 362                         interrupt-names = "peripheral",
 363                                           "host",
 364                                           "otg";
 365                         maximum-speed = "high-speed";
 366                         dr_mode = "otg";
 367                         phys = <&usb1_phy>;
 368                         phy-names = "usb2-phy";
 369                 };
 370         };
 371
 372         usb1_phy: phy@4110000 {
 373                 compatible = "ti,am654-usb2", "ti,omap-usb2";
 374                 reg = <0x0 0x4110000 0x0 0x54>;
 375                 syscon-phy-power = <&scm_conf 0x4020>;
 376                 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
 377                 clock-names = "wkupclk", "refclk";
 378                 #phy-cells = <0>;
 379         };
 380
 381         intr_main_gpio: interrupt-controller0 {
 382                 compatible = "ti,sci-intr";
 383                 ti,intr-trigger-type = <1>;
 384                 interrupt-controller;
 385                 interrupt-parent = <&gic500>;
 386                 #interrupt-cells = <2>;
 387                 ti,sci = <&dmsc>;
 388                 ti,sci-dst-id = <56>;
 389                 ti,sci-rm-range-girq = <0x1>;
 390         };
 391
 392         main_navss {
 393                 compatible = "simple-mfd";
 394                 #address-cells = <2>;
 395                 #size-cells = <2>;
 396                 ranges;
 397                 dma-coherent;
 398                 dma-ranges;
 399
 400                 ti,sci-dev-id = <118>;
 401
 402                 intr_main_navss: interrupt-controller1 {
 403                         compatible = "ti,sci-intr";
 404                         ti,intr-trigger-type = <4>;
 405                         interrupt-controller;
 406                         interrupt-parent = <&gic500>;
 407                         #interrupt-cells = <2>;
 408                         ti,sci = <&dmsc>;
 409                         ti,sci-dst-id = <56>;
 410                         ti,sci-rm-range-girq = <0x0>, <0x2>;
 411                 };
 412
 413                 inta_main_udmass: interrupt-controller@33d00000 {
 414                         compatible = "ti,sci-inta";
 415                         reg = <0x0 0x33d00000 0x0 0x100000>;
 416                         interrupt-controller;
 417                         interrupt-parent = <&intr_main_navss>;
 418                         msi-controller;
 419                         ti,sci = <&dmsc>;
 420                         ti,sci-dev-id = <179>;
 421                         ti,sci-rm-range-vint = <0x0>;
 422                         ti,sci-rm-range-global-event = <0x1>;
 423                 };
 424
 425                 secure_proxy_main: mailbox@32c00000 {
 426                         compatible = "ti,am654-secure-proxy";
 427                         #mbox-cells = <1>;
 428                         reg-names = "target_data", "rt", "scfg";
 429                         reg = <0x00 0x32c00000 0x00 0x100000>,
 430                               <0x00 0x32400000 0x00 0x100000>,
 431                               <0x00 0x32800000 0x00 0x100000>;
 432                         interrupt-names = "rx_011";
 433                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 434                 };
 435
 436                 hwspinlock: spinlock@30e00000 {
 437                         compatible = "ti,am654-hwspinlock";
 438                         reg = <0x00 0x30e00000 0x00 0x1000>;
 439                         #hwlock-cells = <1>;
 440                 };
 441
 442                 mailbox0_cluster0: mailbox@31f80000 {
 443                         compatible = "ti,am654-mailbox";
 444                         reg = <0x00 0x31f80000 0x00 0x200>;
 445                         #mbox-cells = <1>;
 446                         ti,mbox-num-users = <4>;
 447                         ti,mbox-num-fifos = <16>;
 448                         interrupt-parent = <&intr_main_navss>;
 449                 };
 450
 451                 mailbox0_cluster1: mailbox@31f81000 {
 452                         compatible = "ti,am654-mailbox";
 453                         reg = <0x00 0x31f81000 0x00 0x200>;
 454                         #mbox-cells = <1>;
 455                         ti,mbox-num-users = <4>;
 456                         ti,mbox-num-fifos = <16>;
 457                         interrupt-parent = <&intr_main_navss>;
 458                 };
 459
 460                 mailbox0_cluster2: mailbox@31f82000 {
 461                         compatible = "ti,am654-mailbox";
 462                         reg = <0x00 0x31f82000 0x00 0x200>;
 463                         #mbox-cells = <1>;
 464                         ti,mbox-num-users = <4>;
 465                         ti,mbox-num-fifos = <16>;
 466                         interrupt-parent = <&intr_main_navss>;
 467                 };
 468
 469                 mailbox0_cluster3: mailbox@31f83000 {
 470                         compatible = "ti,am654-mailbox";
 471                         reg = <0x00 0x31f83000 0x00 0x200>;
 472                         #mbox-cells = <1>;
 473                         ti,mbox-num-users = <4>;
 474                         ti,mbox-num-fifos = <16>;
 475                         interrupt-parent = <&intr_main_navss>;
 476                 };
 477
 478                 mailbox0_cluster4: mailbox@31f84000 {
 479                         compatible = "ti,am654-mailbox";
 480                         reg = <0x00 0x31f84000 0x00 0x200>;
 481                         #mbox-cells = <1>;
 482                         ti,mbox-num-users = <4>;
 483                         ti,mbox-num-fifos = <16>;
 484                         interrupt-parent = <&intr_main_navss>;
 485                 };
 486
 487                 mailbox0_cluster5: mailbox@31f85000 {
 488                         compatible = "ti,am654-mailbox";
 489                         reg = <0x00 0x31f85000 0x00 0x200>;
 490                         #mbox-cells = <1>;
 491                         ti,mbox-num-users = <4>;
 492                         ti,mbox-num-fifos = <16>;
 493                         interrupt-parent = <&intr_main_navss>;
 494                 };
 495
 496                 mailbox0_cluster6: mailbox@31f86000 {
 497                         compatible = "ti,am654-mailbox";
 498                         reg = <0x00 0x31f86000 0x00 0x200>;
 499                         #mbox-cells = <1>;
 500                         ti,mbox-num-users = <4>;
 501                         ti,mbox-num-fifos = <16>;
 502                         interrupt-parent = <&intr_main_navss>;
 503                 };
 504
 505                 mailbox0_cluster7: mailbox@31f87000 {
 506                         compatible = "ti,am654-mailbox";
 507                         reg = <0x00 0x31f87000 0x00 0x200>;
 508                         #mbox-cells = <1>;
 509                         ti,mbox-num-users = <4>;
 510                         ti,mbox-num-fifos = <16>;
 511                         interrupt-parent = <&intr_main_navss>;
 512                 };
 513
 514                 mailbox0_cluster8: mailbox@31f88000 {
 515                         compatible = "ti,am654-mailbox";
 516                         reg = <0x00 0x31f88000 0x00 0x200>;
 517                         #mbox-cells = <1>;
 518                         ti,mbox-num-users = <4>;
 519                         ti,mbox-num-fifos = <16>;
 520                         interrupt-parent = <&intr_main_navss>;
 521                 };
 522
 523                 mailbox0_cluster9: mailbox@31f89000 {
 524                         compatible = "ti,am654-mailbox";
 525                         reg = <0x00 0x31f89000 0x00 0x200>;
 526                         #mbox-cells = <1>;
 527                         ti,mbox-num-users = <4>;
 528                         ti,mbox-num-fifos = <16>;
 529                         interrupt-parent = <&intr_main_navss>;
 530                 };
 531
 532                 mailbox0_cluster10: mailbox@31f8a000 {
 533                         compatible = "ti,am654-mailbox";
 534                         reg = <0x00 0x31f8a000 0x00 0x200>;
 535                         #mbox-cells = <1>;
 536                         ti,mbox-num-users = <4>;
 537                         ti,mbox-num-fifos = <16>;
 538                         interrupt-parent = <&intr_main_navss>;
 539                 };
 540
 541                 mailbox0_cluster11: mailbox@31f8b000 {
 542                         compatible = "ti,am654-mailbox";
 543                         reg = <0x00 0x31f8b000 0x00 0x200>;
 544                         #mbox-cells = <1>;
 545                         ti,mbox-num-users = <4>;
 546                         ti,mbox-num-fifos = <16>;
 547                         interrupt-parent = <&intr_main_navss>;
 548                 };
 549
 550                 ringacc: ringacc@3c000000 {
 551                         compatible = "ti,am654-navss-ringacc";
 552                         reg =   <0x0 0x3c000000 0x0 0x400000>,
 553                                 <0x0 0x38000000 0x0 0x400000>,
 554                                 <0x0 0x31120000 0x0 0x100>,
 555                                 <0x0 0x33000000 0x0 0x40000>;
 556                         reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
 557                         ti,num-rings = <818>;
 558                         ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
 559                         ti,dma-ring-reset-quirk;
 560                         ti,sci = <&dmsc>;
 561                         ti,sci-dev-id = <187>;
 562                         msi-parent = <&inta_main_udmass>;
 563                 };
 564
 565                 main_udmap: dma-controller@31150000 {
 566                         compatible = "ti,am654-navss-main-udmap";
 567                         reg =   <0x0 0x31150000 0x0 0x100>,
 568                                 <0x0 0x34000000 0x0 0x100000>,
 569                                 <0x0 0x35000000 0x0 0x100000>;
 570                         reg-names = "gcfg", "rchanrt", "tchanrt";
 571                         msi-parent = <&inta_main_udmass>;
 572                         #dma-cells = <1>;
 573
 574                         ti,sci = <&dmsc>;
 575                         ti,sci-dev-id = <188>;
 576                         ti,ringacc = <&ringacc>;
 577
 578                         ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
 579                                                 <0x2>; /* TX_CHAN */
 580                         ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
 581                                                 <0x5>; /* RX_CHAN */
 582                         ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
 583                 };
 584
 585                 cpts@310d0000 {
 586                         compatible = "ti,am65-cpts";
 587                         reg = <0x0 0x310d0000 0x0 0x400>;
 588                         reg-names = "cpts";
 589                         clocks = <&main_cpts_mux>;
 590                         clock-names = "cpts";
 591                         interrupts-extended = <&intr_main_navss 163 0>;
 592                         interrupt-names = "cpts";
 593                         ti,cpts-periodic-outputs = <6>;
 594                         ti,cpts-ext-ts-inputs = <8>;
 595
 596                         main_cpts_mux: refclk-mux {
 597                                 #clock-cells = <0>;
 598                                 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
 599                                         <&k3_clks 118 6>, <&k3_clks 118 3>,
 600                                         <&k3_clks 118 8>, <&k3_clks 118 14>,
 601                                         <&k3_clks 120 3>, <&k3_clks 121 3>;
 602                                 assigned-clocks = <&main_cpts_mux>;
 603                                 assigned-clock-parents = <&k3_clks 118 5>;
 604                         };
 605                 };
 606         };
 607
 608         main_gpio0:  main_gpio0@600000 {
 609                 compatible = "ti,am654-gpio", "ti,keystone-gpio";
 610                 reg = <0x0 0x600000 0x0 0x100>;
 611                 gpio-controller;
 612                 #gpio-cells = <2>;
 613                 interrupt-parent = <&intr_main_gpio>;
 614                 interrupts = <57 256>, <57 257>, <57 258>, <57 259>, <57 260>,
 615                                 <57 261>;
 616                 interrupt-controller;
 617                 #interrupt-cells = <2>;
 618                 ti,ngpio = <96>;
 619                 ti,davinci-gpio-unbanked = <0>;
 620                 clocks = <&k3_clks 57 0>;
 621                 clock-names = "gpio";
 622         };
 623
 624         main_gpio1:  main_gpio1@601000 {
 625                 compatible = "ti,am654-gpio", "ti,keystone-gpio";
 626                 reg = <0x0 0x601000 0x0 0x100>;
 627                 gpio-controller;
 628                 #gpio-cells = <2>;
 629                 interrupt-parent = <&intr_main_gpio>;
 630                 interrupts = <58 256>, <58 257>, <58 258>, <58 259>, <58 260>,
 631                                 <58 261>;
 632                 interrupt-controller;
 633                 #interrupt-cells = <2>;
 634                 ti,ngpio = <90>;
 635                 ti,davinci-gpio-unbanked = <0>;
 636                 clocks = <&k3_clks 58 0>;
 637                 clock-names = "gpio";
 638         };
 639
 640         pcie0_rc: pcie@5500000 {
 641                 compatible = "ti,am654-pcie-rc";
 642                 reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
 643                 reg-names = "app", "dbics", "config", "atu";
 644                 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
 645                 #address-cells = <3>;
 646                 #size-cells = <2>;
 647                 ranges = <0x81000000 0 0          0x0 0x10020000 0 0x00010000
 648                           0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
 649                 ti,syscon-pcie-id = <&pcie_devid>;
 650                 ti,syscon-pcie-mode = <&pcie0_mode>;
 651                 bus-range = <0x0 0xff>;
 652                 num-viewport = <16>;
 653                 max-link-speed = <3>;
 654                 dma-coherent;
 655                 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
 656                 msi-map = <0x0 &gic_its 0x0 0x10000>;
 657         };
 658
 659         pcie0_ep: pcie-ep@5500000 {
 660                 compatible = "ti,am654-pcie-ep";
 661                 reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
 662                 reg-names = "app", "dbics", "addr_space", "atu";
 663                 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
 664                 ti,syscon-pcie-mode = <&pcie0_mode>;
 665                 num-ib-windows = <16>;
 666                 num-ob-windows = <16>;
 667                 max-link-speed = <3>;
 668                 dma-coherent;
 669                 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
 670         };
 671
 672         pcie1_rc: pcie@5600000 {
 673                 compatible = "ti,am654-pcie-rc";
 674                 reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
 675                 reg-names = "app", "dbics", "config", "atu";
 676                 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
 677                 #address-cells = <3>;
 678                 #size-cells = <2>;
 679                 ranges = <0x81000000 0 0          0x0   0x18020000 0 0x00010000
 680                           0x82000000 0 0x18030000 0x0   0x18030000 0 0x07FD0000>;
 681                 ti,syscon-pcie-id = <&pcie_devid>;
 682                 ti,syscon-pcie-mode = <&pcie1_mode>;
 683                 bus-range = <0x0 0xff>;
 684                 num-viewport = <16>;
 685                 max-link-speed = <3>;
 686                 dma-coherent;
 687                 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
 688                 msi-map = <0x0 &gic_its 0x10000 0x10000>;
 689         };
 690
 691         pcie1_ep: pcie-ep@5600000 {
 692                 compatible = "ti,am654-pcie-ep";
 693                 reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
 694                 reg-names = "app", "dbics", "addr_space", "atu";
 695                 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
 696                 ti,syscon-pcie-mode = <&pcie1_mode>;
 697                 num-ib-windows = <16>;
 698                 num-ob-windows = <16>;
 699                 max-link-speed = <3>;
 700                 dma-coherent;
 701                 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
 702         };
 703
 704         mcasp0: mcasp@2b00000 {
 705                 compatible = "ti,am33xx-mcasp-audio";
 706                 reg = <0x0 0x02b00000 0x0 0x2000>,
 707                         <0x0 0x02b08000 0x0 0x1000>;
 708                 reg-names = "mpu","dat";
 709                 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
 710                                 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 711                 interrupt-names = "tx", "rx";
 712
 713                 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
 714                 dma-names = "tx", "rx";
 715
 716                 clocks = <&k3_clks 104 0>;
 717                 clock-names = "fck";
 718                 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
 719
 720                 status = "disabled";
 721         };
 722
 723         mcasp1: mcasp@2b10000 {
 724                 compatible = "ti,am33xx-mcasp-audio";
 725                 reg = <0x0 0x02b10000 0x0 0x2000>,
 726                         <0x0 0x02b18000 0x0 0x1000>;
 727                 reg-names = "mpu","dat";
 728                 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
 729                                 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
 730                 interrupt-names = "tx", "rx";
 731
 732                 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
 733                 dma-names = "tx", "rx";
 734
 735                 clocks = <&k3_clks 105 0>;
 736                 clock-names = "fck";
 737                 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
 738
 739                 status = "disabled";
 740         };
 741
 742         mcasp2: mcasp@2b20000 {
 743                 compatible = "ti,am33xx-mcasp-audio";
 744                 reg = <0x0 0x02b20000 0x0 0x2000>,
 745                         <0x0 0x02b28000 0x0 0x1000>;
 746                 reg-names = "mpu","dat";
 747                 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 748                                 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
 749                 interrupt-names = "tx", "rx";
 750
 751                 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
 752                 dma-names = "tx", "rx";
 753
 754                 clocks = <&k3_clks 106 0>;
 755                 clock-names = "fck";
 756                 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
 757
 758                 status = "disabled";
 759         };
 760
 761         cal: cal@6f03000 {
 762                 compatible = "ti,am654-cal";
 763                 reg = <0x0 0x06f03000 0x0 0x400>,
 764                       <0x0 0x06f03800 0x0 0x40>;
 765                 reg-names = "cal_top",
 766                             "cal_rx_core0";
 767                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 768                 ti,camerrx-control = <&scm_conf 0x40c0>;
 769                 clock-names = "fck";
 770                 clocks = <&k3_clks 2 0>;
 771                 power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>;
 772
 773                 ports {
 774                         #address-cells = <1>;
 775                         #size-cells = <0>;
 776
 777                         csi2_0: port@0 {
 778                                 reg = <0>;
 779                         };
 780                 };
 781         };
 782
 783         dss: dss@04a00000 {
 784                 compatible = "ti,am65x-dss";
 785                 reg =   <0x0 0x04a00000 0x0 0x1000>, /* common */
 786                         <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
 787                         <0x0 0x04a06000 0x0 0x1000>, /* vid */
 788                         <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
 789                         <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
 790                         <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
 791                         <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
 792                 reg-names = "common", "vidl1", "vid",
 793                         "ovr1", "ovr2", "vp1", "vp2";
 794
 795                 ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
 796
 797                 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
 798
 799                 clocks =        <&k3_clks 67 1>,
 800                                 <&k3_clks 216 1>,
 801                                 <&k3_clks 67 2>;
 802                 clock-names = "fck", "vp1", "vp2";
 803
 804                 /*
 805                  * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
 806                  * DIV1. See "Figure 12-3365. DSS Integration"
 807                  * in AM65x TRM for details.
 808                  */
 809                 assigned-clocks = <&k3_clks 67 2>;
 810                 assigned-clock-parents = <&k3_clks 67 5>;
 811
 812                 interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
 813
 814                 status = "disabled";
 815
 816                 dss_ports: ports {
 817                         #address-cells = <1>;
 818                         #size-cells = <0>;
 819                 };
 820         };
 821
 822         ehrpwm0: pwm@3000000 {
 823                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 824                 #pwm-cells = <3>;
 825                 reg = <0x0 0x3000000 0x0 0x100>;
 826                 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
 827                 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
 828                 clock-names = "tbclk", "fck";
 829         };
 830
 831         ehrpwm1: pwm@3010000 {
 832                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 833                 #pwm-cells = <3>;
 834                 reg = <0x0 0x3010000 0x0 0x100>;
 835                 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
 836                 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
 837                 clock-names = "tbclk", "fck";
 838         };
 839
 840         ehrpwm2: pwm@3020000 {
 841                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 842                 #pwm-cells = <3>;
 843                 reg = <0x0 0x3020000 0x0 0x100>;
 844                 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
 845                 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
 846                 clock-names = "tbclk", "fck";
 847         };
 848
 849         ehrpwm3: pwm@3030000 {
 850                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 851                 #pwm-cells = <3>;
 852                 reg = <0x0 0x3030000 0x0 0x100>;
 853                 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
 854                 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
 855                 clock-names = "tbclk", "fck";
 856         };
 857
 858         ehrpwm4: pwm@3040000 {
 859                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 860                 #pwm-cells = <3>;
 861                 reg = <0x0 0x3040000 0x0 0x100>;
 862                 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
 863                 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
 864                 clock-names = "tbclk", "fck";
 865         };
 866
 867         ehrpwm5: pwm@3050000 {
 868                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 869                 #pwm-cells = <3>;
 870                 reg = <0x0 0x3050000 0x0 0x100>;
 871                 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
 872                 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
 873                 clock-names = "tbclk", "fck";
 874         };
 875 };