src/arm64/toshiba/tmpv7708.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Source for the TMPV7708
   4  *
   5  * (C) Copyright 2018 - 2020, Toshiba Corporation.
   6  * (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
   7  *
   8  */
   9
  10 #include <dt-bindings/clock/toshiba,tmpv770x.h>
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13
  14 /memreserve/ 0x81000000 0x00300000;     /* cpu-release-addr */
  15
  16 / {
  17         compatible = "toshiba,tmpv7708";
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu-map {
  26                         cluster0 {
  27                                 core0 {
  28                                         cpu = <&cpu0>;
  29                                 };
  30                                 core1 {
  31                                         cpu = <&cpu1>;
  32                                 };
  33                                 core2 {
  34                                         cpu = <&cpu2>;
  35                                 };
  36                                 core3 {
  37                                         cpu = <&cpu3>;
  38                                 };
  39                         };
  40
  41                         cluster1 {
  42                                 core0 {
  43                                         cpu = <&cpu4>;
  44                                 };
  45                                 core1 {
  46                                         cpu = <&cpu5>;
  47                                 };
  48                                 core2 {
  49                                         cpu = <&cpu6>;
  50                                 };
  51                                 core3 {
  52                                         cpu = <&cpu7>;
  53                                 };
  54                         };
  55                 };
  56
  57                 cpu0: cpu@0 {
  58                         compatible = "arm,cortex-a53";
  59                         device_type = "cpu";
  60                         enable-method = "spin-table";
  61                         cpu-release-addr = <0x0 0x81100000>;
  62                         reg = <0x00>;
  63                 };
  64
  65                 cpu1: cpu@1 {
  66                         compatible = "arm,cortex-a53";
  67                         device_type = "cpu";
  68                         enable-method = "spin-table";
  69                         cpu-release-addr = <0x0 0x81100000>;
  70                         reg = <0x01>;
  71                 };
  72
  73                 cpu2: cpu@2 {
  74                         compatible = "arm,cortex-a53";
  75                         device_type = "cpu";
  76                         enable-method = "spin-table";
  77                         cpu-release-addr = <0x0 0x81100000>;
  78                         reg = <0x02>;
  79                 };
  80
  81                 cpu3: cpu@3 {
  82                         compatible = "arm,cortex-a53";
  83                         device_type = "cpu";
  84                         enable-method = "spin-table";
  85                         cpu-release-addr = <0x0 0x81100000>;
  86                         reg = <0x03>;
  87                 };
  88
  89                 cpu4: cpu@100 {
  90                         compatible = "arm,cortex-a53";
  91                         device_type = "cpu";
  92                         enable-method = "spin-table";
  93                         cpu-release-addr = <0x0 0x81100000>;
  94                         reg = <0x100>;
  95                 };
  96
  97                 cpu5: cpu@101 {
  98                         compatible = "arm,cortex-a53";
  99                         device_type = "cpu";
 100                         enable-method = "spin-table";
 101                         cpu-release-addr = <0x0 0x81100000>;
 102                         reg = <0x101>;
 103                 };
 104
 105                 cpu6: cpu@102 {
 106                         compatible = "arm,cortex-a53";
 107                         device_type = "cpu";
 108                         enable-method = "spin-table";
 109                         cpu-release-addr = <0x0 0x81100000>;
 110                         reg = <0x102>;
 111                 };
 112
 113                 cpu7: cpu@103 {
 114                         compatible = "arm,cortex-a53";
 115                         device_type = "cpu";
 116                         enable-method = "spin-table";
 117                         cpu-release-addr = <0x0 0x81100000>;
 118                         reg = <0x103>;
 119                 };
 120         };
 121
 122         timer {
 123                 compatible = "arm,armv8-timer";
 124                 interrupt-parent = <&gic>;
 125                 interrupts =
 126                         <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 127                         <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 128                         <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 129                         <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 130         };
 131
 132         extclk100mhz: extclk100mhz {
 133                 compatible = "fixed-clock";
 134                 #clock-cells = <0>;
 135                 clock-frequency = <100000000>;
 136                 clock-output-names = "extclk100mhz";
 137         };
 138
 139         osc2_clk: osc2-clk {
 140                 compatible = "fixed-clock";
 141                 clock-frequency = <20000000>;
 142                 #clock-cells = <0>;
 143         };
 144
 145         soc {
 146                 #address-cells = <2>;
 147                 #size-cells = <2>;
 148                 compatible = "simple-bus";
 149                 interrupt-parent = <&gic>;
 150                 ranges;
 151
 152                 gic: interrupt-controller@24001000 {
 153                         compatible = "arm,gic-400";
 154                         interrupt-controller;
 155                         #interrupt-cells = <3>;
 156                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 157                         reg = <0 0x24001000 0 0x1000>,
 158                               <0 0x24002000 0 0x2000>,
 159                               <0 0x24004000 0 0x2000>,
 160                               <0 0x24006000 0 0x2000>;
 161                 };
 162
 163                 pmux: pmux@24190000 {
 164                         compatible = "toshiba,tmpv7708-pinctrl";
 165                         reg = <0 0x24190000 0 0x10000>;
 166                 };
 167
 168                 gpio: gpio@28020000 {
 169                         compatible = "toshiba,gpio-tmpv7708";
 170                         reg = <0 0x28020000 0 0x1000>;
 171                         #gpio-cells = <0x2>;
 172                         gpio-ranges = <&pmux 0 0 32>;
 173                         gpio-controller;
 174                         interrupt-controller;
 175                         #interrupt-cells = <2>;
 176                         interrupt-parent = <&gic>;
 177                 };
 178
 179                 pipllct: clock-controller@24220000 {
 180                         compatible = "toshiba,tmpv7708-pipllct";
 181                         reg = <0 0x24220000 0 0x820>;
 182                         #clock-cells = <1>;
 183                         clocks = <&osc2_clk>;
 184                 };
 185
 186                 pismu: syscon@24200000 {
 187                         compatible = "toshiba,tmpv7708-pismu", "syscon";
 188                         reg = <0 0x24200000 0 0x2140>;
 189                         #clock-cells = <1>;
 190                         #reset-cells = <1>;
 191                 };
 192
 193                 uart0: serial@28200000 {
 194                         compatible = "arm,pl011", "arm,primecell";
 195                         reg = <0 0x28200000 0 0x1000>;
 196                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 197                         pinctrl-names = "default";
 198                         pinctrl-0 = <&uart0_pins>;
 199                         clocks = <&pismu TMPV770X_CLK_PIUART0>;
 200                         clock-names = "apb_pclk";
 201                         status = "disabled";
 202                 };
 203
 204                 uart1: serial@28201000 {
 205                         compatible = "arm,pl011", "arm,primecell";
 206                         reg = <0 0x28201000 0 0x1000>;
 207                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 208                         pinctrl-names = "default";
 209                         pinctrl-0 = <&uart1_pins>;
 210                         clocks = <&pismu TMPV770X_CLK_PIUART1>;
 211                         clock-names = "apb_pclk";
 212                         status = "disabled";
 213                 };
 214
 215                 uart2: serial@28202000 {
 216                         compatible = "arm,pl011", "arm,primecell";
 217                         reg = <0 0x28202000 0 0x1000>;
 218                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 219                         pinctrl-names = "default";
 220                         pinctrl-0 = <&uart2_pins>;
 221                         clocks = <&pismu TMPV770X_CLK_PIUART2>;
 222                         clock-names = "apb_pclk";
 223                         status = "disabled";
 224                 };
 225
 226                 uart3: serial@28203000 {
 227                         compatible = "arm,pl011", "arm,primecell";
 228                         reg = <0 0x28203000 0 0x1000>;
 229                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 230                         pinctrl-names = "default";
 231                         pinctrl-0 = <&uart3_pins>;
 232                         clocks = <&pismu TMPV770X_CLK_PIUART2>;
 233                         clock-names = "apb_pclk";
 234                         status = "disabled";
 235                 };
 236
 237                 i2c0: i2c@28030000 {
 238                         compatible = "snps,designware-i2c";
 239                         reg = <0 0x28030000 0 0x1000>;
 240                         interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 241                         pinctrl-names = "default";
 242                         pinctrl-0 = <&i2c0_pins>;
 243                         clock-frequency = <400000>;
 244                         #address-cells = <1>;
 245                         #size-cells = <0>;
 246                         clocks = <&pismu TMPV770X_CLK_PII2C0>;
 247                         status = "disabled";
 248                 };
 249
 250                 i2c1: i2c@28031000 {
 251                         compatible = "snps,designware-i2c";
 252                         reg = <0 0x28031000 0 0x1000>;
 253                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 254                         pinctrl-names = "default";
 255                         pinctrl-0 = <&i2c1_pins>;
 256                         clock-frequency = <400000>;
 257                         #address-cells = <1>;
 258                         #size-cells = <0>;
 259                         clocks = <&pismu TMPV770X_CLK_PII2C1>;
 260                         status = "disabled";
 261                 };
 262
 263                 i2c2: i2c@28032000 {
 264                         compatible = "snps,designware-i2c";
 265                         reg = <0 0x28032000 0 0x1000>;
 266                         interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 267                         pinctrl-names = "default";
 268                         pinctrl-0 = <&i2c2_pins>;
 269                         clock-frequency = <400000>;
 270                         #address-cells = <1>;
 271                         #size-cells = <0>;
 272                         clocks = <&pismu TMPV770X_CLK_PII2C2>;
 273                         status = "disabled";
 274                 };
 275
 276                 i2c3: i2c@28033000 {
 277                         compatible = "snps,designware-i2c";
 278                         reg = <0 0x28033000 0 0x1000>;
 279                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 280                         pinctrl-names = "default";
 281                         pinctrl-0 = <&i2c3_pins>;
 282                         clock-frequency = <400000>;
 283                         #address-cells = <1>;
 284                         #size-cells = <0>;
 285                         clocks = <&pismu TMPV770X_CLK_PII2C3>;
 286                         status = "disabled";
 287                 };
 288
 289                 i2c4: i2c@28034000 {
 290                         compatible = "snps,designware-i2c";
 291                         reg = <0 0x28034000 0 0x1000>;
 292                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 293                         pinctrl-names = "default";
 294                         pinctrl-0 = <&i2c4_pins>;
 295                         clock-frequency = <400000>;
 296                         #address-cells = <1>;
 297                         #size-cells = <0>;
 298                         clocks = <&pismu TMPV770X_CLK_PII2C4>;
 299                         status = "disabled";
 300                 };
 301
 302                 i2c5: i2c@28035000 {
 303                         compatible = "snps,designware-i2c";
 304                         reg = <0 0x28035000 0 0x1000>;
 305                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 306                         pinctrl-names = "default";
 307                         pinctrl-0 = <&i2c5_pins>;
 308                         clock-frequency = <400000>;
 309                         #address-cells = <1>;
 310                         #size-cells = <0>;
 311                         clocks = <&pismu TMPV770X_CLK_PII2C5>;
 312                         status = "disabled";
 313                 };
 314
 315                 i2c6: i2c@28036000 {
 316                         compatible = "snps,designware-i2c";
 317                         reg = <0 0x28036000 0 0x1000>;
 318                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 319                         pinctrl-names = "default";
 320                         pinctrl-0 = <&i2c6_pins>;
 321                         clock-frequency = <400000>;
 322                         #address-cells = <1>;
 323                         #size-cells = <0>;
 324                         clocks = <&pismu TMPV770X_CLK_PII2C6>;
 325                         status = "disabled";
 326                 };
 327
 328                 i2c7: i2c@28037000 {
 329                         compatible = "snps,designware-i2c";
 330                         reg = <0 0x28037000 0 0x1000>;
 331                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 332                         pinctrl-names = "default";
 333                         pinctrl-0 = <&i2c7_pins>;
 334                         clock-frequency = <400000>;
 335                         #address-cells = <1>;
 336                         #size-cells = <0>;
 337                         clocks = <&pismu TMPV770X_CLK_PII2C7>;
 338                         status = "disabled";
 339                 };
 340
 341                 i2c8: i2c@28038000 {
 342                         compatible = "snps,designware-i2c";
 343                         reg = <0 0x28038000 0 0x1000>;
 344                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 345                         pinctrl-names = "default";
 346                         pinctrl-0 = <&i2c8_pins>;
 347                         clock-frequency = <400000>;
 348                         #address-cells = <1>;
 349                         #size-cells = <0>;
 350                         clocks = <&pismu TMPV770X_CLK_PII2C8>;
 351                         status = "disabled";
 352                 };
 353
 354                 spi0: spi@28140000 {
 355                         compatible = "arm,pl022", "arm,primecell";
 356                         reg = <0 0x28140000 0 0x1000>;
 357                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 358                         pinctrl-names = "default";
 359                         pinctrl-0 = <&spi0_pins>;
 360                         num-cs = <1>;
 361                         #address-cells = <1>;
 362                         #size-cells = <0>;
 363                         clocks = <&pismu TMPV770X_CLK_PISPI1>;
 364                         clock-names = "apb_pclk";
 365                         status = "disabled";
 366                 };
 367
 368                 spi1: spi@28141000 {
 369                         compatible = "arm,pl022", "arm,primecell";
 370                         reg = <0 0x28141000 0 0x1000>;
 371                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 372                         pinctrl-names = "default";
 373                         pinctrl-0 = <&spi1_pins>;
 374                         num-cs = <1>;
 375                         #address-cells = <1>;
 376                         #size-cells = <0>;
 377                         clocks = <&pismu TMPV770X_CLK_PISPI1>;
 378                         clock-names = "apb_pclk";
 379                         status = "disabled";
 380                 };
 381
 382                 spi2: spi@28142000 {
 383                         compatible = "arm,pl022", "arm,primecell";
 384                         reg = <0 0x28142000 0 0x1000>;
 385                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 386                         pinctrl-names = "default";
 387                         pinctrl-0 = <&spi2_pins>;
 388                         num-cs = <1>;
 389                         #address-cells = <1>;
 390                         #size-cells = <0>;
 391                         clocks = <&pismu TMPV770X_CLK_PISPI2>;
 392                         clock-names = "apb_pclk";
 393                         status = "disabled";
 394                 };
 395
 396                 spi3: spi@28143000 {
 397                         compatible = "arm,pl022", "arm,primecell";
 398                         reg = <0 0x28143000 0 0x1000>;
 399                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 400                         pinctrl-names = "default";
 401                         pinctrl-0 = <&spi3_pins>;
 402                         num-cs = <1>;
 403                         #address-cells = <1>;
 404                         #size-cells = <0>;
 405                         clocks = <&pismu TMPV770X_CLK_PISPI3>;
 406                         clock-names = "apb_pclk";
 407                         status = "disabled";
 408                 };
 409
 410                 spi4: spi@28144000 {
 411                         compatible = "arm,pl022", "arm,primecell";
 412                         reg = <0 0x28144000 0 0x1000>;
 413                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 414                         pinctrl-names = "default";
 415                         pinctrl-0 = <&spi4_pins>;
 416                         num-cs = <1>;
 417                         #address-cells = <1>;
 418                         #size-cells = <0>;
 419                         clocks = <&pismu TMPV770X_CLK_PISPI4>;
 420                         clock-names = "apb_pclk";
 421                         status = "disabled";
 422                 };
 423
 424                 spi5: spi@28145000 {
 425                         compatible = "arm,pl022", "arm,primecell";
 426                         reg = <0 0x28145000 0 0x1000>;
 427                         interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
 428                         pinctrl-names = "default";
 429                         pinctrl-0 = <&spi5_pins>;
 430                         num-cs = <1>;
 431                         #address-cells = <1>;
 432                         #size-cells = <0>;
 433                         clocks = <&pismu TMPV770X_CLK_PISPI5>;
 434                         clock-names = "apb_pclk";
 435                         status = "disabled";
 436                 };
 437
 438                 spi6: spi@28146000 {
 439                         compatible = "arm,pl022", "arm,primecell";
 440                         reg = <0 0x28146000 0 0x1000>;
 441                         interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
 442                         pinctrl-names = "default";
 443                         pinctrl-0 = <&spi6_pins>;
 444                         num-cs = <1>;
 445                         #address-cells = <1>;
 446                         #size-cells = <0>;
 447                         clocks = <&pismu TMPV770X_CLK_PISPI6>;
 448                         clock-names = "apb_pclk";
 449                         status = "disabled";
 450                 };
 451
 452                 piether: ethernet@28000000 {
 453                         compatible = "toshiba,visconti-dwmac", "snps,dwmac-4.20a";
 454                         reg = <0 0x28000000 0 0x10000>;
 455                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 456                         interrupt-names = "macirq";
 457                         snps,txpbl = <4>;
 458                         snps,rxpbl = <4>;
 459                         snps,tso;
 460                         clocks = <&pismu TMPV770X_CLK_PIETHER_BUS>, <&pismu TMPV770X_CLK_PIETHER_125M>;
 461                         clock-names = "stmmaceth", "phy_ref_clk";
 462                         status = "disabled";
 463                 };
 464
 465                 wdt: wdt@28330000 {
 466                         compatible = "toshiba,visconti-wdt";
 467                         reg = <0 0x28330000 0 0x1000>;
 468                         clocks = <&pismu TMPV770X_CLK_WDTCLK>;
 469                         status = "disabled";
 470                 };
 471
 472                 pwm: pwm@241c0000 {
 473                         compatible = "toshiba,visconti-pwm";
 474                         reg = <0 0x241c0000 0 0x1000>;
 475                         pinctrl-names = "default";
 476                         pinctrl-0 = <&pwm_mux>;
 477                         #pwm-cells = <2>;
 478                         status = "disabled";
 479                 };
 480
 481                 pcie: pcie@28400000 {
 482                         compatible = "toshiba,visconti-pcie";
 483                         reg = <0x0 0x28400000 0x0 0x00400000>,
 484                               <0x0 0x70000000 0x0 0x10000000>,
 485                               <0x0 0x28050000 0x0 0x00010000>,
 486                               <0x0 0x24200000 0x0 0x00002000>,
 487                               <0x0 0x24162000 0x0 0x00001000>;
 488                         reg-names = "dbi", "config", "ulreg", "smu", "mpu";
 489                         device_type = "pci";
 490                         bus-range = <0x00 0xff>;
 491                         num-lanes = <2>;
 492                         num-viewport = <8>;
 493
 494                         #address-cells = <3>;
 495                         #size-cells = <2>;
 496                         #interrupt-cells = <1>;
 497                         ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000
 498                                   0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>;
 499                         interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 500                                      <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
 501                         interrupt-names = "msi", "intr";
 502                         interrupt-map-mask = <0 0 0 7>;
 503                         interrupt-map =
 504                                 <0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
 505                                  0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
 506                                  0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
 507                                  0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
 508                         max-link-speed = <2>;
 509                         clocks = <&extclk100mhz>, <&pismu TMPV770X_CLK_PCIE_MSTR>, <&pismu TMPV770X_CLK_PCIE_AUX>;
 510                         clock-names = "ref", "core", "aux";
 511                         status = "disabled";
 512                 };
 513         };
 514 };
 515
 516 #include "tmpv7708_pins.dtsi"