src/mips/ingenic/jz4740.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/jz4740-cgu.h>
   3 #include <dt-bindings/clock/ingenic,tcu.h>
   4
   5 / {
   6         #address-cells = <1>;
   7         #size-cells = <1>;
   8         compatible = "ingenic,jz4740";
   9
  10         cpuintc: interrupt-controller {
  11                 #address-cells = <0>;
  12                 #interrupt-cells = <1>;
  13                 interrupt-controller;
  14                 compatible = "mti,cpu-interrupt-controller";
  15         };
  16
  17         intc: interrupt-controller@10001000 {
  18                 compatible = "ingenic,jz4740-intc";
  19                 reg = <0x10001000 0x14>;
  20
  21                 interrupt-controller;
  22                 #interrupt-cells = <1>;
  23
  24                 interrupt-parent = <&cpuintc>;
  25                 interrupts = <2>;
  26         };
  27
  28         ext: ext {
  29                 compatible = "fixed-clock";
  30                 #clock-cells = <0>;
  31         };
  32
  33         rtc: rtc {
  34                 compatible = "fixed-clock";
  35                 #clock-cells = <0>;
  36                 clock-frequency = <32768>;
  37         };
  38
  39         cgu: jz4740-cgu@10000000 {
  40                 compatible = "ingenic,jz4740-cgu";
  41                 reg = <0x10000000 0x100>;
  42
  43                 clocks = <&ext>, <&rtc>;
  44                 clock-names = "ext", "rtc";
  45
  46                 #clock-cells = <1>;
  47         };
  48
  49         tcu: timer@10002000 {
  50                 compatible = "ingenic,jz4740-tcu", "simple-mfd";
  51                 reg = <0x10002000 0x1000>;
  52                 #address-cells = <1>;
  53                 #size-cells = <1>;
  54                 ranges = <0x0 0x10002000 0x1000>;
  55
  56                 #clock-cells = <1>;
  57
  58                 clocks = <&cgu JZ4740_CLK_RTC>,
  59                          <&cgu JZ4740_CLK_EXT>,
  60                          <&cgu JZ4740_CLK_PCLK>,
  61                          <&cgu JZ4740_CLK_TCU>;
  62                 clock-names = "rtc", "ext", "pclk", "tcu";
  63
  64                 interrupt-controller;
  65                 #interrupt-cells = <1>;
  66
  67                 interrupt-parent = <&intc>;
  68                 interrupts = <23 22 21>;
  69
  70                 watchdog: watchdog@0 {
  71                         compatible = "ingenic,jz4740-watchdog";
  72                         reg = <0x0 0xc>;
  73
  74                         clocks = <&tcu TCU_CLK_WDT>;
  75                         clock-names = "wdt";
  76                 };
  77
  78                 pwm: pwm@40 {
  79                         compatible = "ingenic,jz4740-pwm";
  80                         reg = <0x40 0x80>;
  81
  82                         #pwm-cells = <3>;
  83
  84                         clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
  85                                  <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
  86                                  <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
  87                                  <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
  88                         clock-names = "timer0", "timer1", "timer2", "timer3",
  89                                       "timer4", "timer5", "timer6", "timer7";
  90                 };
  91         };
  92
  93         rtc_dev: rtc@10003000 {
  94                 compatible = "ingenic,jz4740-rtc";
  95                 reg = <0x10003000 0x40>;
  96
  97                 interrupt-parent = <&intc>;
  98                 interrupts = <15>;
  99
 100                 clocks = <&cgu JZ4740_CLK_RTC>;
 101                 clock-names = "rtc";
 102         };
 103
 104         pinctrl: pin-controller@10010000 {
 105                 compatible = "ingenic,jz4740-pinctrl";
 106                 reg = <0x10010000 0x400>;
 107
 108                 #address-cells = <1>;
 109                 #size-cells = <0>;
 110
 111                 gpa: gpio@0 {
 112                         compatible = "ingenic,jz4740-gpio";
 113                         reg = <0>;
 114
 115                         gpio-controller;
 116                         gpio-ranges = <&pinctrl 0 0 32>;
 117                         #gpio-cells = <2>;
 118
 119                         interrupt-controller;
 120                         #interrupt-cells = <2>;
 121
 122                         interrupt-parent = <&intc>;
 123                         interrupts = <28>;
 124                 };
 125
 126                 gpb: gpio@1 {
 127                         compatible = "ingenic,jz4740-gpio";
 128                         reg = <1>;
 129
 130                         gpio-controller;
 131                         gpio-ranges = <&pinctrl 0 32 32>;
 132                         #gpio-cells = <2>;
 133
 134                         interrupt-controller;
 135                         #interrupt-cells = <2>;
 136
 137                         interrupt-parent = <&intc>;
 138                         interrupts = <27>;
 139                 };
 140
 141                 gpc: gpio@2 {
 142                         compatible = "ingenic,jz4740-gpio";
 143                         reg = <2>;
 144
 145                         gpio-controller;
 146                         gpio-ranges = <&pinctrl 0 64 32>;
 147                         #gpio-cells = <2>;
 148
 149                         interrupt-controller;
 150                         #interrupt-cells = <2>;
 151
 152                         interrupt-parent = <&intc>;
 153                         interrupts = <26>;
 154                 };
 155
 156                 gpd: gpio@3 {
 157                         compatible = "ingenic,jz4740-gpio";
 158                         reg = <3>;
 159
 160                         gpio-controller;
 161                         gpio-ranges = <&pinctrl 0 96 32>;
 162                         #gpio-cells = <2>;
 163
 164                         interrupt-controller;
 165                         #interrupt-cells = <2>;
 166
 167                         interrupt-parent = <&intc>;
 168                         interrupts = <25>;
 169                 };
 170         };
 171
 172         aic: audio-controller@10020000 {
 173                 compatible = "ingenic,jz4740-i2s";
 174                 reg = <0x10020000 0x38>;
 175
 176                 #sound-dai-cells = <0>;
 177
 178                 interrupt-parent = <&intc>;
 179                 interrupts = <18>;
 180
 181                 clocks = <&cgu JZ4740_CLK_AIC>,
 182                          <&cgu JZ4740_CLK_I2S>,
 183                          <&cgu JZ4740_CLK_EXT>,
 184                          <&cgu JZ4740_CLK_PLL_HALF>;
 185                 clock-names = "aic", "i2s", "ext", "pll half";
 186
 187                 dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>;
 188                 dma-names = "rx", "tx";
 189         };
 190
 191         codec: audio-codec@100200a4 {
 192                 compatible = "ingenic,jz4740-codec";
 193                 reg = <0x10020080 0x8>;
 194
 195                 #sound-dai-cells = <0>;
 196
 197                 clocks = <&cgu JZ4740_CLK_AIC>;
 198                 clock-names = "aic";
 199         };
 200
 201         mmc: mmc@10021000 {
 202                 compatible = "ingenic,jz4740-mmc";
 203                 reg = <0x10021000 0x1000>;
 204
 205                 clocks = <&cgu JZ4740_CLK_MMC>;
 206                 clock-names = "mmc";
 207
 208                 interrupt-parent = <&intc>;
 209                 interrupts = <14>;
 210
 211                 dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>;
 212                 dma-names = "rx", "tx";
 213
 214                 cap-sd-highspeed;
 215                 cap-mmc-highspeed;
 216                 cap-sdio-irq;
 217         };
 218
 219         uart0: serial@10030000 {
 220                 compatible = "ingenic,jz4740-uart";
 221                 reg = <0x10030000 0x100>;
 222
 223                 interrupt-parent = <&intc>;
 224                 interrupts = <9>;
 225
 226                 clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;
 227                 clock-names = "baud", "module";
 228         };
 229
 230         uart1: serial@10031000 {
 231                 compatible = "ingenic,jz4740-uart";
 232                 reg = <0x10031000 0x100>;
 233
 234                 interrupt-parent = <&intc>;
 235                 interrupts = <8>;
 236
 237                 clocks = <&ext>, <&cgu JZ4740_CLK_UART1>;
 238                 clock-names = "baud", "module";
 239         };
 240
 241         adc: adc@10070000 {
 242                 compatible = "ingenic,jz4740-adc";
 243                 reg = <0x10070000 0x30>;
 244                 #io-channel-cells = <1>;
 245
 246                 clocks = <&cgu JZ4740_CLK_ADC>;
 247                 clock-names = "adc";
 248
 249                 interrupt-parent = <&intc>;
 250                 interrupts = <12>;
 251         };
 252
 253         nemc: memory-controller@13010000 {
 254                 compatible = "ingenic,jz4740-nemc";
 255                 reg = <0x13010000 0x54>;
 256                 #address-cells = <2>;
 257                 #size-cells = <1>;
 258                 ranges = <1 0 0x18000000 0x4000000>,
 259                          <2 0 0x14000000 0x4000000>,
 260                          <3 0 0x0c000000 0x4000000>,
 261                          <4 0 0x08000000 0x4000000>;
 262
 263                 clocks = <&cgu JZ4740_CLK_MCLK>;
 264         };
 265
 266         ecc: ecc-controller@13010100 {
 267                 compatible = "ingenic,jz4740-ecc";
 268                 reg = <0x13010100 0x2C>;
 269
 270                 clocks = <&cgu JZ4740_CLK_MCLK>;
 271         };
 272
 273         dmac: dma-controller@13020000 {
 274                 compatible = "ingenic,jz4740-dma";
 275                 reg = <0x13020000 0xbc>, <0x13020300 0x14>;
 276                 #dma-cells = <2>;
 277
 278                 interrupt-parent = <&intc>;
 279                 interrupts = <20>;
 280
 281                 clocks = <&cgu JZ4740_CLK_DMA>;
 282         };
 283
 284         uhc: uhc@13030000 {
 285                 compatible = "ingenic,jz4740-ohci", "generic-ohci";
 286                 reg = <0x13030000 0x1000>;
 287
 288                 clocks = <&cgu JZ4740_CLK_UHC>;
 289                 assigned-clocks = <&cgu JZ4740_CLK_UHC>;
 290                 assigned-clock-rates = <48000000>;
 291
 292                 interrupt-parent = <&intc>;
 293                 interrupts = <3>;
 294
 295                 status = "disabled";
 296         };
 297
 298         udc: usb@13040000 {
 299                 compatible = "ingenic,jz4740-musb";
 300                 reg = <0x13040000 0x10000>;
 301
 302                 interrupt-parent = <&intc>;
 303                 interrupts = <24>;
 304                 interrupt-names = "mc";
 305
 306                 clocks = <&cgu JZ4740_CLK_UDC>;
 307                 clock-names = "udc";
 308         };
 309
 310         lcd: lcd-controller@13050000 {
 311                 compatible = "ingenic,jz4740-lcd";
 312                 reg = <0x13050000 0x1000>;
 313
 314                 interrupt-parent = <&intc>;
 315                 interrupts = <30>;
 316
 317                 clocks = <&cgu JZ4740_CLK_LCD_PCLK>, <&cgu JZ4740_CLK_LCD>;
 318                 clock-names = "lcd_pclk", "lcd";
 319         };
 320 };