2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the acknowledgement as bellow:
17 * This product includes software developed by K. Kobayashi and H. Shimokawa
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
40 #include <bootstrap.h>
42 #include <dev/firewire/firewire.h>
44 #include <dev/firewire/fwohcireg.h>
45 #include <dev/firewire/firewire_phy.h>
47 static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t);
48 static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t);
52 #define device_printf(a, x, ...) printf("FW1394: " x, ## __VA_ARGS__)
54 #define device_printf(a, x, ...)
58 #define DELAY(x) delay(x)
61 #define MAXREC(x) (2 << (x))
63 "S100", "S200", "S400", "S800",
64 "S1600", "S3200", "undef", "undef"
68 * Communication with PHY device
71 fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data)
78 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA));
79 OWRITE(sc, OHCI_PHYACCESS, fun);
82 return(fwphy_rddata( sc, addr));
86 fwphy_rddata(struct fwohci_softc *sc, u_int addr)
94 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL);
95 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR);
96 OWRITE(sc, OHCI_PHYACCESS, fun);
97 for ( i = 0 ; i < MAX_RETRY ; i ++ ){
98 fun = OREAD(sc, OHCI_PHYACCESS);
99 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0)
105 device_printf(sc->fc.dev, "phy read failed(1).\n");
106 if (++retry < MAX_RETRY) {
111 /* Make sure that SCLK is started */
112 stat = OREAD(sc, FWOHCI_INTSTAT);
113 if ((stat & OHCI_INT_REG_FAIL) != 0 ||
114 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) {
116 device_printf(sc->fc.dev, "phy read failed(2).\n");
117 if (++retry < MAX_RETRY) {
122 if (firewire_debug || retry >= MAX_RETRY)
123 device_printf(sc->fc.dev,
124 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry);
126 return((fun >> PHYDEV_RDDATA )& 0xff);
131 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev)
137 * probe PHY parameters
138 * 0. to prove PHY version, whether compliance of 1394a.
139 * 1. to probe maximum speed supported by the PHY and
140 * number of port supported by core-logic.
141 * It is not actually available port on your PC .
143 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
146 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
148 if((reg >> 5) != 7 ){
149 nport = reg & FW_PHY_NP;
150 speed = reg & FW_PHY_SPD >> 6;
151 if (speed > MAX_SPEED) {
152 device_printf(dev, "invalid speed %d (fixed to %d).\n",
157 "Phy 1394 only %s, %d ports.\n",
158 linkspeed[speed], nport);
160 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG);
161 nport = reg & FW_PHY_NP;
162 speed = (reg2 & FW_PHY_ESPD) >> 5;
163 if (speed > MAX_SPEED) {
164 device_printf(dev, "invalid speed %d (fixed to %d).\n",
169 "Phy 1394a available %s, %d ports.\n",
170 linkspeed[speed], nport);
172 /* check programPhyEnable */
173 reg2 = fwphy_rddata(sc, 5);
175 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
176 #else /* XXX force to enable 1394a */
181 "Enable 1394a Enhancements\n");
184 /* set aPhyEnhanceEnable */
185 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN);
186 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY);
191 reg2 = fwphy_wrdata(sc, 5, reg2);
195 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
196 if((reg >> 5) == 7 ){
197 reg = fwphy_rddata(sc, 4);
199 fwphy_wrdata(sc, 4, reg);
200 reg = fwphy_rddata(sc, 4);
207 fwohci_reset(struct fwohci_softc *sc, device_t dev)
209 int i, max_rec, speed;
212 /* Disable interrupts */
213 OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
215 /* FLUSH FIFO and reset Transmitter/Receiver */
216 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
218 device_printf(dev, "resetting OHCI...");
220 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
221 if (i++ > 100) break;
225 printf("done (loop=%d)\n", i);
228 fwohci_probe_phy(sc, dev);
231 reg = OREAD(sc, OHCI_BUS_OPT);
232 reg2 = reg | OHCI_BUSFNC;
233 max_rec = (reg & 0x0000f000) >> 12;
234 speed = (reg & 0x00000007);
235 device_printf(dev, "Link %s, max_rec %d bytes.\n",
236 linkspeed[speed], MAXREC(max_rec));
237 /* XXX fix max_rec */
238 sc->maxrec = sc->speed + 8;
239 if (max_rec != sc->maxrec) {
240 reg2 = (reg2 & 0xffff0fff) | (sc->maxrec << 12);
241 device_printf(dev, "max_rec %d -> %d\n",
242 MAXREC(max_rec), MAXREC(sc->maxrec));
245 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
246 OWRITE(sc, OHCI_BUS_OPT, reg2);
248 /* Initialize registers */
249 OWRITE(sc, OHCI_CROMHDR, sc->config_rom[0]);
250 OWRITE(sc, OHCI_CROMPTR, VTOP(sc->config_rom));
252 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr);
254 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
255 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
257 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID);
261 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN);
265 fwohci_init(struct fwohci_softc *sc, device_t dev)
272 reg = OREAD(sc, OHCI_VERSION);
273 mver = (reg >> 16) & 0xff;
274 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n",
275 mver, reg & 0xff, (reg>>24) & 1);
276 if (mver < 1 || mver > 9) {
277 device_printf(dev, "invalid OHCI version\n");
281 /* Available Isochronous DMA channel probe */
282 OWRITE(sc, OHCI_IT_MASK, 0xffffffff);
283 OWRITE(sc, OHCI_IR_MASK, 0xffffffff);
284 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK);
285 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff);
286 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff);
287 for (i = 0; i < 0x20; i++)
288 if ((reg & (1 << i)) == 0)
290 device_printf(dev, "No. of Isochronous channels is %d.\n", i);
295 /* SID receive buffer must align 2^11 */
296 #define OHCI_SIDSIZE (1 << 11)
297 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE,
298 &sc->sid_dma, BUS_DMA_WAITOK);
299 if (sc->sid_buf == NULL) {
300 device_printf(dev, "sid_buf alloc failed.");
305 sc->eui.hi = OREAD(sc, FWOHCIGUID_H);
306 sc->eui.lo = OREAD(sc, FWOHCIGUID_L);
307 for( i = 0 ; i < 8 ; i ++)
308 ui[i] = FW_EUI64_BYTE(&sc->eui,i);
309 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
310 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]);
311 fwohci_reset(sc, dev);
317 fwohci_ibr(struct fwohci_softc *sc)
321 device_printf(sc->dev, "Initiate bus reset\n");
324 * Make sure our cached values from the config rom are
327 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->config_rom[0]));
328 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->config_rom[2]));
331 * Set root hold-off bit so that non cyclemaster capable node
332 * shouldn't became the root node.
335 fun = fwphy_rddata(sc, FW_PHY_IBR_REG);
337 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun);
338 #else /* Short bus reset */
339 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG);
341 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun);
347 fwohci_sid(struct fwohci_softc *sc)
352 node_id = OREAD(sc, FWOHCI_NODEID);
353 if (!(node_id & OHCI_NODE_VALID)) {
355 printf("Bus reset failure\n");
360 /* Enable bus reset interrupt */
361 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R);
362 /* Allow async. request to us */
363 OWRITE(sc, OHCI_AREQHI, 1 << 31);
364 /* XXX insecure ?? */
365 OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
366 OWRITE(sc, OHCI_PREQLO, 0xffffffff);
367 OWRITE(sc, OHCI_PREQUPPER, 0x10000);
368 /* Set ATRetries register */
369 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff);
371 ** Checking whether the node is root or not. If root, turn on
374 plen = OREAD(sc, OHCI_SID_CNT);
375 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ",
376 node_id, (plen >> 16) & 0xff);
377 if (node_id & OHCI_NODE_ROOT) {
378 device_printf(sc->dev, "CYCLEMASTER mode\n");
379 OWRITE(sc, OHCI_LNKCTL,
380 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER);
382 device_printf(sc->dev, "non CYCLEMASTER mode\n");
383 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR);
384 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER);
386 if (plen & OHCI_SID_ERR) {
387 device_printf(fc->dev, "SID Error\n");
390 device_printf(sc->dev, "bus reset phase done\n");
391 sc->state = FWOHCI_STATE_NORMAL;
395 fwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count)
400 if(stat & OREAD(sc, FWOHCI_INTMASK))
404 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
405 stat & OHCI_INT_EN ? "DMA_EN ":"",
406 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
407 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
408 stat & OHCI_INT_ERR ? "INT_ERR ":"",
409 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
410 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",
411 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"",
412 stat & OHCI_INT_CYC_START ? "CYC_START ":"",
413 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"",
414 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"",
415 stat & OHCI_INT_PHY_SID ? "SID ":"",
416 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"",
417 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"",
418 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"",
419 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"",
420 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"",
421 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"",
422 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"",
423 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"",
424 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"",
425 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"",
426 stat, OREAD(sc, FWOHCI_INTMASK)
430 if(stat & OHCI_INT_PHY_BUS_R ){
431 device_printf(fc->dev, "BUS reset\n");
432 if (sc->state == FWOHCI_STATE_BUSRESET)
434 sc->state = FWOHCI_STATE_BUSRESET;
435 /* Disable bus reset interrupt until sid recv. */
436 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R);
438 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
439 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);
441 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->config_rom[0]));
442 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->config_rom[2]));
443 } else if (sc->state == FWOHCI_STATE_BUSRESET) {
451 fwochi_check_stat(struct fwohci_softc *sc)
455 stat = OREAD(sc, FWOHCI_INTSTAT);
456 if (stat == 0xffffffff) {
457 device_printf(sc->fc.dev,
458 "device physically ejected?\n");
462 OWRITE(sc, FWOHCI_INTSTATCLR, stat);
467 fwohci_poll(struct fwohci_softc *sc)
471 stat = fwochi_check_stat(sc);
472 if (stat != 0xffffffff)
473 fwohci_intr_body(sc, stat, 1);