2 * Copyright (c) 2007 Hidetoshi Shimokawa
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the acknowledgement as bellow:
16 * This product includes software developed by K. Kobayashi and H. Shimokawa
18 * 4. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
38 #define CROMSIZE 0x400
47 struct crom_src_buf *crom_src_buf;
48 struct crom_src *crom_src;
49 struct crom_chunk *crom_root;
54 char config_rom_buf[CROMSIZE*2]; /* double size for alignment */
57 int fwohci_init(struct fwohci_softc *, int);
58 void fwohci_ibr(struct fwohci_softc *);
59 void fwohci_poll(struct fwohci_softc *);
61 #define FWOHCI_STATE_DEAD (-1)
62 #define FWOHCI_STATE_INIT 0
63 #define FWOHCI_STATE_ENABLED 1
64 #define FWOHCI_STATE_BUSRESET 2
65 #define FWOHCI_STATE_NORMAL 3
67 #define OREAD(f, o) (*(volatile uint32_t *)((f)->handle + (o)))
68 #define OWRITE(f, o, v) (*(volatile uint32_t *)((f)->handle + (o)) = (v))
70 #define OHCI_VERSION 0x00
71 #define OHCI_ATRETRY 0x08
72 #define OHCI_CROMHDR 0x18
73 #define OHCI_BUS_ID 0x1c
74 #define OHCI_BUS_OPT 0x20
75 #define OHCI_BUSIRMC (1U << 31)
76 #define OHCI_BUSCMC (1 << 30)
77 #define OHCI_BUSISC (1 << 29)
78 #define OHCI_BUSBMC (1 << 28)
79 #define OHCI_BUSPMC (1 << 27)
80 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\
81 OHCI_BUSBMC | OHCI_BUSPMC
83 #define OHCI_EUID_HI 0x24
84 #define OHCI_EUID_LO 0x28
86 #define OHCI_CROMPTR 0x34
87 #define OHCI_HCCCTL 0x50
88 #define OHCI_HCCCTLCLR 0x54
89 #define OHCI_AREQHI 0x100
90 #define OHCI_AREQHICLR 0x104
91 #define OHCI_AREQLO 0x108
92 #define OHCI_AREQLOCLR 0x10c
93 #define OHCI_PREQHI 0x110
94 #define OHCI_PREQHICLR 0x114
95 #define OHCI_PREQLO 0x118
96 #define OHCI_PREQLOCLR 0x11c
97 #define OHCI_PREQUPPER 0x120
99 #define OHCI_SID_BUF 0x64
100 #define OHCI_SID_CNT 0x68
101 #define OHCI_SID_ERR (1U << 31)
102 #define OHCI_SID_CNT_MASK 0xffc
104 #define OHCI_IT_STAT 0x90
105 #define OHCI_IT_STATCLR 0x94
106 #define OHCI_IT_MASK 0x98
107 #define OHCI_IT_MASKCLR 0x9c
109 #define OHCI_IR_STAT 0xa0
110 #define OHCI_IR_STATCLR 0xa4
111 #define OHCI_IR_MASK 0xa8
112 #define OHCI_IR_MASKCLR 0xac
114 #define OHCI_LNKCTL 0xe0
115 #define OHCI_LNKCTLCLR 0xe4
117 #define OHCI_PHYACCESS 0xec
118 #define OHCI_CYCLETIMER 0xf0
120 #define OHCI_DMACTL(off) (off)
121 #define OHCI_DMACTLCLR(off) (off + 4)
122 #define OHCI_DMACMD(off) (off + 0xc)
123 #define OHCI_DMAMATCH(off) (off + 0x10)
125 #define OHCI_ATQOFF 0x180
126 #define OHCI_ATQCTL OHCI_ATQOFF
127 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4)
128 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc)
129 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10)
131 #define OHCI_ATSOFF 0x1a0
132 #define OHCI_ATSCTL OHCI_ATSOFF
133 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4)
134 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc)
135 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10)
137 #define OHCI_ARQOFF 0x1c0
138 #define OHCI_ARQCTL OHCI_ARQOFF
139 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4)
140 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc)
141 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10)
143 #define OHCI_ARSOFF 0x1e0
144 #define OHCI_ARSCTL OHCI_ARSOFF
145 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4)
146 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc)
147 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10)
149 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH))
150 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH))
151 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4)
152 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc)
154 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH))
155 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH))
156 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4)
157 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc)
158 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10)