2 * Copyright (c) 2011-2014 Robert N. M. Watson
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * MIPS segment definitions.
36 __mips_ckseg_cached__ = 0xffffffff80000000; /* BSD kernel here. */
37 __mips64_xkphys_cached__ = 0x9800000000000000; /* Device memory here. */
38 __mips64_xkphys_uncached__ = 0x9000000000000000; /* Device I/O here. */
41 * Physical addresses of various peripherals.
43 __cheri_flash_base__ = 0x74000000;
44 __cheri_sdcard_base__ = 0x7f008000;
47 * Location of boot2 in flash.
49 __cheri_flash_boot_loader_base_ = 0x03fe0000;
50 __cheri_flash_boot_loader_vaddr__ = __mips64_xkphys_cached__ +
51 __cheri_flash_base__ + __cheri_flash_boot_loader_base_;
54 * Location of boot file system in flash.
56 __cheri_flash_bootfs_base__ = 0x1820000;
57 __cheri_flash_bootfs_len__ = 0x27c0000;
58 __cheri_flash_bootfs_vaddr__ = __mips64_xkphys_cached__ +
59 __cheri_flash_base__ + __cheri_flash_bootfs_base__;
62 * Location of SD card controller.
64 __cheri_sdcard_vaddr__ = __mips64_xkphys_uncached__ + __cheri_sdcard_base__;
67 * Location where the production kernel gets put. This must agree with other
68 * definitions, such as in the kernel's own linker script.
70 * (As it happens, in the short run, we also place boot2 here, as Miniboot
71 * expects to find an ELF binary there -- but that will change.)
73 __kernel_base__ = 0x100000;
74 __kernel_vaddr__ = __mips64_xkphys_cached__ + __kernel_base__;