2 * Copyright (c) 2011 Robert N. M. Watson
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 typedef unsigned long register_t; /* 64-bit MIPS register */
42 typedef unsigned long paddr_t; /* Physical address */
43 typedef unsigned long vaddr_t; /* Virtual address */
46 typedef unsigned char uint8_t;
47 typedef unsigned short uint16_t;
48 typedef unsigned int uint32_t;
49 typedef unsigned long uint64_t;
53 * MIPS address space layout.
55 #define MIPS_XKPHYS_UNCACHED_BASE 0x9000000000000000
56 #define MIPS_XKPHYS_CACHED_NC_BASE 0x9800000000000000
59 mips_phys_to_cached(paddr_t phys)
62 return (phys | MIPS_XKPHYS_CACHED_NC_BASE);
66 mips_phys_to_uncached(paddr_t phys)
69 return (phys | MIPS_XKPHYS_UNCACHED_BASE);
73 * Endian conversion routines for use in I/O -- most Altera devices are little
74 * endian, but our processor is big endian.
76 static inline uint16_t
77 byteswap16(uint16_t v)
80 return ((v & 0xff00) >> 8 | (v & 0xff) << 8);
83 static inline uint32_t
84 byteswap32(uint32_t v)
87 return ((v & 0xff000000) >> 24 | (v & 0x00ff0000) >> 8 |
88 (v & 0x0000ff00) << 8 | (v & 0x000000ff) << 24);
92 * MIPS simple I/O routines -- arguments are virtual addresses so that the
93 * caller can determine required caching properties.
96 mips_ioread_uint8(vaddr_t vaddr)
100 __asm__ __volatile__ ("lb %0, 0(%1)" : "=r" (v) : "r" (vaddr));
105 mips_iowrite_uint8(vaddr_t vaddr, uint8_t v)
108 __asm__ __volatile__ ("sb %0, 0(%1)" : : "r" (v), "r" (vaddr));
111 static inline uint32_t
112 mips_ioread_uint32(vaddr_t vaddr)
116 __asm__ __volatile__ ("lw %0, 0(%1)" : "=r" (v) : "r" (vaddr));
121 mips_iowrite_uint32(vaddr_t vaddr, uint32_t v)
124 __asm__ __volatile__ ("sw %0, 0(%1)" : : "r" (v), "r" (vaddr));
128 * Little-endian versions of 32-bit I/O routines.
130 static inline uint32_t
131 mips_ioread_uint32le(vaddr_t vaddr)
134 return (byteswap32(mips_ioread_uint32(vaddr)));
138 mips_iowrite_uint32le(vaddr_t vaddr, uint32_t v)
141 mips_iowrite_uint32(vaddr, byteswap32(v));
145 * Coprocessor 0 interfaces.
147 static inline register_t
152 __asm__ __volatile__ ("dmfc0 %0, $9" : "=r" (count));