1 /* $NetBSD: dec_1000a.c,v 1.5 1999/04/15 22:06:47 thorpej Exp $ */
4 * Copyright (c) 1998 The NetBSD Foundation, Inc.
7 * This code is based on dec_kn20aa.c, written by Chris G. Demetriou at
8 * Carnegie-Mellon University. Platform support for Noritake, Pintake, and
9 * Corelle by Ross Harvey with copyright assignment by permission of Avalon
10 * Computer Systems, Inc.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the NetBSD
23 * Foundation, Inc. and its contributors.
24 * 4. Neither the name of The NetBSD Foundation nor the names of its
25 * contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
42 * Copyright (c) 1995, 1996, 1997 Carnegie-Mellon University.
43 * All rights reserved.
45 * Author: Chris G. Demetriou
47 * Permission to use, copy, modify and distribute this software and
48 * its documentation is hereby granted, provided that both the copyright
49 * notice and this permission notice appear in all copies of the
50 * software, derivative works or modified versions, and any portions
51 * thereof, and that both notices appear in supporting documentation.
53 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
54 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
55 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
57 * Carnegie Mellon requests users of this software to return to
59 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
60 * School of Computer Science
61 * Carnegie Mellon University
62 * Pittsburgh PA 15213-3890
64 * any improvements or extensions that they make and grant Carnegie the
65 * rights to redistribute these changes.
68 * Additional Copyright (c) 1997 by Matthew Jacob for NASA/Ames Research Center
71 * Additional Copyright (c) 1999 by Andrew Gallatin
78 #include <sys/param.h>
79 #include <sys/systm.h>
80 #include <sys/termios.h>
82 #include <machine/rpb.h>
83 #include <machine/cpuconf.h>
84 #include <machine/clock.h>
86 #include <alpha/pci/apecsvar.h>
87 #include <alpha/pci/ciavar.h>
89 #include <pci/pcivar.h>
96 #define CONSPEED TTYDEF_SPEED
98 static int comcnrate = CONSPEED;
100 void dec_1000a_init __P((int));
101 static void dec_1000a_cons_init __P((void));
104 static void dec_1000_intr_map __P((void *));
105 static void dec_1000_intr_disable __P((int));
106 static void dec_1000_intr_enable __P((int));
107 static void dec_1000_intr_init __P((void));
109 static void dec_1000a_intr_map __P((void *));
110 static void dec_1000a_intr_disable __P((int));
111 static void dec_1000a_intr_enable __P((int));
112 static void dec_1000a_intr_init __P((void));
114 extern int siocnattach __P((int, int));
115 extern int siogdbattach __P((int, int));
116 extern int sccnattach __P((void));
119 static const struct alpha_variation_table dec_1000_variations[] = {
120 { 0, "AlphaServer 1000" },
124 static const struct alpha_variation_table dec_1000a_variations[] = {
125 { 0, "AlphaServer 1000A" },
130 dec_1000a_init(int cputype)
134 platform.family = "AlphaServer 1000/1000A";
136 if ((platform.model = alpha_dsr_sysname()) == NULL) {
137 variation = hwrpb->rpb_variation & SV_ST_MASK;
138 if ((platform.model = alpha_variation_name(variation,
139 cputype == ST_DEC_1000 ? dec_1000_variations
140 : dec_1000a_variations)) == NULL)
141 platform.model = alpha_unknown_sysname();
144 switch(LOCATE_PCS(hwrpb, 0)->pcs_proc_type & PCS_PROC_MAJOR) {
147 platform.iobus = "apecs";
148 platform.pci_intr_map = dec_1000_intr_map;
149 platform.pci_intr_disable = dec_1000_intr_disable;
150 platform.pci_intr_enable = dec_1000_intr_enable;
151 platform.pci_intr_init = dec_1000_intr_init;
155 platform.iobus = "cia";
156 platform.pci_intr_map = dec_1000a_intr_map;
157 platform.pci_intr_disable = dec_1000a_intr_disable;
158 platform.pci_intr_enable = dec_1000a_intr_enable;
159 platform.pci_intr_init = dec_1000a_intr_init;
162 platform.cons_init = dec_1000a_cons_init;
165 extern int comconsole; /* XXX for forcing comconsole when srm serial console is used */
167 dec_1000a_cons_init()
171 if(strcmp(platform.iobus, "cia") == 0) {
178 siogdbattach(0x2f8, 57600);
181 ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off);
183 switch (ctb->ctb_term_type) {
185 /* serial console ... */
189 * Delay to allow PROM putchars to complete.
190 * FIFO depth * character time,
191 * character time = (1000000 / (defaultrate / 10))
193 DELAY(160000000 / comcnrate);
196 * force a comconsole on com1 if the SRM has a serial
200 if (siocnattach(0x3f8, comcnrate))
201 panic("can't init serial console");
207 /* display console ... */
212 panic("not configured to use display && keyboard console");
217 printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type);
218 printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot);
220 panic("consinit: unknown console type %d\n",
221 (int) ctb->ctb_term_type);
227 dec_1000_intr_map(arg)
230 pcicfgregs *cfg = (pcicfgregs *)arg;
232 if (cfg->intpin == 0) /* No IRQ used. */
234 if (!(1 <= cfg->intpin && cfg->intpin <= 4))
241 cfg->intline = 0xc; /* integrated ncr scsi */
247 cfg->intline = (cfg->slot - 11) * 4 + cfg->intpin - 1;
251 bad: printf("dec_1000_intr_map: can't map dev %d pin %d\n",
252 cfg->slot, cfg->intpin);
257 * Read and write the mystery ICU IMR registers
258 * on the AlphaServer 1000
261 #define IR() inw(0x536)
262 #define IW(x) outw(0x536, (x))
265 * Enable and disable interrupts at the ICU level
269 dec_1000_intr_enable(irq)
276 dec_1000_intr_disable(irq)
279 IW(IR() & ~(1 << irq));
287 * Initialize mystery ICU
291 * Enable cascade interrupt.
293 dec_1000_intr_enable(2);
297 * Read and write the mystery ICU IMR registers
298 * on the AlphaServer 1000a
301 #define IRA(o) inw(0x54a + 2*(o))
302 #define IWA(o, v) outw(0x54a + 2*(o), (v))
303 #define IMR2IRQ(bn) ((bn) - 1)
304 #define IRQ2IMR(irq) ((irq) + 1)
307 dec_1000a_intr_map(arg)
310 pcicfgregs *cfg = (pcicfgregs *)arg;
311 int device = cfg->slot;
314 * Get bit number in mystery ICU imr
316 static const signed char imrmap[][4] = {
317 # define IRQSPLIT(o) { (o), (o)+1, (o)+16, (o)+16+1 }
318 # define IRQNONE { 0, 0, 0, 0 }
319 /* 0 */ { 1, 0, 0, 0 }, /* Noritake and Pintake */
321 /* 2 */ IRQSPLIT(10),
322 /* 3 */ IRQSPLIT(12),
323 /* 4 */ IRQSPLIT(14),
324 /* 5 */ { 1, 0, 0, 0 }, /* Corelle */
325 /* 6 */ { 10, 0, 0, 0 }, /* Corelle */
327 /* 8 */ { 1, 0, 0, 0 }, /* isp behind ppb */
330 /* 11 */ IRQSPLIT(2),
331 /* 12 */ IRQSPLIT(4),
332 /* 13 */ IRQSPLIT(6),
333 /* 14 */ IRQSPLIT(8) /* Corelle */
336 if (cfg->intpin == 0) /* No IRQ used. */
338 if (!(1 <= cfg->intpin && cfg->intpin <= 4))
341 if (0 <= device && device < sizeof imrmap / sizeof imrmap[0]) {
342 imrbit = imrmap[device][cfg->intpin - 1];
344 cfg->intline = IMR2IRQ(imrbit);
348 bad: printf("dec_1000a_intr_map: can't map dev %d pin %d\n", device, cfg->intpin);
355 dec_1000a_intr_enable(irq)
358 int imrval = IRQ2IMR(irq);
359 int i = imrval >= 16;
361 IWA(i, IRA(i) | 1 << (imrval & 0xf));
367 dec_1000a_intr_disable(irq)
370 int imrval = IRQ2IMR(irq);
371 int i = imrval >= 16;
373 IWA(i, IRA(i) & ~(1 << (imrval & 0xf)));
377 dec_1000a_intr_init()
381 * Initialize mystery ICU
387 * Enable cascade interrupt.
389 dec_1000_intr_enable(2);