3 * Copyright (c) 1995, 1996, 1997 Carnegie-Mellon University.
6 * Author: Chris G. Demetriou
8 * Permission to use, copy, modify and distribute this software and
9 * its documentation is hereby granted, provided that both the copyright
10 * notice and this permission notice appear in all copies of the
11 * software, derivative works or modified versions, and any portions
12 * thereof, and that both notices appear in supporting documentation.
14 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
15 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
16 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18 * Carnegie Mellon requests users of this software to return to
20 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
21 * School of Computer Science
22 * Carnegie Mellon University
23 * Pittsburgh PA 15213-3890
25 * any improvements or extensions that they make and grant Carnegie the
26 * rights to redistribute these changes.
29 * Additional Copyright (c) 1997 by Matthew Jacob for NASA/Ames Research Center
32 * Additional Copyright (c) 1998 by Andrew Gallatin for Duke University
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/module.h>
42 #include <machine/intr.h>
44 #include <sys/termios.h>
46 #include <machine/rpb.h>
47 #include <machine/cpuconf.h>
48 #include <machine/clock.h>
49 #include <pci/pcireg.h>
50 #include <pci/pcivar.h>
51 #include <alpha/pci/ciareg.h>
52 #include <alpha/pci/ciavar.h>
58 #define CONSPEED TTYDEF_SPEED
60 static int comcnrate = CONSPEED;
62 void st550_init __P((void));
63 static void st550_cons_init __P((void));
64 static void st550_intr_init __P((void));
65 static void pyxis_intr_enable __P((int));
66 static void pyxis_intr_disable __P((int));
67 static void st550_intr_enable __P((int));
68 static void st550_intr_disable __P((int));
69 static void st550_intr_map __P((void *));
70 #define ST550_PCI_IRQ_BEGIN 8
71 #define ST550_PCI_MAX_IRQ 47
73 extern int siocnattach __P((int, int));
74 extern int siogdbattach __P((int, int));
75 extern int sccnattach __P((void));
80 platform.family = "Digital Personal Workstation (Miata)";
82 if ((platform.model = alpha_dsr_sysname()) == NULL) {
83 /* XXX Don't know the system variations, yet. */
84 platform.model = alpha_unknown_sysname();
87 platform.iobus = "cia";
88 platform.cons_init = st550_cons_init;
89 platform.pci_intr_init = st550_intr_init;
90 platform.pci_intr_map = st550_intr_map;
91 platform.pci_intr_disable = st550_intr_disable;
92 platform.pci_intr_enable = st550_intr_enable;
95 extern int comconsole;
105 siogdbattach(0x2f8, 57600);
108 ctb = (struct ctb *)(((caddr_t)hwrpb) + hwrpb->rpb_ctb_off);
110 switch (ctb->ctb_term_type) {
112 /* serial console ... */
116 * Delay to allow PROM putchars to complete.
117 * FIFO depth * character time,
118 * character time = (1000000 / (defaultrate / 10))
120 DELAY(160000000 / comcnrate);
122 if (siocnattach(0x3f8, comcnrate))
123 panic("can't init serial console");
129 /* display console ... */
134 panic("not configured to use display && keyboard console");
139 printf("ctb->ctb_term_type = 0x%lx\n", ctb->ctb_term_type);
140 printf("ctb->ctb_turboslot = 0x%lx\n", ctb->ctb_turboslot);
142 panic("consinit: unknown console type %ld\n",
150 /* This is here because we need to disable extraneous pci interrupts. */
152 for(i = ST550_PCI_IRQ_BEGIN; i <= ST550_PCI_MAX_IRQ; i++)
153 pyxis_intr_disable(i);
155 pyxis_intr_enable(2); /* enable HALT switch */
156 pyxis_intr_enable(6); /* enable timer */
157 pyxis_intr_enable(7); /* enable ISA PIC cascade */
161 st550_intr_map(void *arg)
163 pcicfgregs *cfg = (pcicfgregs *)arg;
165 /* There are two main variants of Miata: Miata 1 (Intel SIO)
166 * and Miata {1.5,2} (Cypress).
168 * The Miata 1 has a CMD PCI IDE wired to compatibility mode at
169 * slot 4 of bus 0. This variant has the Pyxis DMA bug.
171 * On the Miata 1.5 and Miata 2, the Cypress PCI-ISA bridge lives
172 * on device 7 of bus 0. This device has PCI IDE wired to
173 * compatibility mode on functions 1 and 2.
175 * There will be no interrupt mapping for these devices, so just
179 if ((hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) {
183 else if (cfg->func == 4)
186 /* Miata 1.5 or Miata 2 */
187 if (cfg->slot == 7) {
194 /* Account for the PCI interrupt offset. */
195 /* cfg->intline += ST550_PCI_IRQ_BEGIN; */
200 * The functions below were written based on a draft copy of the
204 pyxis_intr_enable(irq)
207 volatile u_int64_t temp;
210 temp = REGVAL64(PYXIS_INT_MASK);
213 temp |= ( 1L << irq );
214 REGVAL64(PYXIS_INT_MASK) = temp;
216 temp = REGVAL64(PYXIS_INT_MASK);
218 printf("pyxis_intr_enable: enabling %d, current mask= ", irq);
221 for ( i = 0; i < 61; i++)
222 if (temp & (1 << i)){
232 pyxis_intr_disable(irq)
235 volatile u_int64_t temp;
238 temp = REGVAL64(PYXIS_INT_MASK);
239 temp &= ~(1L << irq );
240 REGVAL64(PYXIS_INT_MASK) = temp;
242 temp = REGVAL64(PYXIS_INT_MASK);
244 printf("pyxis_intr_disable: disabled %d, current mask ", irq);
247 for ( i = 0; i < 61; i++)
248 if (temp & (1 << i)){
258 st550_intr_enable(irq)
261 pyxis_intr_enable(irq + ST550_PCI_IRQ_BEGIN);
265 st550_intr_disable(irq)
268 pyxis_intr_disable(irq + ST550_PCI_IRQ_BEGIN);